From ddba68605ebc7932337a6d74f30e79144ef434ac Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 16 Nov 2022 10:13:27 -0800
Subject: [PATCH] Renamed DivBusy to FDivBusyE in FPU
---
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 6 +++---
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 8 +++-----
pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 12 ++++++------
pipelined/src/fpu/fpu.sv | 2 +-
4 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index e675d3574..9bb9117c7 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -48,7 +48,7 @@ module fdivsqrt(
input logic [2:0] Funct3E, Funct3M,
input logic MDUE, W64E,
output logic DivSM,
- output logic DivBusy,
+ output logic FDivBusyE,
output logic DivDone,
output logic [`NE+1:0] QeM,
output logic [`DIVb:0] QmM
@@ -75,14 +75,14 @@ module fdivsqrt(
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
fdivsqrtfsm fdivsqrtfsm(
.clk, .reset, .FmtE, .XsE, .SqrtE,
- .DivBusy, .FDivStartE, .IDivStartE, .DivStartE, .StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
+ .FDivBusyE, .FDivStartE, .IDivStartE, .DivStartE, .StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE, .MDUE, .n,
.XInfE, .YInfE, .WZero, .SpecialCaseM);
fdivsqrtiter fdivsqrtiter(
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC),
.DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .OTFCSwap,
- .DivBusy);
+ .FDivBusyE);
fdivsqrtpostproc fdivsqrtpostproc(
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
.SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
index 03f519049..2c7a7947d 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -47,7 +47,7 @@ module fdivsqrtfsm(
input logic [`DIVBLEN:0] n,
output logic DivStartE,
output logic DivDone,
- output logic DivBusy,
+ output logic FDivBusyE,
output logic SpecialCaseM
);
@@ -60,13 +60,11 @@ module fdivsqrtfsm(
// *** start logic is presently in fctl. Make it look more like integer division start logic
// DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division
- assign DivStartE = (FDivStartE | IDivStartE); // & (state == IDLE) & ~StallM;
- //assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
+ assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
assign DivDone = (state == DONE) | (WZero & (state == BUSY));
- assign DivBusy = (state == BUSY & ~DivDone);
+ assign FDivBusyE = (state == BUSY & ~DivDone);
// Divider control signals from MDU
- //assign DivStartE = DivE & (state == IDLE) & ~StallM;
//assign DivBusyE = (state == BUSY) | DivStartE;
// terminate immediately on special cases
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
index 4df7a1472..a6c6c8bce 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -33,7 +33,7 @@
module fdivsqrtiter(
input logic clk,
input logic DivStartE,
- input logic DivBusy,
+ input logic FDivBusyE,
input logic [`NE-1:0] Xe, Ye,
input logic XZeroE, YZeroE,
input logic SqrtE,
@@ -85,8 +85,8 @@ module fdivsqrtiter(
// Residual WS/SC registers/initializaiton mux
mux2 #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, DivStartE, WSN);
mux2 #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, DivStartE, WCN);
- flopen #(`DIVb+4) wsflop(clk, DivStartE|DivBusy, WSN, WS[0]);
- flopen #(`DIVb+4) wcflop(clk, DivStartE|DivBusy, WCN, WC[0]);
+ flopen #(`DIVb+4) wsflop(clk, DivStartE|FDivBusyE, WSN, WS[0]);
+ flopen #(`DIVb+4) wcflop(clk, DivStartE|FDivBusyE, WCN, WC[0]);
// UOTFC Result U and UM registers/initialization mux
// Initialize U to 1.0 and UM to 0 for square root; U to 0 and UM to -1 for division
@@ -94,8 +94,8 @@ module fdivsqrtiter(
assign initUM = SqrtE ? 0 : {1'b1, {(`DIVb){1'b0}}};
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, DivStartE, UMux);
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, DivStartE, UMMux);
- flopen #(`DIVb+1) UReg(clk, DivStartE|DivBusy, UMux, U[0]);
- flopen #(`DIVb+1) UMReg(clk, DivStartE|DivBusy, UMMux, UM[0]);
+ flopen #(`DIVb+1) UReg(clk, DivStartE|FDivBusyE, UMux, U[0]);
+ flopen #(`DIVb+1) UMReg(clk, DivStartE|FDivBusyE, UMMux, UM[0]);
// C register/initialization mux
// Initialize C to -1 for sqrt and -R for division
@@ -103,7 +103,7 @@ module fdivsqrtiter(
assign initCUpper = SqrtE ? 2'b11 : (`RADIX == 4) ? 2'b00 : 2'b10;
assign initC = {initCUpper, {`DIVb{1'b0}}};
mux2 #(`DIVb+2) Cmux(C[`DIVCOPIES], initC, DivStartE, CMux);
- flopen #(`DIVb+2) cflop(clk, DivStartE|DivBusy, CMux, C[0]);
+ flopen #(`DIVb+2) cflop(clk, DivStartE|FDivBusyE, CMux, C[0]);
// Divisior register
flopen #(`DIVN-1) dflop(clk, DivStartE, Dpreproc, D);
diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index 2f6dcce5a..d0b4aceef 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -263,7 +263,7 @@ module fpu (
fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
- .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal
+ .StallE, .StallM, .DivSM, .FDivBusyE, .QeM,
.QmM, .DivDone(DivDoneM));
//