Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix FSM bug

Browse Source
This commit is contained in:
Matthew 2024-06-25 16:40:04 -05:00
parent a91dcd8372
commit dcff039096
2 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/debug/dm.sv
View File

@ -207,6 +207,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
if (rst) begin
DmActive <= 0;
State <= INACTIVE;
NewAcState <= AC_IDLE;
end else begin
case (State)
default : begin // INACTIVE
@ -447,7 +448,10 @@ module dm import cvw::*; #(parameter cvw_t P) (
Cycle <= Cycle + 1;
end
default:;
default : begin
AcState <= AC_IDLE;
Cycle <= Cycle;
end
endcase
end
end

1
src/fpu/fpu.sv
View File

@ -211,6 +211,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
assign FResultWM = DebugSel ? DebugFPRWriteD : FResultW;
flopenrs #(P.FLEN) FPScanReg(.clk, .reset, .en(DebugCapture), .d(FRD1D), .q(DebugFPRWriteD), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanOut));
end else begin
assign DebugScanOut = '0;
fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW),
.a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]),
.a4(RdW), .wd4(FResultW),