From dcff039096948028357c3644e5481ead0c866890 Mon Sep 17 00:00:00 2001
From: Matthew <106996253+Matthew-Otto@users.noreply.github.com>
Date: Tue, 25 Jun 2024 16:40:04 -0500
Subject: [PATCH] Fix FSM bug

---
 src/debug/dm.sv | 6 +++++-
 src/fpu/fpu.sv  | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/debug/dm.sv b/src/debug/dm.sv
index 410a47c4c..f584d7756 100644
--- a/src/debug/dm.sv
+++ b/src/debug/dm.sv
@@ -207,6 +207,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
     if (rst) begin
       DmActive <= 0;
       State <= INACTIVE;
+      NewAcState <= AC_IDLE;
     end else begin
       case (State)
         default : begin  // INACTIVE
@@ -447,7 +448,10 @@ module dm import cvw::*; #(parameter cvw_t P) (
             Cycle <= Cycle + 1;
         end
 
-        default:;
+        default : begin 
+          AcState <= AC_IDLE;
+          Cycle <= Cycle;
+        end
       endcase
     end
   end
diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
index 698b79e19..404ea7692 100755
--- a/src/fpu/fpu.sv
+++ b/src/fpu/fpu.sv
@@ -211,6 +211,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
     assign FResultWM = DebugSel ? DebugFPRWriteD : FResultW;
     flopenrs #(P.FLEN) FPScanReg(.clk, .reset, .en(DebugCapture), .d(FRD1D), .q(DebugFPRWriteD), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanOut));
   end else begin
+    assign DebugScanOut = '0;
     fregfile #(P.FLEN) fregfile (.clk, .reset, .we4(FRegWriteW),
       .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
       .a4(RdW), .wd4(FResultW),