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Revert "Non-ideal fix. Added new output from pma which indicates if the write shift should occur."

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This reverts commit 3714b2bf4a.
This commit is contained in:
Rose Thompson 2024-03-06 15:16:37 -06:00
parent a48c16c0ef
commit dce7de59a3
5 changed files with 10 additions and 13 deletions
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2
src/ifu/ifu.sv
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@ -185,7 +185,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
.TLBFlush, .TLBFlush,
.PhysicalAddress(PCPF), .PhysicalAddress(PCPF),
.TLBMiss(ITLBMissF), .TLBMiss(ITLBMissF),
.Cacheable(CacheableF), .Idempotent(), .AllowShift(), .SelTIM(SelIROM), .Cacheable(CacheableF), .Idempotent(), .SelTIM(SelIROM),
.InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(), .InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
.InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(), .InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
.LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(), .LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),

5
src/lsu/lsu.sv
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@ -119,7 +119,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic SelSpillE; // Align logic detected a spill and needs to stall logic SelSpillE; // Align logic detected a spill and needs to stall
logic CacheableM; // PMA indicates memory address is cacheable logic CacheableM; // PMA indicates memory address is cacheable
logic AllowShiftM; // PMA: indicates if WriteData should be byte shifted before going to cache or bus by offset.
logic BusCommittedM; // Bus memory operation in flight, delay interrupts logic BusCommittedM; // Bus memory operation in flight, delay interrupts
logic DCacheCommittedM; // D$ memory operation started, delay interrupts logic DCacheCommittedM; // D$ memory operation started, delay interrupts
@ -243,7 +242,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]), .PrivilegeModeW, .DisableTranslation, .VAdr(IHAdrM), .Size(LSUFunct3M[1:0]),
.PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM), .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), .TLBFlush(sfencevmaM),
.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .AllowShift(AllowShiftM), .SelTIM(SelDTIM), .PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM), .InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM),
.StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM), .StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM),
.StoreAmoPageFaultM(LSUStoreAmoPageFaultM), .StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
@ -425,7 +424,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if(MISALIGN_SUPPORT) begin if(MISALIGN_SUPPORT) begin
subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, subwordreaddouble #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM); subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .CacheableM, .IMAFWriteDataM, .LittleEndianWriteDataM);
end else begin end else begin
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM, subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);

6
src/lsu/subwordwritedouble.sv
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@ -33,7 +33,7 @@ module subwordwritedouble #(parameter LLEN) (
input logic [2:0] PAdrM, input logic [2:0] PAdrM,
input logic FpLoadStoreM, input logic FpLoadStoreM,
input logic BigEndianM, input logic BigEndianM,
input logic AllowShiftM, input logic CacheableM,
input logic [LLEN-1:0] IMAFWriteDataM, input logic [LLEN-1:0] IMAFWriteDataM,
output logic [LLEN*2-1:0] LittleEndianWriteDataM output logic [LLEN*2-1:0] LittleEndianWriteDataM
); );
@ -48,8 +48,8 @@ module subwordwritedouble #(parameter LLEN) (
// 10: PAdrM[2:0] // 10: PAdrM[2:0]
// 11: BigEndianPAdr // 11: BigEndianPAdr
// 00: 00000 // 00: 00000
// 01: 11111 // 01: 00111
mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {AllowShiftM, BigEndianM}, PAdrSwap); mux4 #(5) OffsetMux(5'b0, 5'b11111, {2'b0, PAdrM}, BigEndianPAdr, {CacheableM, BigEndianM}, PAdrSwap);
//assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM}; //assign PAdrSwap = BigEndianM ? BigEndianPAdr : {2'b0, PAdrM};
/* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHEXPAND */
/* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHTRUNC */

3
src/mmu/mmu.sv
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@ -49,7 +49,6 @@ module mmu import cvw::*; #(parameter cvw_t P,
output logic TLBMiss, // Miss TLB output logic TLBMiss, // Miss TLB
output logic Cacheable, // PMA indicates memory address is cachable output logic Cacheable, // PMA indicates memory address is cachable
output logic Idempotent, // PMA indicates memory address is idempotent output logic Idempotent, // PMA indicates memory address is idempotent
output logic AllowShift, // PMA indicates if WriteData should be byte shifted before going to cache or bus by offset
output logic SelTIM, // Select a tightly integrated memory output logic SelTIM, // Select a tightly integrated memory
// Faults // Faults
output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
@ -113,7 +112,7 @@ module mmu import cvw::*; #(parameter cvw_t P,
pmachecker #(P) pmachecker(.PhysicalAddress, .Size, .CMOpM, pmachecker #(P) pmachecker(.PhysicalAddress, .Size, .CMOpM,
.AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PBMemoryType, .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PBMemoryType,
.Cacheable, .Idempotent, .AllowShift, .SelTIM, .Cacheable, .Idempotent, .SelTIM,
.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM); .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
if (P.PMP_ENTRIES > 0) begin : pmp if (P.PMP_ENTRIES > 0) begin : pmp

5
src/mmu/pmachecker.sv
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@ -1,4 +1,4 @@
////////////////////////////////////////// ///////////////////////////////////////////
// pmachecker.sv // pmachecker.sv
// //
// Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021 // Written: tfleming@hmc.edu & jtorrey@hmc.edu 20 April 2021
@ -38,7 +38,7 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
input logic WriteAccessM, // Write access input logic WriteAccessM, // Write access
input logic ReadAccessM, // Read access input logic ReadAccessM, // Read access
input logic [1:0] PBMemoryType, // PBMT field of PTE during TLB hit, or 00 otherwise input logic [1:0] PBMemoryType, // PBMT field of PTE during TLB hit, or 00 otherwise
output logic Cacheable, Idempotent, AllowShift, SelTIM, output logic Cacheable, Idempotent, SelTIM,
output logic PMAInstrAccessFaultF, output logic PMAInstrAccessFaultF,
output logic PMALoadAccessFaultM, output logic PMALoadAccessFaultM,
output logic PMAStoreAmoAccessFaultM output logic PMAStoreAmoAccessFaultM
@ -61,7 +61,6 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
// Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable // Only non-core RAM/ROM memory regions are cacheable. PBMT can override cachable; NC and IO are uncachable
assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-cachable assign CacheableRegion = SelRegions[3] | SelRegions[4] | SelRegions[5]; // exclusion-tag: unused-cachable
assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0; assign Cacheable = (PBMemoryType == 2'b00) ? CacheableRegion : 0;
assign AllowShift = SelRegions[1] | SelRegions[2] | SelRegions[3] | SelRegions[5] | SelRegions[6];
// Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly
// I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent // I/O is nonidempotent. PBMT can override PMA; NC is idempotent and IO is non-idempotent