Clean up tabs

pipelined/src/fpu/fcvt.sv

@@ -56,8 +56,6 @@ module fcvt (
   //                            bit 2              bit 1                   bit 0
   //      for example: signed long -> single floating point has the OpCode 101
 
-
-
   logic [`FMTBITS-1:0]    OutFmt;     // format of the output
   logic [`XLEN-1:0]       PosInt;     // the positive integer input
   logic [`XLEN-1:0]       TrimInt;    // integer trimmed to the correct size

pipelined/src/fpu/fhazard.sv

@@ -73,7 +73,6 @@ module fhazard(
       if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM
       // if the needed value is in the writeback stage
     end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
-
   end 
 
 endmodule

pipelined/src/fpu/fma/fmaadd.sv

@@ -43,6 +43,7 @@ module fmaadd(
   output logic [`NE+1:0]      Se,         // sum's exponent
   output logic [3*`NF+3:0]    Sm          // the positive sum
 );
+
   logic [3*`NF+3:0]    PreSum, NegPreSum; // possibly negitive sum
   logic                NegSum;            // was the sum negitive
 

pipelined/src/fpu/fma/fmaalign.sv

@@ -62,9 +62,7 @@ module fmaalign(
   assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero;
   assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(3));
 
-    always_comb
-        begin
-        
+  always_comb begin
     // If the product is too small to effect the sum, kill the product
 
     //          |   53'b0    |  106'b(product)  | 1'b0 |

pipelined/src/fpu/fma/fmaexpadd.sv

@@ -34,7 +34,7 @@ module fmaexpadd(
   output logic [`NE+1:0]      Pe              // product's exponent B^(1023)NE+2
 );
 
-   logic PZero; // is the product zero
+  logic                       PZero;          // is the product zero?
   
   // kill the exponent if the product is zero - either X or Y is 0
   assign PZero = XZero | YZero;

pipelined/src/fpu/fma/fmalza.sv

@@ -7,6 +7,7 @@
 // Purpose: Leading Zero Anticipator
 // 
 // Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14)
+//    See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -28,7 +29,7 @@
 
 `include "wally-config.vh"
 
-module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
+module fmalza #(WIDTH) ( 
   input logic [WIDTH-1:0]             A,      // addend
   input logic [2*`NF+1:0]             Pm,     // product
   input logic 		                    Cin,    // carry in
@@ -36,24 +37,25 @@ module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and d
   output logic [$clog2(WIDTH+1)-1:0]  SCnt    // normalization shift count for the positive result
 ); 
 
-   logic [WIDTH:0] 	  F;
-   logic [WIDTH-1:0]  B, P, Guard, K;
-    logic [WIDTH-1:0] Pp1, Gm1, Km1;
+  logic [WIDTH:0] 	                  F;              // most significant bit of F indicates leading digit
+  logic [WIDTH-1:0]                   B;              // zero-extended product with same size as aligned A
+  logic [WIDTH-1:0]                   P, G, K;        // propagate, generate, kill for each column
+  logic [WIDTH-1:0]                   Pp1, Gm1, Km1;  // propagate shifted right by 1, generate/kill shifted left 1
 
   assign B = {{(`NF+1){1'b0}}, Pm, 1'b0}; // Zero extend product
 
   assign P = A^B;
-    assign Guard = A&B;
+  assign G = A&B;
   assign K= ~A&~B;
 
-   assign Pp1 = {sub, P[WIDTH-1:1]};
-   assign Gm1 = {Guard[WIDTH-2:0], Cin};
-   assign Km1 = {K[WIDTH-2:0], ~Cin};
+  assign Pp1 = {sub, P[WIDTH-1:1]};   // shift P right by 1 (for P_i+1) , use subtract flag in most significant bit
+  assign Gm1 = {G[WIDTH-2:0], Cin};   // shift G left by 1 (for G_i-1) and bring in Cin
+  assign Km1 = {K[WIDTH-2:0], ~Cin};  // shift K left by 1 (for K_i-1) and bring in Cin
   
   // Apply function to determine Leading pattern
-    //      - note: the paper linked above uses the numbering system where 0 is the most significant bit
+  //      - note: Schmookler01 uses the numbering system where 0 is the most significant bit
   assign F[WIDTH] = ~sub&P[WIDTH-1];
-    assign F[WIDTH-1:0] = (Pp1&(Guard&~Km1 | K&~Gm1)) | (~Pp1&(K&~Km1 | Guard&~Gm1));
+  assign F[WIDTH-1:0] = (Pp1&(G&~Km1 | K&~Gm1)) | (~Pp1&(K&~Km1 | G&~Gm1));
 
   lzc #(WIDTH+1) lzc (.num(F), .ZeroCnt(SCnt));
 endmodule

pipelined/src/fpu/fma/fmamult.sv

@@ -32,6 +32,7 @@ module fmamult(
   input  logic [`NF:0]     Xm, Ym, // x and y significand
   output logic [2*`NF+1:0] Pm      // product's significand
 );
+
   assign Pm = Xm * Ym;
 endmodule
 

pipelined/src/fpu/fma/fmasign.sv

@@ -36,12 +36,7 @@ module fmasign(
   output logic        InvA        // Effective subtraction: invert addend
 );
 
-    // Calculate the product's sign
-    //      Negate product's sign if FNMADD or FNMSUB
-    // flip is negation opperation
-    assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]);
-    // flip addend sign for subtraction
-    assign As = Zs^OpCtrl[0];
-   // Effective subtraction when product and addend have opposite signs
-    assign InvA = As ^ Ps;
+  assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]); // product sign.  Negate for FMNADD or FNMSUB
+  assign As = Zs^OpCtrl[0];                     // flip addend sign for subtraction
+  assign InvA = As ^ Ps;                        // Effective subtraction when product and addend have opposite signs
 endmodule

pipelined/src/fpu/fsgninj.sv

@@ -52,10 +52,8 @@ module fsgninj (
 	
   if (`FPSIZES == 1)
 		assign SgnRes = {ResSgn, X[`FLEN-2:0]};
-
   else if (`FPSIZES == 2)
 		assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]};
-
   else if (`FPSIZES == 3) begin
 		logic [2:0] SgnBits;
     always_comb
@@ -66,8 +64,6 @@ module fsgninj (
         default: SgnBits = {3{1'bx}};
       endcase
 		assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]};
-        
-
 	end else if (`FPSIZES == 4) begin
 		logic [3:0] SgnBits;
     always_comb

pipelined/src/fpu/postproc/cvtshiftcalc.sv

@@ -40,8 +40,8 @@ module cvtshiftcalc(
   output logic                    CvtResUf,           // does the cvt result unerflow
   output logic [`CVTLEN+`NF:0]    CvtShiftIn          // number to be shifted
 );
-    logic [$clog2(`NF):0] ResNegNF; // the result's fraction length negated (-NF)
 
+  logic [$clog2(`NF):0]           ResNegNF;           // the result's fraction length negated (-NF)
 
   ///////////////////////////////////////////////////////////////////////////
   // shifter

pipelined/src/fpu/postproc/divshiftcalc.sv

@@ -36,6 +36,7 @@ module divshiftcalc(
   output logic                        DivResSubnorm,      // is the divsqrt result subnormal
   output logic                        DivSubnormShiftPos  // is the subnormal shift amount positive
 );
+
   logic [`LOGNORMSHIFTSZ-1:0]         NormShift;          // normalized result shift amount
   logic [`LOGNORMSHIFTSZ-1:0]         DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive)
   logic [`NE+1:0]                     DivSubnormShift;    // subnormal result shift amount

pipelined/src/fpu/postproc/flags.sv

@@ -62,6 +62,7 @@ module flags(
   output logic                IntInvalid,             // invalid integer result to select
   output logic [4:0]          PostProcFlg             // flags
 );
+
   logic               SigNaN;         // is an input a signaling NaN
   logic               Inexact;        // final inexact flag
   logic               FpInexact;      // floating point inexact flag

pipelined/src/fpu/postproc/fmashiftcalc.sv

@@ -55,11 +55,9 @@ module fmashiftcalc(
   //convert the sum's exponent into the proper percision
   if (`FPSIZES == 1) begin
     assign NormSumExp = PreNormSumExp;
-
   end else if (`FPSIZES == 2) begin
     assign BiasCorr = Fmt ? (`NE+2)'(0) : (`NE+2)'(`BIAS1-`BIAS);
     assign NormSumExp = PreNormSumExp+BiasCorr;
-        
   end else if (`FPSIZES == 3) begin
     always_comb begin
         case (Fmt)
@@ -70,7 +68,6 @@ module fmashiftcalc(
         endcase
     end
     assign NormSumExp = PreNormSumExp+BiasCorr;
-
   end else if (`FPSIZES == 4) begin
     always_comb begin
         case (Fmt)
@@ -81,7 +78,6 @@ module fmashiftcalc(
         endcase
     end
     assign NormSumExp = PreNormSumExp+BiasCorr;
-
   end
   
   // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen) & ~FmaSZero
@@ -90,7 +86,6 @@ module fmashiftcalc(
     assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
     assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2));
     assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
-
   end else if (`FPSIZES == 2) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
     assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
@@ -98,7 +93,6 @@ module fmashiftcalc(
     assign Sum1LEZ  = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS1));
     assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF1-2+`BIAS-`BIAS1)) | ~|PreNormSumExp;
     assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
-
   end else if (`FPSIZES == 3) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
     assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
@@ -115,7 +109,6 @@ module fmashiftcalc(
         default: FmaPreResultSubnorm = 1'bx;
       endcase
     end
-
   end else if (`FPSIZES == 4) begin
     logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
     assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
@@ -134,14 +127,11 @@ module fmashiftcalc(
         2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL & ~FmaSZero;
       endcase
     end
-
   end
 
   // set and calculate the shift input and amount
   //  - shift once if killing a product and the result is subnormal
   assign FmaShiftIn = {2'b0, FmaSm};
-    if (`FPSIZES == 1)
-        assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2): FmaSCnt+1;
-    else
-        assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2)+BiasCorr[$clog2(3*`NF+5)-1:0]: FmaSCnt+1;
+  if (`FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2): FmaSCnt+1;
+  else               assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2)+BiasCorr[$clog2(3*`NF+5)-1:0]: FmaSCnt+1;
 endmodule

pipelined/src/fpu/postproc/normshift.sv

@@ -77,6 +77,6 @@ module normshift(
   input  logic [`NORMSHIFTSZ-1:0]     ShiftIn,    // number to be shifted
   output logic [`NORMSHIFTSZ-1:0]     Shifted     // shifted result
 );
-    assign Shifted = ShiftIn << ShiftAmt;
    
+  assign Shifted = ShiftIn << ShiftAmt;
 endmodule

pipelined/src/fpu/postproc/round.sv

@@ -66,6 +66,7 @@ module round(
   output logic                    Plus1,              // do you add one to the final result
   output logic                    Round, Guard        // bits needed to calculate rounding
 );
+
   logic           UfCalcPlus1;        // calculated plus one for unbounded exponent
   logic           NormSticky;         // normalized sum's sticky bit
   logic [`NF-1:0] RoundFrac;          // rounded fraction

pipelined/src/fpu/postproc/shiftcorrection.sv

@@ -25,6 +25,7 @@
 // either express or implied. See the License for the specific language governing permissions 
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+
 `include "wally-config.vh"
 
 module shiftcorrection(
@@ -72,6 +73,7 @@ module shiftcorrection(
     if(FmaOp)                       Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+4){1'b0}}};
     else if (DivOp&~DivResSubnorm)  Mf = CorrQmShifted;
     else                            Mf = Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`CORRSHIFTSZ];
+    
   // Determine sum's exponent
   //  main exponent issues: 
   //      - LZA was one too large

pipelined/src/fpu/postproc/specialcase.sv

@@ -63,6 +63,7 @@ module specialcase(
   output logic [`FLEN-1:0]    PostProcRes,// final result
   output logic [`XLEN-1:0]    FCvtIntRes  // final integer result
 );
+
   logic [`FLEN-1:0]   XNaNRes;    // X is NaN result
   logic [`FLEN-1:0]   YNaNRes;    // Y is NaN result
   logic [`FLEN-1:0]   ZNaNRes;    // Z is NaN result
@@ -80,7 +81,6 @@ module specialcase(
   //                output infinity if the input is infinity
   assign OfResMax = (~InfIn|(IntToFp&CvtOp))&~DivByZero&((Frm[1:0]==2'b01) | (Frm[1:0]==2'b10&~Rs) | (Frm[1:0]==2'b11&Rs));
 
-
   // select correct outputs for special cases
   if (`FPSIZES == 1) begin
       //NaN res selection depending on standard
@@ -238,10 +238,6 @@ module specialcase(
           endcase
   end
 
-    
-
-
-
   // determine if you shoould kill the res - Cvt
   //      - do so if the res underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0
   //      - dont set to zero if fp input is zero but not using the fp input
@@ -251,7 +247,6 @@ module specialcase(
   // calculate if the overflow result should be selected
   assign SelOfRes = Overflow|DivByZero|(InfIn&~(YInf&DivOp));
   
-    
   // output infinity with result sign if divide by zero
   if(`IEEE754)
     always_comb
@@ -269,11 +264,6 @@ module specialcase(
       else if(KillRes)            PostProcRes = UfRes;
       else                        PostProcRes = NormRes;
 
-
-
-
-
-
   ///////////////////////////////////////////////////////////////////////////////////////
   // integer result selection        
   ///////////////////////////////////////////////////////////////////////////////////////        

pipelined/src/lsu/atomic.sv

@@ -39,16 +39,18 @@ module atomic (
   input logic                IgnoreRequest,
   output logic [`XLEN-1:0]   IMAWriteDataM,
   output logic               SquashSCW,
-  output logic [1:0]         LSURWM);
+  output logic [1:0]         LSURWM
+);
 
   logic [`XLEN-1:0]          AMOResult;
   logic                      MemReadM;
 
   amoalu amoalu(.srca(ReadDataM), .srcb(IHWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), 
                 .result(AMOResult));
+
   mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM);
   assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
-  lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM,
-    .SquashSCW, .LSURWM);
+
+  lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
 
 endmodule  

pipelined/src/lsu/endianswap.sv

@@ -31,7 +31,8 @@
 module endianswap #(parameter LEN=`XLEN) (
   input  logic            BigEndianM,
   input  logic [LEN-1:0]  a,
-  output logic [LEN-1:0] y); 
+  output logic [LEN-1:0]  y
+); 
 
   if(LEN == 128) begin
     always_comb 

pipelined/src/lsu/lrsc.sv

@@ -27,8 +27,7 @@
 
 `include "wally-config.vh"
 
-module lrsc
-  (
+module lrsc(
   input  logic                clk, reset,
   input  logic                StallW,
   input  logic                MemReadM,
@@ -38,6 +37,7 @@ module lrsc
   input  logic [`PA_BITS-1:0] PAdrM,  // from mmu to dcache
   output logic                SquashSCW
 );
+
   // Handle atomic load reserved / store conditional
   logic [`PA_BITS-1:2] 			  ReservationPAdrW;
   logic 						          ReservationValidM, ReservationValidW; 
@@ -55,6 +55,7 @@ module lrsc
     else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc
     else ReservationValidM = ReservationValidW; // otherwise don't change valid
   end
+  
   flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
   flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
   flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);

pipelined/src/lsu/subwordwrite.sv

@@ -29,7 +29,8 @@
 module subwordwrite (
   input logic [2:0]          LSUFunct3M,
   input logic [`LLEN-1:0]    IMAFWriteDataM,
-  output logic [`LLEN-1:0]   LittleEndianWriteDataM);
+  output logic [`LLEN-1:0]   LittleEndianWriteDataM
+);
 
   // Replicate data for subword writes
   if (`LLEN == 128) begin:sww

pipelined/src/lsu/swbytemask.sv

@@ -29,7 +29,8 @@
 module swbytemask #(parameter WORDLEN = `XLEN)(
   input logic [2:0]              Size,
   input logic [$clog2(WORDLEN/8)-1:0] Adr,
-  output logic [WORDLEN/8-1:0]   ByteMask);
+  output logic [WORDLEN/8-1:0]   ByteMask
+);
   
   assign ByteMask = ((2**(2**Size))-1) << Adr;
 

pipelined/src/uncore/uartPC16550D.sv

@@ -11,7 +11,7 @@
 //
 //  Compatible with most of PC16550D with the following known exceptions:
 //   Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1
-//   Timeout not ye implemented***
+//   Timeout not yet implemented***
 // 
 // Documentation: RISC-V System on Chip Design Chapter 15
 //