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fix E_SUPPORTED inversion bug

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Matthew 2024-06-04 19:08:17 -05:00
parent be0199fb3c
commit dc065429fc
6 changed files with 83 additions and 83 deletions
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36
src/debug/dm.sv
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@ -26,31 +26,31 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module dm import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic rst,
input logic clk,
input logic rst,
// External JTAG signals
input logic tck,
input logic tdi,
input logic tms,
output logic tdo,
input logic tck,
input logic tdi,
input logic tms,
output logic tdo,
// Platform reset signal
output logic NdmReset,
output logic NdmReset,
// Core hazard signal
output logic DebugStall,
output logic DebugStall,
// Scan Chain
output logic ScanEn,
input logic ScanIn,
output logic ScanOut,
output logic GPRSel,
output logic DebugCapture,
output logic DebugGPRUpdate,
output logic [P.E_SUPPORTED+3:0] GPRAddr,
output logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
output logic ScanEn,
input logic ScanIn,
output logic ScanOut,
output logic GPRSel,
output logic DebugCapture,
output logic DebugGPRUpdate,
output logic [4:0] GPRAddr,
output logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
);
`include "debug.vh"

24
src/debug/rad.sv
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@ -26,15 +26,15 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module rad import cvw::*; #(parameter cvw_t P) (
input logic [2:0] AarSize,
input logic [15:0] Regno,
output logic GPRRegNo,
output logic [9:0] ScanChainLen,
output logic [9:0] ShiftCount,
output logic InvalidRegNo,
output logic RegReadOnly,
output logic [P.E_SUPPORTED+3:0] GPRAddr,
output logic [P.XLEN-1:0] ARMask
input logic [2:0] AarSize,
input logic [15:0] Regno,
output logic GPRRegNo,
output logic [9:0] ScanChainLen,
output logic [9:0] ShiftCount,
output logic InvalidRegNo,
output logic RegReadOnly,
output logic [4:0] GPRAddr,
output logic [P.XLEN-1:0] ARMask
);
`include "debug.vh"
@ -68,9 +68,9 @@ module rad import cvw::*; #(parameter cvw_t P) (
assign ScanChainLen = GPRRegNo ? GPRCHAINLEN : SCANCHAINLEN;
if (P.E_SUPPORTED)
assign GPRAddr = Regno[4:0];
else
assign GPRAddr = Regno[3:0];
else
assign GPRAddr = Regno[4:0];
// Register decoder
always_comb begin
@ -84,7 +84,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
end
16'h101? : begin
ShiftCount = P.XLEN - 1;
InvalidRegNo = ~P.E_SUPPORTED;
InvalidRegNo = P.E_SUPPORTED;
GPRRegNo = 1;
end
`MISA_REGNO : begin

20
src/ieu/datapath.sv
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@ -75,16 +75,16 @@ module datapath import cvw::*; #(parameter cvw_t P) (
input logic [4:0] RdW, // Destination register
// Hazard Unit signals
// Debug scan chain
input logic DebugScanEn,
input logic DebugScanIn,
output logic DebugScanOut,
input logic GPRSel,
input logic DebugCapture,
input logic DebugGPRUpdate,
input logic [P.E_SUPPORTED+3:0] GPRAddr,
input logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
input logic DebugScanEn,
input logic DebugScanIn,
output logic DebugScanOut,
input logic GPRSel,
input logic DebugCapture,
input logic DebugGPRUpdate,
input logic [4:0] GPRAddr,
input logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
);
// Fetch stage signals

14
src/ieu/ieu.sv
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@ -84,13 +84,13 @@ module ieu import cvw::*; #(parameter cvw_t P) (
input logic DebugScanIn,
output logic DebugScanOut,
// GPR debug scan chain
input logic GPRSel,
input logic DebugCapture,
input logic DebugGPRUpdate,
input logic [P.E_SUPPORTED+3:0] GPRAddr,
input logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
input logic GPRSel,
input logic DebugCapture,
input logic DebugGPRUpdate,
input logic [4:0] GPRAddr,
input logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
);
logic [2:0] ImmSrcD; // Select type of immediate extension

48
src/wally/wallypipelinedcore.sv
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@ -33,30 +33,30 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
// Bus Interface
input logic [P.AHBW-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [P.PA_BITS-1:0] HADDR,
output logic [P.AHBW-1:0] HWDATA,
output logic [P.XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK,
input logic DebugStall,
// Debug scan chain
input logic DebugScanEn,
input logic DebugScanIn,
output logic DebugScanOut,
input logic GPRSel,
input logic DebugCapture,
input logic DebugGPRUpdate,
input logic [P.E_SUPPORTED+3:0] GPRAddr,
input logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
input logic [P.AHBW-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [P.PA_BITS-1:0] HADDR,
output logic [P.AHBW-1:0] HWDATA,
output logic [P.XLEN/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK,
input logic DebugStall,
// Debug scan chain
input logic DebugScanEn,
input logic DebugScanIn,
output logic DebugScanOut,
input logic GPRSel,
input logic DebugCapture,
input logic DebugGPRUpdate,
input logic [4:0] GPRAddr,
input logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
);
logic StallF, StallD, StallE, StallM, StallW;

24
src/wally/wallypipelinedsoc.sv
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@ -74,18 +74,18 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
logic MExtInt,SExtInt; // from PLIC
// Debug Module signals
logic NdmReset;
logic DebugStall;
logic ScanEn;
logic ScanIn;
logic ScanOut;
logic GPRSel;
logic DebugCapture;
logic DebugGPRUpdate;
logic [P.E_SUPPORTED+3:0] GPRAddr;
logic GPRScanEn;
logic GPRScanIn;
logic GPRScanOut;
logic NdmReset;
logic DebugStall;
logic ScanEn;
logic ScanIn;
logic ScanOut;
logic GPRSel;
logic DebugCapture;
logic DebugGPRUpdate;
logic [4:0] GPRAddr;
logic GPRScanEn;
logic GPRScanIn;
logic GPRScanOut;
// synchronize reset to SOC clock domain
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));