From dc065429fc148651595a89bb648de39fa8005665 Mon Sep 17 00:00:00 2001 From: Matthew <106996253+Matthew-Otto@users.noreply.github.com> Date: Tue, 4 Jun 2024 19:08:17 -0500 Subject: [PATCH] fix E_SUPPORTED inversion bug --- src/debug/dm.sv | 36 ++++++++++++------------- src/debug/rad.sv | 24 ++++++++--------- src/ieu/datapath.sv | 20 +++++++------- src/ieu/ieu.sv | 14 +++++----- src/wally/wallypipelinedcore.sv | 48 ++++++++++++++++----------------- src/wally/wallypipelinedsoc.sv | 24 ++++++++--------- 6 files changed, 83 insertions(+), 83 deletions(-) diff --git a/src/debug/dm.sv b/src/debug/dm.sv index 38f31d263..4414f5684 100644 --- a/src/debug/dm.sv +++ b/src/debug/dm.sv @@ -26,31 +26,31 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module dm import cvw::*; #(parameter cvw_t P) ( - input logic clk, - input logic rst, + input logic clk, + input logic rst, // External JTAG signals - input logic tck, - input logic tdi, - input logic tms, - output logic tdo, + input logic tck, + input logic tdi, + input logic tms, + output logic tdo, // Platform reset signal - output logic NdmReset, + output logic NdmReset, // Core hazard signal - output logic DebugStall, + output logic DebugStall, // Scan Chain - output logic ScanEn, - input logic ScanIn, - output logic ScanOut, - output logic GPRSel, - output logic DebugCapture, - output logic DebugGPRUpdate, - output logic [P.E_SUPPORTED+3:0] GPRAddr, - output logic GPRScanEn, - input logic GPRScanIn, - output logic GPRScanOut + output logic ScanEn, + input logic ScanIn, + output logic ScanOut, + output logic GPRSel, + output logic DebugCapture, + output logic DebugGPRUpdate, + output logic [4:0] GPRAddr, + output logic GPRScanEn, + input logic GPRScanIn, + output logic GPRScanOut ); `include "debug.vh" diff --git a/src/debug/rad.sv b/src/debug/rad.sv index 5af74ef79..3cfff82a6 100644 --- a/src/debug/rad.sv +++ b/src/debug/rad.sv @@ -26,15 +26,15 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module rad import cvw::*; #(parameter cvw_t P) ( - input logic [2:0] AarSize, - input logic [15:0] Regno, - output logic GPRRegNo, - output logic [9:0] ScanChainLen, - output logic [9:0] ShiftCount, - output logic InvalidRegNo, - output logic RegReadOnly, - output logic [P.E_SUPPORTED+3:0] GPRAddr, - output logic [P.XLEN-1:0] ARMask + input logic [2:0] AarSize, + input logic [15:0] Regno, + output logic GPRRegNo, + output logic [9:0] ScanChainLen, + output logic [9:0] ShiftCount, + output logic InvalidRegNo, + output logic RegReadOnly, + output logic [4:0] GPRAddr, + output logic [P.XLEN-1:0] ARMask ); `include "debug.vh" @@ -68,9 +68,9 @@ module rad import cvw::*; #(parameter cvw_t P) ( assign ScanChainLen = GPRRegNo ? GPRCHAINLEN : SCANCHAINLEN; if (P.E_SUPPORTED) - assign GPRAddr = Regno[4:0]; - else assign GPRAddr = Regno[3:0]; + else + assign GPRAddr = Regno[4:0]; // Register decoder always_comb begin @@ -84,7 +84,7 @@ module rad import cvw::*; #(parameter cvw_t P) ( end 16'h101? : begin ShiftCount = P.XLEN - 1; - InvalidRegNo = ~P.E_SUPPORTED; + InvalidRegNo = P.E_SUPPORTED; GPRRegNo = 1; end `MISA_REGNO : begin diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 4bddcf8cd..f88486fd0 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -75,16 +75,16 @@ module datapath import cvw::*; #(parameter cvw_t P) ( input logic [4:0] RdW, // Destination register // Hazard Unit signals // Debug scan chain - input logic DebugScanEn, - input logic DebugScanIn, - output logic DebugScanOut, - input logic GPRSel, - input logic DebugCapture, - input logic DebugGPRUpdate, - input logic [P.E_SUPPORTED+3:0] GPRAddr, - input logic GPRScanEn, - input logic GPRScanIn, - output logic GPRScanOut + input logic DebugScanEn, + input logic DebugScanIn, + output logic DebugScanOut, + input logic GPRSel, + input logic DebugCapture, + input logic DebugGPRUpdate, + input logic [4:0] GPRAddr, + input logic GPRScanEn, + input logic GPRScanIn, + output logic GPRScanOut ); // Fetch stage signals diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index ecbb95e6f..373954137 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -84,13 +84,13 @@ module ieu import cvw::*; #(parameter cvw_t P) ( input logic DebugScanIn, output logic DebugScanOut, // GPR debug scan chain - input logic GPRSel, - input logic DebugCapture, - input logic DebugGPRUpdate, - input logic [P.E_SUPPORTED+3:0] GPRAddr, - input logic GPRScanEn, - input logic GPRScanIn, - output logic GPRScanOut + input logic GPRSel, + input logic DebugCapture, + input logic DebugGPRUpdate, + input logic [4:0] GPRAddr, + input logic GPRScanEn, + input logic GPRScanIn, + output logic GPRScanOut ); logic [2:0] ImmSrcD; // Select type of immediate extension diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 31665e351..f4ac7e29e 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -33,30 +33,30 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, // Bus Interface - input logic [P.AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [P.PA_BITS-1:0] HADDR, - output logic [P.AHBW-1:0] HWDATA, - output logic [P.XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, - input logic DebugStall, - // Debug scan chain - input logic DebugScanEn, - input logic DebugScanIn, - output logic DebugScanOut, - input logic GPRSel, - input logic DebugCapture, - input logic DebugGPRUpdate, - input logic [P.E_SUPPORTED+3:0] GPRAddr, - input logic GPRScanEn, - input logic GPRScanIn, - output logic GPRScanOut + input logic [P.AHBW-1:0] HRDATA, + input logic HREADY, HRESP, + output logic HCLK, HRESETn, + output logic [P.PA_BITS-1:0] HADDR, + output logic [P.AHBW-1:0] HWDATA, + output logic [P.XLEN/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, + input logic DebugStall, + // Debug scan chain + input logic DebugScanEn, + input logic DebugScanIn, + output logic DebugScanOut, + input logic GPRSel, + input logic DebugCapture, + input logic DebugGPRUpdate, + input logic [4:0] GPRAddr, + input logic GPRScanEn, + input logic GPRScanIn, + output logic GPRScanOut ); logic StallF, StallD, StallE, StallM, StallW; diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 8739a60f2..80e63a680 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -74,18 +74,18 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( logic MExtInt,SExtInt; // from PLIC // Debug Module signals - logic NdmReset; - logic DebugStall; - logic ScanEn; - logic ScanIn; - logic ScanOut; - logic GPRSel; - logic DebugCapture; - logic DebugGPRUpdate; - logic [P.E_SUPPORTED+3:0] GPRAddr; - logic GPRScanEn; - logic GPRScanIn; - logic GPRScanOut; + logic NdmReset; + logic DebugStall; + logic ScanEn; + logic ScanIn; + logic ScanOut; + logic GPRSel; + logic DebugCapture; + logic DebugGPRUpdate; + logic [4:0] GPRAddr; + logic GPRScanEn; + logic GPRScanIn; + logic GPRScanOut; // synchronize reset to SOC clock domain synchronizer resetsync(.clk, .d(reset_ext), .q(reset));