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added in the CSR name for stimecmp(h)

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Kip Macsai-Goren 2023-03-04 15:53:03 -08:00
parent ab6b953a4b
commit db6caedfec
2 changed files with 6 additions and 6 deletions
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8
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -145,8 +145,8 @@ cause_s_time_interrupt:
bgtu t3, t2, nowrap_s // check new time exceeds current time (no wraparound) bgtu t3, t2, nowrap_s // check new time exceeds current time (no wraparound)
addi t6, t6, 1 // if wrap, increment most significant word addi t6, t6, 1 // if wrap, increment most significant word
nowrap_s: nowrap_s:
csrw 0x14D, t3 // store into STIMECMP csrw stimecmp, t3 // store into STIMECMP
csrw 0x15D, t6 // store into STIMECMPH csrw stimecmph, t6 // store into STIMECMPH
time_loop_s: time_loop_s:
addi a3, a3, -1 addi a3, a3, -1
bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
@ -558,8 +558,8 @@ time_interrupt_\MODE\():
li t2, 0xFFFFFFFF li t2, 0xFFFFFFFF
sw t2, 0(t0) // reset interrupt by setting mtimecmp to max sw t2, 0(t0) // reset interrupt by setting mtimecmp to max
//sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max //sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max
csrw 0x14D, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH. csrw stimecmp, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH.
csrw 0x15D, t2 csrw stimecmph, t2
li t0, 0x20 li t0, 0x20

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
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@ -145,7 +145,7 @@ cause_s_time_interrupt:
lw t2, 0(t5) // low word of MTIME lw t2, 0(t5) // low word of MTIME
lw t6, 4(t5) // high word of MTIME lw t6, 4(t5) // high word of MTIME
add t3, t2, t3 // add desired offset to the current time add t3, t2, t3 // add desired offset to the current time
csrw 0x14D, t3 // store into most significant word of STIMECMP csrw stimecmp, t3 // store into most significant word of STIMECMP
time_loop_s: time_loop_s:
addi a3, a3, -1 addi a3, a3, -1
bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt
@ -548,7 +548,7 @@ time_interrupt_\MODE\():
la t0, 0x02004000 // MTIMECMP register in CLINT la t0, 0x02004000 // MTIMECMP register in CLINT
li t2, 0xFFFFFFFF li t2, 0xFFFFFFFF
sd t2, 0(t0) // reset interrupt by setting mtimecmp to max sd t2, 0(t0) // reset interrupt by setting mtimecmp to max
csrw 0x14D, t2 // reset stime interrupts by doing the same. csrw stimecmp, t2 // reset stime interrupts by doing the same.
li t0, 0x20 li t0, 0x20
csrc \MODE\()ip, t0 csrc \MODE\()ip, t0