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Partially sd card read on fpga.

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This commit is contained in:
Ross Thompson 2021-09-30 11:23:09 -05:00
parent 99070127d8
commit db18aac9af
9 changed files with 666 additions and 691 deletions
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2
wally-pipelined/regression/wally-pipelined-fpga.do
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@ -40,7 +40,7 @@ vsim workopt -fsmdebug
#profile on #profile on
do wave.do do fpga-wave.do
add log -r /* add log -r /*
-- Run the Simulation -- Run the Simulation

1088
wally-pipelined/regression/wave.do
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File diff suppressed because it is too large Load Diff

2
wally-pipelined/src/sdc/SDC.sv
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@ -337,7 +337,7 @@ module SDC
.o_ERROR_CODE_Q(ErrorCode), .o_ERROR_CODE_Q(ErrorCode),
.o_FATAL_ERROR(FatalError), .o_FATAL_ERROR(FatalError),
.i_COUNT_IN_MAX(-8'd62), .i_COUNT_IN_MAX(-8'd62),
.LIMIT_SD_TIMERS(1'b1)); // *** must change this to 0 for real hardware. .LIMIT_SD_TIMERS(1'b0)); // *** must change this to 0 for real hardware.
endmodule endmodule

104
wally-pipelined/src/sdc/sd_cmd_fsm.sv
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@ -33,76 +33,76 @@ module sd_cmd_fsm
input logic i_RST, // reset FSM, input logic i_RST, // reset FSM,
// MUST COME OUT OF RESET // MUST COME OUT OF RESET
// SYNCHRONIZED TO THE 1.2 GHZ CLOCK! // SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
output logic o_TIMER_LOAD, o_TIMER_EN, // Timer (* mark_debug = "true" *) output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
output logic [18:0] o_TIMER_IN, (* mark_debug = "true" *) output logic [18:0] o_TIMER_IN,
input logic [18:0] i_TIMER_OUT, (* mark_debug = "true" *) input logic [18:0] i_TIMER_OUT,
output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter (* mark_debug = "true" *) output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
output logic [7:0] o_COUNTER_IN, (* mark_debug = "true" *) output logic [7:0] o_COUNTER_IN,
input logic [7:0] i_COUNTER_OUT, (* mark_debug = "true" *) input logic [7:0] i_COUNTER_OUT,
output logic o_SD_CLK_EN, // Clock Gaters (* mark_debug = "true" *) output logic o_SD_CLK_EN, // Clock Gaters
input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM (* mark_debug = "true" *) input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM (* mark_debug = "true" *) output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter (* mark_debug = "true" *) output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17 (* mark_debug = "true" *) input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
input logic [1:0] i_USES_DAT, (* mark_debug = "true" *) input logic [1:0] i_USES_DAT,
input logic [6:0] i_OPCODE, (* mark_debug = "true" *) input logic [6:0] i_OPCODE,
input logic [2:0] i_R_TYPE, (* mark_debug = "true" *) input logic [2:0] i_R_TYPE,
// bit masks // bit masks
input logic [31:0] i_NO_REDO_MASK, (* mark_debug = "true" *) input logic [31:0] i_NO_REDO_MASK,
input logic [31:0] i_NO_REDO_ANS, (* mark_debug = "true" *) input logic [31:0] i_NO_REDO_ANS,
input logic [31:0] i_NO_ERROR_MASK, (* mark_debug = "true" *) input logic [31:0] i_NO_ERROR_MASK,
input logic [31:0] i_NO_ERROR_ANS, (* mark_debug = "true" *) input logic [31:0] i_NO_ERROR_ANS,
output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line (* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
// TX Components // TX Components
output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head (* mark_debug = "true" *) output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail (* mark_debug = "true" *) output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator (* mark_debug = "true" *) output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX (* mark_debug = "true" *) output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
// TX Memory // TX Memory
output logic o_CMD_TX_IS_CMD55_RST, (* mark_debug = "true" *) output logic o_CMD_TX_IS_CMD55_RST,
output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index (* mark_debug = "true" *) output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
// 55, so the subsequent command is to be // 55, so the subsequent command is to be
// viewed as ACMD by the SD card. // viewed as ACMD by the SD card.
// RX Components // RX Components
input logic i_SD_CMD_RX, // serial response input on SD_CMD (* mark_debug = "true" *) input logic i_SD_CMD_RX, // serial response input on SD_CMD
output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response (* mark_debug = "true" *) output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT (* mark_debug = "true" *) input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT (* mark_debug = "true" *) input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator (* mark_debug = "true" *) output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
input logic [6:0] i_RX_CRC7, (* mark_debug = "true" *) input logic [6:0] i_RX_CRC7,
// RX Memory // RX Memory
output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address (* mark_debug = "true" *) output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
// Communication to sd_dat_fsm // Communication to sd_dat_fsm
output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete (* mark_debug = "true" *) output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed (* mark_debug = "true" *) input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
input logic i_ERROR_CRC16, // repeat last command (* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command
input logic i_ERROR_DAT_TIMES_OUT, (* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT,
// Commnuication to core // Commnuication to core
output logic o_READY_FOR_READ, // tell core that I have completed initialization (* mark_debug = "true" *) output logic o_READY_FOR_READ, // tell core that I have completed initialization
output logic o_SD_RESTARTING, // inform core the need to restart (* mark_debug = "true" *) output logic o_SD_RESTARTING, // inform core the need to restart
input logic i_READ_REQUEST, // core tells me to execute CMD17 (* mark_debug = "true" *) input logic i_READ_REQUEST, // core tells me to execute CMD17
// Communication to Host // Communication to Host
output logic o_DAT_ERROR_FD_RST, (* mark_debug = "true" *) output logic o_DAT_ERROR_FD_RST,
output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error (* mark_debug = "true" *) output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card (* mark_debug = "true" *) output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
input logic LIMIT_SD_TIMERS (* mark_debug = "true" *) input logic LIMIT_SD_TIMERS
); );
(* mark_debug = "true" *) logic [4:0] w_next_state, r_curr_state; (* mark_debug = "true" *) logic [4:0] w_next_state, r_curr_state;
logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card; (* mark_debug = "true" *) logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card;
logic [31:0] w_redo_result, w_error_result; (* mark_debug = "true" *) logic [31:0] w_redo_result, w_error_result;
logic w_ACMD41_init_done; (* mark_debug = "true" *) logic w_ACMD41_init_done;
logic w_fail_cnt_en, w_fail_count_rst; (* mark_debug = "true" *) logic w_fail_cnt_en, w_fail_count_rst;
logic [10:0] r_fail_count_out; (* mark_debug = "true" *) logic [10:0] r_fail_count_out;
logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41 (* mark_debug = "true" *) logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41
logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM (* mark_debug = "true" *) logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM
logic w_ERROR_CODE_RST, w_ERROR_CODE_EN; (* mark_debug = "true" *) logic w_ERROR_CODE_RST, w_ERROR_CODE_EN;
logic [18:0] Timer_In; (* mark_debug = "true" *) logic [18:0] Timer_In;
localparam s_reset_clear_error_reg = 5'b00000; localparam s_reset_clear_error_reg = 5'b00000;

14
wally-pipelined/src/sdc/sd_top.sv
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@ -31,11 +31,11 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles) input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK! // a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
// io_SD_CMD_z : inout std_logic; // SD CMD Bus // io_SD_CMD_z : inout std_logic; // SD CMD Bus
input logic i_SD_CMD, // CMD Response from card (* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card
output logic o_SD_CMD, // CMD Command from host (* mark_debug = "true" *)output logic o_SD_CMD, // CMD Command from host
output logic o_SD_CMD_OE, // Direction of SD_CMD (* mark_debug = "true" *)output logic o_SD_CMD_OE, // Direction of SD_CMD
input logic [3:0] i_SD_DAT, // SD DAT Bus (* mark_debug = "true" *)input logic [3:0] i_SD_DAT, // SD DAT Bus
output logic o_SD_CLK, // SD CLK Bus (* mark_debug = "true" *)output logic o_SD_CLK, // SD CLK Bus
// For communication with core cpu // For communication with core cpu
input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used) input logic [32:9] i_BLOCK_ADDR, // see "Addressing" in parts.fods (only 8GB total capacity is used)
output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and output logic o_READY_FOR_READ, // tells core that initialization sequence is completed and
@ -222,7 +222,7 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
logic [15:0] r_RCA_Q2; logic [15:0] r_RCA_Q2;
// Multiplexer Logics // Multiplexer Logics
logic [132:0] w_instruction_control_bits; (* mark_debug = "true" *) logic [132:0] w_instruction_control_bits;
logic [132:130] w_R_TYPE ; logic [132:130] w_R_TYPE ;
logic [129:128] w_USES_DAT ; logic [129:128] w_USES_DAT ;
logic [127:96] w_NO_REDO_MASK ; logic [127:96] w_NO_REDO_MASK ;
@ -255,7 +255,7 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
// Tri state IO Driver BC18MIMS // Tri state IO Driver BC18MIMS
logic w_SD_CMD_TX_Q; // Write Data logic w_SD_CMD_TX_Q; // Write Data
logic w_SD_CMD_RX; // Read Data (* mark_debug = "true" *) logic w_SD_CMD_RX; // Read Data
// CLOCKS // CLOCKS

41
wally-pipelined/src/wally/ila_0.sv
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@ -1,41 +0,0 @@
///////////////////////////////////////////
// ila_0.sv
//
// Written: Ross Thompson September 26, 2021
// Modified:
//
// Purpose: stub for simulation. does nothing.
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module ila_0
(input logic clk,
input logic [`XLEN-1:0] probe0,
input logic [`XLEN-1:0] probe1,
input logic [`XLEN-1:0] probe2,
input logic [`XLEN-1:0] probe3,
input logic probe4,
input logic [1:0] probe5,
input logic [31:0] probe6
);
endmodule; // ila_0

17
wally-pipelined/src/wally/wallypipelinedsoc.sv
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@ -54,8 +54,10 @@ module wallypipelinedsoc (
output logic [31:0] GPIOPinsOut, GPIOPinsEn, output logic [31:0] GPIOPinsOut, GPIOPinsEn,
input logic UARTSin, input logic UARTSin,
output logic UARTSout, output logic UARTSout,
output tri1 SDCCmd, input logic SDCCmdIn,
input logic [3:0] SDCDat, output logic SDCCmdOut,
output logic SDCCmdOE,
input logic [3:0] SDCDatIn,
output logic SDCCLK output logic SDCCLK
); );
@ -77,14 +79,17 @@ module wallypipelinedsoc (
logic [31:0] InstrF; logic [31:0] InstrF;
logic HRESP; logic HRESP;
/* -----\/----- EXCLUDED -----\/-----
logic SDCCmdOut; logic SDCCmdOut;
logic SDCCmdOE; logic SDCCmdOE;
logic SDCCmdIn; logic SDCCmdIn;
logic [3:0] SDCDatIn; -----/\----- EXCLUDED -----/\----- */
// logic [3:0] SDCDatIn;
assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz; // it turn out vivado cannot infer these at this level of the hierarchy.
assign SDCCmdIn = SDCCmd; //assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
assign SDCDatIn = SDCDat; // when write supported this will be a tristate //assign SDCCmdIn = SDCCmd;
//assign SDCDatIn = SDCDat; // when write supported this will be a tristate
// instantiate processor and memories // instantiate processor and memories
wallypipelinedhart hart(.*); wallypipelinedhart hart(.*);

12
wally-pipelined/src/wally/wallypipelinedsocwrapper.v
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@ -55,9 +55,11 @@ module wallypipelinedsocwrapper (
input UARTSin, input UARTSin,
output UARTSout, output UARTSout,
input ddr4_calib_complete, input ddr4_calib_complete,
input [3:0] SDCDat, input [3:0] SDCDatIn,
output SDCCLK, output SDCCLK,
inout SDCCmd input SDCCmdIn,
output SDCCmdOut,
output SDCCmdOE
); );
wire [31:0] GPIOPinsEn; wire [31:0] GPIOPinsEn;
@ -109,8 +111,10 @@ module wallypipelinedsocwrapper (
.GPIOPinsEn(GPIOPinsEn), .GPIOPinsEn(GPIOPinsEn),
.UARTSin(UARTSin), .UARTSin(UARTSin),
.UARTSout(UARTSout), .UARTSout(UARTSout),
.SDCDat(SDCDat), .SDCDatIn(SDCDatIn),
.SDCCLK(SDCCLK), .SDCCLK(SDCCLK),
.SDCCmd(SDCCmd)); .SDCCmdIn(SDCCmdIn),
.SDCCmdOut(SDCCmdOut),
.SDCCmdOE(SDCCmdOE));
endmodule endmodule

63
wally-pipelined/testbench/testbench-fpga.sv
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@ -519,12 +519,12 @@ string tests32f[] = '{
logic DCacheFlushDone, DCacheFlushStart; logic DCacheFlushDone, DCacheFlushStart;
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); flopenr #(`XLEN) PCWReg(clk, reset, ~dut.wallypipelinedsoc.hart.ieu.dp.StallW, dut.wallypipelinedsoc.hart.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW); flopenr #(32) InstrWReg(clk, reset, ~dut.wallypipelinedsoc.hart.ieu.dp.StallW, dut.wallypipelinedsoc.hart.ifu.InstrM, InstrW);
// check assertions for a legal configuration // check assertions for a legal configuration
riscvassertions riscvassertions(); riscvassertions riscvassertions();
logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS); logging logging(clk, reset, dut.wallypipelinedsoc.uncore.HADDR, dut.wallypipelinedsoc.uncore.HTRANS);
// pick tests based on modes supported // pick tests based on modes supported
initial begin initial begin
@ -568,8 +568,11 @@ string tests32f[] = '{
string signame, memfilename, romfilename, sdcfilename; string signame, memfilename, romfilename, sdcfilename;
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic [3:0] GPIOPinsIn_IO;
logic [4:0] GPIOPinsOut_IO;
logic UARTSin, UARTSout; logic UARTSin, UARTSout;
logic ddr4_calib_complete;
logic SDCCLK; logic SDCCLK;
tri1 SDCCmd; tri1 SDCCmd;
@ -594,10 +597,10 @@ string tests32f[] = '{
wallypipelinedsocwrapper dut(.*); wallypipelinedsocwrapper dut(.*);
// Track names of instructions // Track names of instructions
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, instrTrackerTB it(clk, reset, dut.wallypipelinedsoc.hart.ieu.dp.FlushE,
dut.hart.ifu.icache.FinalInstrRawF, dut.wallypipelinedsoc.hart.ifu.icache.FinalInstrRawF,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.wallypipelinedsoc.hart.ifu.InstrD, dut.wallypipelinedsoc.hart.ifu.InstrE,
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, dut.wallypipelinedsoc.hart.ifu.InstrM, dut.wallypipelinedsoc.hart.ifu.InstrW,
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
// initialize tests // initialize tests
@ -630,7 +633,7 @@ string tests32f[] = '{
romfilename = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.memfile"}; romfilename = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.memfile"};
sdcfilename = {"../src/sdc/tb/ramdisk2.hex"}; sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};
$readmemh(memfilename, dtim.RAM); $readmemh(memfilename, dtim.RAM);
$readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM); $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootdtim.bootdtim.RAM);
$readmemh(sdcfilename, sdcard.FLASHmem); $readmemh(sdcfilename, sdcard.FLASHmem);
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.addr"}; ProgramAddrMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.addr"};
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.lab"}; ProgramLabelMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.lab"};
@ -648,11 +651,11 @@ string tests32f[] = '{
always @(negedge clk) always @(negedge clk)
begin begin
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
if (dut.hart.priv.EcallFaultM && if (dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.hart.ieu.dp.regf.we3 && (dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
dut.hart.ieu.dp.regf.a3 == 3 && dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
dut.hart.ieu.dp.regf.wd3 == 1))) begin dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1))) begin
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
if (DCacheFlushDone) begin if (DCacheFlushDone) begin
//$display("Code ended with ecall with gp = 1"); //$display("Code ended with ecall with gp = 1");
@ -729,18 +732,20 @@ string tests32f[] = '{
end // always @ (negedge clk) end // always @ (negedge clk)
// track the current function or global label // track the current function or global label
/* -----\/----- EXCLUDED -----\/-----
if (DEBUG == 1) begin : FunctionName if (DEBUG == 1) begin : FunctionName
FunctionName FunctionName(.reset(reset), FunctionName FunctionName(.reset(reset),
.clk(clk), .clk(clk),
.ProgramAddrMapFile(ProgramAddrMapFile), .ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile)); .ProgramLabelMapFile(ProgramLabelMapFile));
end end
-----/\----- EXCLUDED -----/\----- */
assign DCacheFlushStart = dut.hart.priv.EcallFaultM && assign DCacheFlushStart = dut.wallypipelinedsoc.hart.priv.EcallFaultM &&
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.wallypipelinedsoc.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.hart.ieu.dp.regf.we3 && (dut.wallypipelinedsoc.hart.ieu.dp.regf.we3 &&
dut.hart.ieu.dp.regf.a3 == 3 && dut.wallypipelinedsoc.hart.ieu.dp.regf.a3 == 3 &&
dut.hart.ieu.dp.regf.wd3 == 1)); dut.wallypipelinedsoc.hart.ieu.dp.regf.wd3 == 1));
DCacheFlushFSM DCacheFlushFSM(.clk(clk), DCacheFlushFSM DCacheFlushFSM(.clk(clk),
.reset(reset), .reset(reset),
@ -753,8 +758,8 @@ string tests32f[] = '{
if (`BPRED_ENABLED == 1) begin : bpred if (`BPRED_ENABLED == 1) begin : bpred
initial begin initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
end end
end end
endgenerate endgenerate
@ -794,10 +799,10 @@ module DCacheFlushFSM
input logic start, input logic start,
output logic done); output logic done);
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES; localparam integer numlines = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMLINES;
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS; localparam integer numways = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMWAYS;
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN; localparam integer blockbytelen = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKBYTELEN;
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN; localparam integer numwords = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKLEN/`XLEN;
localparam integer lognumlines = $clog2(numlines); localparam integer lognumlines = $clog2(numlines);
localparam integer logblockbytelen = $clog2(blockbytelen); localparam integer logblockbytelen = $clog2(blockbytelen);
localparam integer lognumways = $clog2(numways); localparam integer lognumways = $clog2(numways);
@ -823,10 +828,10 @@ module DCacheFlushFSM
.logblockbytelen(logblockbytelen)) .logblockbytelen(logblockbytelen))
copyShadow(.clk, copyShadow(.clk,
.start, .start,
.tag(testbench.dut.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]), .tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
.valid(testbench.dut.hart.lsu.dcache.MemWay[way].ValidBits[index]), .valid(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].ValidBits[index]),
.dirty(testbench.dut.hart.lsu.dcache.MemWay[way].DirtyBits[index]), .dirty(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
.data(testbench.dut.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]), .data(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
.index(index), .index(index),
.cacheWord(cacheWord), .cacheWord(cacheWord),
.CacheData(CacheData[way][index][cacheWord]), .CacheData(CacheData[way][index][cacheWord]),