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Fixed issue with branch deriv configs.

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This commit is contained in:
Rose Thompson 2024-02-06 16:07:41 -06:00
parent 58580445ab
commit da65928f04
3 changed files with 5 additions and 14 deletions
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11
config/rv32gc/config.vh
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@ -154,22 +154,11 @@ localparam PLIC_SPI_ID = 32'd6;
localparam PLIC_SDC_ID = 32'd9; localparam PLIC_SDC_ID = 32'd9;
localparam BPRED_SUPPORTED = 1; localparam BPRED_SUPPORTED = 1;
// this is an annoying hack for the branch predictor parameterization override.
`ifdef BPRED_OVERRIDE
localparam BPRED_TYPE = `BPRED_TYPE;
localparam BPRED_SIZE = `BPRED_SIZE;
`else
localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
localparam BPRED_SIZE = 32'd10; localparam BPRED_SIZE = 32'd10;
`endif
localparam BPRED_NUM_LHR = 32'd6; localparam BPRED_NUM_LHR = 32'd6;
`ifdef BTB_OVERRIDE
localparam BTB_SIZE = `BTB_SIZE;
localparam RAS_SIZE = `RAS_SIZE;
`else
localparam BTB_SIZE = 32'd10; localparam BTB_SIZE = 32'd10;
localparam RAS_SIZE = 32'd16; localparam RAS_SIZE = 32'd16;
`endif
localparam INSTR_CLASS_PRED = 1; localparam INSTR_CLASS_PRED = 1;
localparam SVADU_SUPPORTED = 1; localparam SVADU_SUPPORTED = 1;

2
sim/regression-wally
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@ -72,7 +72,7 @@ def getBuildrootTC(boot):
BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!" BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
else: else:
print( "buildroot no coverage") print( "buildroot no coverage")
BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!" BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot -GINSTR_LIMIT=" +str(INSTR_LIMIT) + " \n!"
BRgrepstr=str(INSTR_LIMIT)+" instructions" BRgrepstr=str(INSTR_LIMIT)+" instructions"
return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr) return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)

4
testbench/testbench.sv
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@ -41,6 +41,7 @@ module testbench;
parameter I_CACHE_ADDR_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0;
parameter RISCV_DIR = "/opt/riscv"; parameter RISCV_DIR = "/opt/riscv";
parameter INSTR_LIMIT = 0;
`include "parameter-defs.vh" `include "parameter-defs.vh"
@ -543,7 +544,8 @@ module testbench;
logic [P.XLEN-1:0] Minstret; logic [P.XLEN-1:0] Minstret;
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
always @(negedge clk) begin always @(negedge clk) begin
if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions, %d", Minstret, INSTR_LIMIT);
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
end end
end end