From da65928f04e147a6c6a4ee00f361647646b1ac05 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Tue, 6 Feb 2024 16:07:41 -0600
Subject: [PATCH] Fixed issue with branch deriv configs.

---
 config/rv32gc/config.vh | 11 -----------
 sim/regression-wally    |  2 +-
 testbench/testbench.sv  |  6 ++++--
 3 files changed, 5 insertions(+), 14 deletions(-)

diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
index 8b4b78a4f..843f55530 100644
--- a/config/rv32gc/config.vh
+++ b/config/rv32gc/config.vh
@@ -154,22 +154,11 @@ localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
 localparam BPRED_SUPPORTED = 1;
-// this is an annoying hack for the branch predictor parameterization override.
-`ifdef BPRED_OVERRIDE
-localparam BPRED_TYPE = `BPRED_TYPE;
-localparam BPRED_SIZE = `BPRED_SIZE;
-`else
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
-`endif
 localparam BPRED_NUM_LHR = 32'd6;
-`ifdef BTB_OVERRIDE
-localparam BTB_SIZE = `BTB_SIZE;
-localparam RAS_SIZE = `RAS_SIZE;
-`else
 localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
-`endif
 localparam INSTR_CLASS_PRED = 1;
 
 localparam SVADU_SUPPORTED = 1;
diff --git a/sim/regression-wally b/sim/regression-wally
index 4c3b630c4..757282b7c 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -72,7 +72,7 @@ def getBuildrootTC(boot):
             BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
         else:
             print( "buildroot no coverage")
-            BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
+            BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot -GINSTR_LIMIT=" +str(INSTR_LIMIT) + " \n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"
     return  TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
 
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index c65ab8a42..8b323b928 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -41,7 +41,8 @@ module testbench;
   parameter I_CACHE_ADDR_LOGGER=0;
   parameter D_CACHE_ADDR_LOGGER=0;
   parameter RISCV_DIR = "/opt/riscv";
- 
+  parameter INSTR_LIMIT = 0;
+  
 `include "parameter-defs.vh"
 
   logic        clk;
@@ -543,7 +544,8 @@ module testbench;
     logic [P.XLEN-1:0] Minstret;
     assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];  
     always @(negedge clk) begin
-      if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
+      if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions, %d", Minstret, INSTR_LIMIT);
+      if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
     end
   end