mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Ross Thompson
GitHub
commit
d8fcd9d350
1
.gitignore
vendored
1
.gitignore
vendored
@ -111,6 +111,5 @@ sim/imperas.log
|
||||
sim/results-error/
|
||||
sim/test1.rep
|
||||
sim/vsim.log
|
||||
tests/coverage/*.S
|
||||
tests/coverage/*.elf
|
||||
*.elf.memfile
|
||||
58
README.md
58
README.md
@ -11,15 +11,15 @@ Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by H
|
||||
|
||||
New users may wish to do the following setup to access the server via a GUI and use a text editor.
|
||||
|
||||
Git started with Git configuration and authentication: B.1 (replace with your name and email)
|
||||
$ git config --global user.name "Ben Bitdiddle"
|
||||
$ git config --global user.email "ben_bitdiddle@wally.edu"
|
||||
$ git config --global pull.rebase false
|
||||
Optional: Download and install x2go - A.1.1
|
||||
Optional: Download and install VSCode - A.4.2
|
||||
Optional: Make sure you can log into your server via x2go and via a terminal
|
||||
Terminal on Mac, cmd on Windows, xterm on Linux
|
||||
See A.1 about ssh -Y login from a terminal
|
||||
Git started with Git configuration and authentication: B.1
|
||||
$ git config --global user.name ″Ben Bitdiddle″
|
||||
$ git config --global user.email ″ben_bitdiddle@wally.edu″
|
||||
$ git config --global pull.rebase false
|
||||
|
||||
Then clone the repo, source setup, make the tests and run regression
|
||||
|
||||
@ -30,20 +30,20 @@ Then clone the repo, source setup, make the tests and run regression
|
||||
|
||||
On the Linux computer where you will be working, log in
|
||||
|
||||
Clone your fork of the repo and run the setup script.
|
||||
|
||||
$ cd
|
||||
$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
|
||||
$ git remote add upstream https://github.com/openhwgroup/cvw
|
||||
$ cd cvw
|
||||
$ source ./setup.sh
|
||||
|
||||
Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
|
||||
|
||||
if [ -f ~/cvw/setup.sh ]; then
|
||||
source ~/cvw/setup.sh
|
||||
fi
|
||||
|
||||
Clone your fork of the repo, run the setup script, and build the tests:
|
||||
|
||||
$ cd
|
||||
$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
|
||||
$ cd cvw
|
||||
$ source ./setup.sh
|
||||
$ make
|
||||
|
||||
Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis.
|
||||
|
||||
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
|
||||
@ -51,8 +51,11 @@ Edit setup.sh and change the following lines to point to the path and license se
|
||||
export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
|
||||
export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
|
||||
|
||||
Run a regression simulation with Questa to prove everything is installed.
|
||||
If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
|
||||
|
||||
Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while.
|
||||
|
||||
$ make
|
||||
$ cd sim
|
||||
$ ./regression-wally (depends on having Questa installed)
|
||||
|
||||
@ -60,32 +63,15 @@ Run a regression simulation with Questa to prove everything is installed.
|
||||
|
||||
This section describes the open source toolchain installation. The
|
||||
current version of the toolchain has been tested on Ubuntu and Red
|
||||
Hat/Rocky 8. The latter is more difficult to install and Ubuntu may
|
||||
be more recommended for new users. The <pre>wally-tool-chain-install.sh</pre> script inside
|
||||
the bin directory can be utilized to install the toolchain on Ubuntu
|
||||
using sudo.
|
||||
Hat/Rocky 8 Linux. Ubuntu works more smoothly and is recommended
|
||||
unless you have a compelling need for RedHat.
|
||||
|
||||
### Download Synthesis Libraries
|
||||
|
||||
For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library. Clone the OSU 12-track cell library for the Skywater 130 nm process:
|
||||
|
||||
$ cd $RISCV
|
||||
$ mkdir cad
|
||||
$ mkdir cad/lib
|
||||
$ cd cad/lib
|
||||
$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12
|
||||
|
||||
### Install github cli
|
||||
|
||||
The github cli allows users to directly issue pull requests from their fork back to openhwgroup/cvw using the command line.
|
||||
|
||||
$ type -p curl >/dev/null || sudo apt install curl -y
|
||||
$ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ && sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
|
||||
&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
|
||||
&& sudo apt update \
|
||||
&& sudo apt install gh -y
|
||||
Ubuntu users can install the tools by running
|
||||
|
||||
$ sudo $WALLY/bin/wally-tool-chain-install.sh
|
||||
|
||||
See wally-tool-chain-install.sh for a detailed description of each component,
|
||||
or to issue the commands one at a time to install on the command line.
|
||||
## Installing EDA Tools
|
||||
|
||||
Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access.
|
||||
|
||||
@ -34,18 +34,20 @@ export PATH=$PATH:$RISCV/bin
|
||||
set -e # break on error
|
||||
|
||||
# Modify accordingly for your machine
|
||||
NUM_THREADS=1 # for low memory machines > 16GiB
|
||||
# Increasing NUM_THREADS will speed up parallel compilation of the tools
|
||||
NUM_THREADS=2 # for low memory machines > 16GiB
|
||||
#NUM_THREADS=8 # for >= 32GiB
|
||||
#NUM_THREADS=16 # for >= 64GiB
|
||||
|
||||
sudo mkdir -p $RISCV
|
||||
|
||||
# Update and Upgrade (see https://itsfoss.com/apt-update-vs-upgrade/)
|
||||
apt update
|
||||
apt upgrade
|
||||
# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
|
||||
apt update -y
|
||||
apt upgrade -y
|
||||
apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator
|
||||
|
||||
# INSTALL
|
||||
apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev
|
||||
# Other python libraries used through the book.
|
||||
pip3 install matplotlib scipy scikit-learn adjustText lief
|
||||
|
||||
# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
|
||||
if ! command -v python &> /dev/null
|
||||
@ -55,6 +57,14 @@ then
|
||||
fi
|
||||
|
||||
# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
|
||||
# To install GCC from source can take hours to compile.
|
||||
#This configuration enables multilib to target many flavors of RISC-V.
|
||||
# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well.
|
||||
# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes
|
||||
# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly.
|
||||
# However GCC12.x is needed for bit manipulation instructions. There is an open issue to fix this:
|
||||
# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188
|
||||
|
||||
cd $RISCV
|
||||
git clone https://github.com/riscv/riscv-gnu-toolchain
|
||||
cd riscv-gnu-toolchain
|
||||
@ -64,6 +74,12 @@ make -j ${NUM_THREADS}
|
||||
make install
|
||||
|
||||
# elf2hex (https://github.com/sifive/elf2hex)
|
||||
#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation.
|
||||
# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t
|
||||
# handle programs that start at 0x80000000. The SiFive version above is touchy to install.
|
||||
# For example, if Python version 2.x is in your path, it won’t install correctly.
|
||||
# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin
|
||||
# at the time of compilation, or elf2hex won’t work properly.
|
||||
cd $RISCV
|
||||
export PATH=$RISCV/bin:$PATH
|
||||
git clone https://github.com/sifive/elf2hex.git
|
||||
@ -73,11 +89,6 @@ autoreconf -i
|
||||
make
|
||||
make install
|
||||
|
||||
# Update Python3.6 for QEMU
|
||||
apt-get -y update
|
||||
apt-get -y install python3-pip
|
||||
apt-get -y install pkg-config
|
||||
apt-get -y install libglib2.0-dev
|
||||
|
||||
# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html)
|
||||
cd $RISCV
|
||||
@ -88,6 +99,8 @@ make -j ${NUM_THREADS}
|
||||
make install
|
||||
|
||||
# Spike (https://github.com/riscv-software-src/riscv-isa-sim)
|
||||
# Spike also takes a while to install and compile, but this can be done concurrently
|
||||
#with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions.
|
||||
cd $RISCV
|
||||
git clone https://github.com/riscv-software-src/riscv-isa-sim
|
||||
mkdir -p riscv-isa-sim/build
|
||||
@ -100,17 +113,24 @@ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
|
||||
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
|
||||
# Sail (https://github.com/riscv/sail-riscv)
|
||||
cd $RISCV
|
||||
apt-get install -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev
|
||||
git clone https://github.com/Z3Prover/z3.git
|
||||
cd z3
|
||||
python scripts/mk_make.py
|
||||
cd build
|
||||
make -j ${NUM_THREADS}
|
||||
make install
|
||||
cd ../..
|
||||
pip3 install chardet==3.0.4
|
||||
pip3 install urllib3==1.22
|
||||
# Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which
|
||||
# is an object-oriented extension of ML, which in turn is a functional programming
|
||||
# language suited to formal verification. OCaml is installed with the opam OCcaml
|
||||
# package manager. Sail has so many dependencies that it can be difficult to install.
|
||||
# This script works for Ubuntu.
|
||||
|
||||
# Do these commands only for RedHat / Rocky 8 to build from source.
|
||||
#cd $RISCV
|
||||
#git clone https://github.com/Z3Prover/z3.git
|
||||
#cd z3
|
||||
#python scripts/mk_make.py
|
||||
#cd build
|
||||
#make -j ${NUM_THREADS}
|
||||
#make install
|
||||
#cd ../..
|
||||
#pip3 install chardet==3.0.4
|
||||
#pip3 install urllib3==1.22
|
||||
|
||||
opam init -y --disable-sandboxing
|
||||
opam switch create ocaml-base-compiler.4.06.1
|
||||
opam install sail -y
|
||||
@ -130,17 +150,3 @@ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
|
||||
pip3 install testresources
|
||||
pip3 install riscof --ignore-installed PyYAML
|
||||
|
||||
# Verilator
|
||||
apt install -y verilator
|
||||
|
||||
# install github cli (gh)
|
||||
type -p curl >/dev/null || sudo apt install curl -y
|
||||
curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \
|
||||
&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
|
||||
&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
|
||||
&& sudo apt update \
|
||||
&& sudo apt install gh -y
|
||||
|
||||
# Other python libraries used through the book.
|
||||
sudo pip3 install matplotlib scipy sklearn adjustText leif
|
||||
|
||||
|
||||
@ -126,11 +126,18 @@ for test in ahbTests:
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
|
||||
tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
|
||||
if (coverage): # delete all but 64gc tests when running coverage
|
||||
configs = []
|
||||
tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
|
||||
# tests64gc.append(["imperas64f", "imperas64d", "imperas64c", "imperas64i"])
|
||||
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
"arch64zi", "wally64a", "wally64periph", "wally64priv",
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
|
||||
# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
# "arch64zi", "wally64a", "wally64periph", "wally64priv",
|
||||
# "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
# "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
|
||||
coverStr = '-coverage'
|
||||
else:
|
||||
coverStr = ''
|
||||
|
||||
@ -76,106 +76,84 @@ module bmuctrl(
|
||||
|
||||
// Main Instruction Decoder
|
||||
always_comb begin
|
||||
BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
// ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
|
||||
// ZBS
|
||||
17'b0010011_0100100_001: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri
|
||||
17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64)
|
||||
17'b0010011_0100100_101: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti
|
||||
17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64)
|
||||
17'b0010011_0110100_001: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi
|
||||
17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64)
|
||||
17'b0010011_0010100_001: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti
|
||||
17'b0010011_0010101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64)
|
||||
17'b0110011_0100100_001: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr
|
||||
17'b0110011_0100100_101: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext
|
||||
17'b0110011_0110100_001: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv
|
||||
17'b0110011_0010100_001: if (`ZBS_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset
|
||||
17'b0110011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll
|
||||
17'b0010011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli
|
||||
17'b0111011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw
|
||||
17'b0011011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw
|
||||
BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction
|
||||
if (`ZBA_SUPPORTED)
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add
|
||||
17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add
|
||||
17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add
|
||||
endcase
|
||||
if (`ZBA_SUPPORTED & `XLEN==64)
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw
|
||||
17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw
|
||||
17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw
|
||||
17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw
|
||||
17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw
|
||||
endcase
|
||||
if (`ZBB_SUPPORTED)
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol
|
||||
17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror
|
||||
17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
|
||||
else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
|
||||
17'b0110011_0000100_100: if (`XLEN == 32)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
|
||||
17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
|
||||
17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
|
||||
17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
|
||||
17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
|
||||
17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
|
||||
17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max
|
||||
17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu
|
||||
17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min
|
||||
17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu
|
||||
endcase
|
||||
if (`ZBB_SUPPORTED & `XLEN==64)
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw
|
||||
17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw
|
||||
17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64)
|
||||
17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw
|
||||
17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction
|
||||
17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64)
|
||||
endcase
|
||||
if (`ZBC_SUPPORTED)
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction
|
||||
endcase
|
||||
if (`ZBS_SUPPORTED) // ZBS
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri
|
||||
17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti
|
||||
17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi
|
||||
17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti
|
||||
17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr
|
||||
17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext
|
||||
17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv
|
||||
17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset
|
||||
endcase
|
||||
if (`ZBS_SUPPORTED & `XLEN==64) // ZBS 64-bit
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0010011_0100101_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64)
|
||||
17'b0010011_0100101_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64)
|
||||
17'b0010011_0110101_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64)
|
||||
17'b0010011_0010101_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64)
|
||||
endcase
|
||||
if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used
|
||||
casez({OpD, Funct7D, Funct3D})
|
||||
17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll
|
||||
17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli
|
||||
17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw
|
||||
17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw
|
||||
endcase
|
||||
// ZBC
|
||||
17'b0110011_0000101_0??: if (`ZBC_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction
|
||||
// ZBA
|
||||
17'b0110011_0010000_010: if (`ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add
|
||||
17'b0110011_0010000_100: if (`ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add
|
||||
17'b0110011_0010000_110: if (`ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add
|
||||
17'b0111011_0010000_010: if (`XLEN == 64 & `ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw
|
||||
17'b0111011_0010000_100: if (`XLEN == 64 & `ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw
|
||||
17'b0111011_0010000_110: if (`XLEN == 64 & `ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw
|
||||
17'b0111011_0000100_000: if (`XLEN == 64 & `ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw
|
||||
17'b0011011_000010?_001: if (`XLEN == 64 & `ZBA_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw
|
||||
// ZBB
|
||||
17'b0110011_0110000_001: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol
|
||||
17'b0111011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw
|
||||
17'b0110011_0110000_101: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror
|
||||
17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw
|
||||
//17'b0010011_0110000_101: if (`ZBB_SUPPORTED)
|
||||
// BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32)
|
||||
17'b0010011_011000?_101: if ((`XLEN == 64 | ~Funct7D[0]) & `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64)
|
||||
17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw
|
||||
17'b0010011_0110000_001: if (`ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
|
||||
else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
|
||||
17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction
|
||||
17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64)
|
||||
17'b0110011_0000100_100: if (`XLEN == 32 & `ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
|
||||
17'b0110011_0100000_111: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
|
||||
17'b0110011_0100000_110: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
|
||||
17'b0110011_0100000_100: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
|
||||
17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000))
|
||||
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
|
||||
17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
|
||||
17'b0110011_0000101_110: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max
|
||||
17'b0110011_0000101_111: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu
|
||||
17'b0110011_0000101_100: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min
|
||||
17'b0110011_0000101_101: if (`ZBB_SUPPORTED)
|
||||
BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu
|
||||
endcase
|
||||
end
|
||||
|
||||
// Unpack Control Signals
|
||||
|
||||
@ -100,10 +100,10 @@ module csrs #(parameter
|
||||
else
|
||||
assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
|
||||
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
|
||||
if (`SSTC_SUPPORTED) begin
|
||||
if (`XLEN == 64)
|
||||
if (`SSTC_SUPPORTED) begin : sstc
|
||||
if (`XLEN == 64) begin : sstc64
|
||||
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
|
||||
else begin
|
||||
end else begin : sstc32
|
||||
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]);
|
||||
flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]);
|
||||
end
|
||||
|
||||
@ -11,7 +11,7 @@ import matplotlib.lines as lines
|
||||
import matplotlib as mpl
|
||||
import numpy as np
|
||||
from collections import namedtuple
|
||||
import sklearn.metrics as skm
|
||||
import sklearn.metrics as skm # depricated, will need to replace with scikit-learn
|
||||
import os
|
||||
|
||||
def synthsfromcsv(filename):
|
||||
|
||||
@ -106,6 +106,7 @@ logic [3:0] dummy;
|
||||
"coremark": tests = coremark;
|
||||
"fpga": tests = fpga;
|
||||
"ahb" : tests = ahb;
|
||||
"coverage64gc" : tests = coverage64gc;
|
||||
"arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba;
|
||||
"arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb;
|
||||
"arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc;
|
||||
@ -306,20 +307,22 @@ logic [3:0] dummy;
|
||||
testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
|
||||
#600; // give time for instructions in pipeline to finish
|
||||
if (TEST == "embench") begin
|
||||
// Writes contents of begin_signature to .sim.output file
|
||||
// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
|
||||
// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
|
||||
$display("Embench Benchmark: %s is done.", tests[test]);
|
||||
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
|
||||
else outputfile = {pathname, tests[test], ".sim.output"};
|
||||
outputFilePointer = $fopen(outputfile);
|
||||
i = 0;
|
||||
while ($unsigned(i) < $unsigned(5'd5)) begin
|
||||
$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
|
||||
i = i + 1;
|
||||
end
|
||||
$fclose(outputFilePointer);
|
||||
$display("Embench Benchmark: created output file: %s", outputfile);
|
||||
// Writes contents of begin_signature to .sim.output file
|
||||
// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
|
||||
// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
|
||||
$display("Embench Benchmark: %s is done.", tests[test]);
|
||||
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
|
||||
else outputfile = {pathname, tests[test], ".sim.output"};
|
||||
outputFilePointer = $fopen(outputfile);
|
||||
i = 0;
|
||||
while ($unsigned(i) < $unsigned(5'd5)) begin
|
||||
$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
|
||||
i = i + 1;
|
||||
end
|
||||
$fclose(outputFilePointer);
|
||||
$display("Embench Benchmark: created output file: %s", outputfile);
|
||||
end else if (TEST == "coverage64gc") begin
|
||||
$display("Coverage tests don't get checked");
|
||||
end else begin
|
||||
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
|
||||
// clear signature to prevent contamination from previous tests
|
||||
|
||||
@ -27,22 +27,27 @@
|
||||
`define IMPERASTEST "0"
|
||||
`define RISCVARCHTEST "1"
|
||||
`define WALLYTEST "2"
|
||||
`define MYIMPERASTEST "3"
|
||||
`define COREMARK "4"
|
||||
`define EMBENCH "5"
|
||||
`define CUSTOM "6"
|
||||
// *** remove MYIMPERASTEST cases when ported
|
||||
`define COREMARK "3"
|
||||
`define EMBENCH "4"
|
||||
`define CUSTOM "5"
|
||||
`define COVERAGE "6"
|
||||
|
||||
string tvpaths[] = '{
|
||||
"$RISCV/imperas-riscv-tests/work/",
|
||||
"../tests/riscof/work/riscv-arch-test/",
|
||||
"../tests/riscof/work/wally-riscv-arch-test/",
|
||||
"../tests/imperas-riscv-tests/work/",
|
||||
"../benchmarks/coremark/work/",
|
||||
"../addins/embench-iot/",
|
||||
"../tests/custom/work/"
|
||||
"../tests/custom/work/",
|
||||
"../tests/coverage/"
|
||||
};
|
||||
|
||||
string coverage64gc[] = '{
|
||||
`COVERAGE,
|
||||
"badinstr",
|
||||
"csrwrites"
|
||||
};
|
||||
|
||||
string coremark[] = '{
|
||||
`COREMARK,
|
||||
"coremark.bare.riscv"
|
||||
|
||||
@ -15,12 +15,12 @@ all: $(OBJECTS)
|
||||
|
||||
%.elf.objdump: %.elf
|
||||
|
||||
# Change many things if bit width isn't 64
|
||||
%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
|
||||
echo $@
|
||||
riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \
|
||||
-nostartfiles -T../../examples/link/link.ld $<
|
||||
riscv64-unknown-elf-objdump -D $@ > $@.objdump
|
||||
riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $@ --output $@.memfile
|
||||
riscv64-unknown-elf-objdump -S $@ > $@.objdump
|
||||
riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
|
||||
extractFunctionRadix.sh $@.objdump
|
||||
|
||||
sim: %.elf
|
||||
@ -29,7 +29,7 @@ sim: %.elf
|
||||
echo "Signature matches! Success!"
|
||||
|
||||
clean:
|
||||
rm -f *.elf *.objdump *.signature.output
|
||||
rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile
|
||||
|
||||
|
||||
|
||||
|
||||
@ -30,7 +30,13 @@ main:
|
||||
.word 0x00000033 // legal R-type instruction
|
||||
.word 0x80000033 // illegal R-type instruction
|
||||
.word 0x00007003 // illegal Load instruction
|
||||
.word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000
|
||||
.word 0x00000000 // illegal instruction
|
||||
.word 0x0000701B // Illegal IW instruction
|
||||
.word 0x00004023 // Illegal store instruction
|
||||
.word 0x0400003B // Illegal RW or MulDivW instruction
|
||||
.word 0x00007067 // Illegal JALR instruction
|
||||
.word 0x00002063 // Illegal branch instruction
|
||||
|
||||
j done
|
||||
|
||||
|
||||
35
tests/coverage/csrwrites.S
Normal file
35
tests/coverage/csrwrites.S
Normal file
@ -0,0 +1,35 @@
|
||||
///////////////////////////////////////////
|
||||
// csrwrites.S
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 21 March 2023
|
||||
//
|
||||
// Purpose: Test writes to CSRs
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// load code to initalize stack, handle interrupts, terminate
|
||||
#include "WALLY-init-lib.h"
|
||||
|
||||
main:
|
||||
csrrw t0, stimecmp, t0
|
||||
csrrw t0, satp, t0
|
||||
csrrw t0, stvec, t0
|
||||
csrrw t0, sscratch, t0
|
||||
|
||||
j done
|
||||
Loading…
Reference in New Issue
Block a user