From 3b3aa942c75744fd6fe610769a91442b68d7c273 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 22 Mar 2023 13:00:10 -0700
Subject: [PATCH 01/12] Added coverage tests to regression coverage

---
 sim/regression-wally    |  3 +--
 testbench/testbench.sv  | 31 +++++++++++++++++--------------
 testbench/tests.vh      | 18 +++++++++++-------
 tests/coverage/Makefile |  5 +++--
 4 files changed, 32 insertions(+), 25 deletions(-)

diff --git a/sim/regression-wally b/sim/regression-wally
index 683f30a93..9be1839a6 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -130,8 +130,7 @@ for test in ahbTests:
 tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
 if (coverage):  # delete all but 64gc tests when running coverage
     configs = []
-    tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
-#    tests64gc.append(["imperas64f", "imperas64d", "imperas64c", "imperas64i"])
+    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
     coverStr = '-coverage'
 else:
    coverStr = ''
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index fe3875cbb..cef2d986f 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -106,6 +106,7 @@ logic [3:0] dummy;
         "coremark":                       tests = coremark;
         "fpga":                           tests = fpga;
         "ahb" :                           tests = ahb;
+        "coverage64gc" :                  tests = coverage64gc;
       endcase 
     end else begin // RV32
       case (TEST)
@@ -299,20 +300,22 @@ logic [3:0] dummy;
           testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
           #600; // give time for instructions in pipeline to finish
           if (TEST == "embench") begin
-			// Writes contents of begin_signature to .sim.output file
-			// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
-			// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
-			$display("Embench Benchmark: %s is done.", tests[test]);
-			if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
-			else outputfile = {pathname, tests[test], ".sim.output"};
-			outputFilePointer = $fopen(outputfile);
-			i = 0;
-			while ($unsigned(i) < $unsigned(5'd5)) begin
-              $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
-              i = i + 1;
-			end
-			$fclose(outputFilePointer);
-			$display("Embench Benchmark: created output file: %s", outputfile);
+            // Writes contents of begin_signature to .sim.output file
+            // this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
+            // also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
+            $display("Embench Benchmark: %s is done.", tests[test]);
+            if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
+            else outputfile = {pathname, tests[test], ".sim.output"};
+            outputFilePointer = $fopen(outputfile);
+            i = 0;
+            while ($unsigned(i) < $unsigned(5'd5)) begin
+                    $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
+                    i = i + 1;
+            end
+            $fclose(outputFilePointer);
+            $display("Embench Benchmark: created output file: %s", outputfile);
+          end else if (TEST == "coverage64gc") begin
+            $display("Coverage tests don't get checked");
           end else begin 
 			// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
 			// clear signature to prevent contamination from previous tests
diff --git a/testbench/tests.vh b/testbench/tests.vh
index eff013a5b..4ca08a5e0 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -27,22 +27,26 @@
 `define IMPERASTEST   "0"
 `define RISCVARCHTEST "1"
 `define WALLYTEST "2"
-`define MYIMPERASTEST   "3"
-`define COREMARK "4"
-`define EMBENCH "5"
-`define CUSTOM "6"
-// *** remove MYIMPERASTEST cases when ported 
+`define COREMARK "3"
+`define EMBENCH "4"
+`define CUSTOM "5"
+`define COVERAGE "6"
 
 string tvpaths[] = '{
     "$RISCV/imperas-riscv-tests/work/",
     "../tests/riscof/work/riscv-arch-test/",
     "../tests/riscof/work/wally-riscv-arch-test/",
-    "../tests/imperas-riscv-tests/work/",
     "../benchmarks/coremark/work/",
     "../addins/embench-iot/",
-    "../tests/custom/work/"
+    "../tests/custom/work/",
+    "../tests/coverage/"
     };
 
+  string coverage64gc[] = '{
+    `COVERAGE,
+    "badinstr"
+  };
+
   string coremark[] = '{
     `COREMARK,
     "coremark.bare.riscv"
diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile
index 57a8a1b51..8742dee63 100644
--- a/tests/coverage/Makefile
+++ b/tests/coverage/Makefile
@@ -16,11 +16,12 @@ all: $(OBJECTS)
 %.elf.objdump: %.elf
 
 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
+	# Change many things if bit width isn't 64
 	echo $@
 	riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \
 	    -nostartfiles -T../../examples/link/link.ld $<
 	riscv64-unknown-elf-objdump -D $@ > $@.objdump
-	riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $@ --output $@.memfile
+	riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
 	extractFunctionRadix.sh $@.objdump
     
 sim: %.elf
@@ -29,7 +30,7 @@ sim: %.elf
 	echo "Signature matches! Success!"
 
 clean:
-	rm -f *.elf *.objdump *.signature.output
+	rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile
 
 
 

From a29769b7baba23f6b4b4cb317b2d48ee6960b4be Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 06:37:48 -0700
Subject: [PATCH 02/12] Updated README for upstream repo

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index f7abf0ba1..5a93b1a19 100644
--- a/README.md
+++ b/README.md
@@ -40,6 +40,7 @@ Clone your fork of the repo, run the setup script, and build the tests:
 
 	$ cd
 	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
+	$ git remote add upstream https://github.com/openhwgroup/cvw
 	$ cd cvw
 	$ source ./setup.sh
 	$ make

From 610b50a693e736e2fa65d261ba4ead4e84d04631 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 06:38:00 -0700
Subject: [PATCH 03/12] Added new tests from class

---
 tests/coverage/badinstr.S | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/tests/coverage/badinstr.S b/tests/coverage/badinstr.S
index ec875eaac..7714ab07b 100644
--- a/tests/coverage/badinstr.S
+++ b/tests/coverage/badinstr.S
@@ -30,7 +30,12 @@ main:
     .word 0x00000033 // legal R-type instruction
     .word 0x80000033 // illegal R-type instruction
     .word 0x00007003 // illegal Load instruction
+    .word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000
     .word 0x00000000 // illegal instruction
+    .word 0x0000701B  // Illegal IW instruction
+    .word 0x00004023  // Illegal store instruction
+    .word 0x0400003B  // Illegal RW or MulDivW instruction
+    .word 0x00007067  // Illegal JALR instruction
 
     j done
 

From 120da12414ee5e1be49e1b0c7259e8175ed4e8e6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 08:42:40 -0700
Subject: [PATCH 04/12] README/tool installation merge

---
 README.md                       | 33 +++++++++++++++++++--------------
 bin/wally-tool-chain-install.sh |  3 +--
 2 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/README.md b/README.md
index 3c105157e..ab9566afa 100644
--- a/README.md
+++ b/README.md
@@ -11,15 +11,15 @@ Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by H
 
 New users may wish to do the following setup to access the server via a GUI and use a text editor.
 
+	Git started with Git configuration and authentication: B.1 (replace with your name and email)
+		$ git config --global user.name "Ben Bitdiddle"
+		$ git config --global user.email "ben_bitdiddle@wally.edu"
+		$ git config --global pull.rebase false
 	Optional: Download and install x2go - A.1.1
 	Optional: Download and install VSCode - A.4.2
 	Optional: Make sure you can log into your server via x2go and via a terminal
 		Terminal on Mac, cmd on Windows, xterm on Linux
 		See A.1 about ssh -Y login from a terminal
-	Git started with Git configuration and authentication: B.1
-		$ git config --global user.name ″Ben Bitdiddle″
-		$ git config --global user.email ″ben_bitdiddle@wally.edu″
-		$ git config --global pull.rebase false
 
 Then clone the repo, source setup,  make the tests and run regression
 
@@ -30,21 +30,20 @@ Then clone the repo, source setup,  make the tests and run regression
 	
 	On the Linux computer where you will be working, log in
 
-Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
-
-	if [ -f ~/cvw/setup.sh ]; then
-		source ~/cvw/setup.sh
-	fi
-
-Clone your fork of the repo, run the setup script, and build the tests:
+Clone your fork of the repo and run the setup script.  
 
 	$ cd
 	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
 	$ git remote add upstream https://github.com/openhwgroup/cvw
 	$ cd cvw
 	$ source ./setup.sh
-	$ make
-	
+
+Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in.
+
+	if [ -f ~/cvw/setup.sh ]; then
+		source ~/cvw/setup.sh
+	fi
+
 Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server.  If you only have Questa, you can still simulate but cannot run logic synthesis.
 
 	export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu                # Change this to your Siemens license server
@@ -52,8 +51,11 @@ Edit setup.sh and change the following lines to point to the path and license se
 	export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin     # Change this for your path to Questa
 	export SNPSPATH=/cad/synopsys/SYN/bin                               # Change this for your path to Design Compiler
 
-Run a regression simulation with Questa to prove everything is installed.
+If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
 
+Build the tests and run a regression simulation with Questa to prove everything is installed.  Building tests will take a while.
+
+	$ make
 	$ cd sim
 	$ ./regression-wally       (depends on having Questa installed)
 
@@ -66,6 +68,9 @@ This section describes the open source toolchain installation.  These steps shou
 The full installation details are involved can be be skipped using the following script, wally-tool-chain-install.sh.
 The script installs the open source tools to /opt/riscv by default.  This can be changed by supply the path as the first argument.  This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide.
 
+	modify lines 34-36 of bin/wally-tool-chain-install to increase the number of threads to 8 or 16 to speed up installation
+	if you are on a machine with plenty of memory.
+	
 	$ sudo bin/wally-tool-chain-install.sh <optional, install directory, defaults to /opt/riscv>
 
 ## Detailed Toolchain Install Guide
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 181d097af..10dbaba2d 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -140,5 +140,4 @@ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo
 && sudo apt install gh -y
 
 # Other python libraries used through the book.
-sudo pip3 install matplotlib scipy sklearn adjustText leif
-
+pip3 install matplotlib scipy scikit-learn adjustText lief

From 92908be951f652d2a08da380aae1f88cf62583bc Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 08:49:20 -0700
Subject: [PATCH 05/12] README improvement

---
 README.md | 233 ++----------------------------------------------------
 1 file changed, 5 insertions(+), 228 deletions(-)

diff --git a/README.md b/README.md
index 73b9448b5..64243248d 100644
--- a/README.md
+++ b/README.md
@@ -61,236 +61,13 @@ Build the tests and run a regression simulation with Questa to prove everything
 
 # Toolchain Installation (Sys Admin)
 
-<<<<<<< HEAD
-This section describes the open source toolchain installation.  These steps should only be done once by the system admin.
-
-## TL;DR Open Source Tool-chain Installation
-
-The full installation details are involved can be be skipped using the following script, wally-tool-chain-install.sh.
-The script installs the open source tools to /opt/riscv by default.  This can be changed by supply the path as the first argument.  This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide.
-
-	modify lines 34-36 of bin/wally-tool-chain-install to increase the number of threads to 8 or 16 to speed up installation
-	if you are on a machine with plenty of memory.
-	
-	$ sudo bin/wally-tool-chain-install.sh <optional, install directory, defaults to /opt/riscv>
-
-## Detailed Toolchain Install Guide
-
-This section describes how to install the tools needed for CORE-V-Wally. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so Appendix D also describes an option with a Docker container.  
-
-### Open Source Software Installation
-
-Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools:
-
-1. The GCC cross-compiler
-2. A RISC-V simulator such as Spike, Sail, and/or QEMU
-3. Spike is easy to use but doesn’t support peripherals to boot Linux
-4. QEMU is faster and can boot Linux
-5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal
-
-This setup needs to be done once by the administrator
-
-Note: The following directions assume you have an account called cad to install shared software and files. You can substitute a different user for cad if you prefer.
-
-Note: Installing software in Linux is unreasonably touchy and varies with the flavor and version of your Linux distribution. Don’t be surprised if the installation directions have changed since the book was written or don’t work on your machine; you may need some ingenuity to adjust them. Browse the openhwgroup/core-v-wally repo and look at the README.md for the latest build instructions. 
-
-### Create the $RISCV Directory
-
-First, set up a directory for riscv software in some place such as /opt/riscv.  We will call this shared directory $RISCV.
-
-	$ export RISCV=/opt/riscv
-	$ sudo mkdir $RISCV
-	$ sudo chown cad $RISCV
-	$ sudo su cad  (or root, if you don’t have a cad account)
-	$ export RISCV=/opt/riscv
-	$ chmod 755 $RISCV
-	$ umask 0002
-	$ cd $RISCV
-
-### Update Tools
-
-Ubuntu users may need to install and update various tools.  Beware when cutting and pasting that some lines are long!
-
-	$ sudo apt update
-	$ sudo apt upgrade
-	$ sudo apt install git gawk make texinfo bison flex build-essential python3 zlib1g-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.0-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog 
-
-### Install RISC-V GCC Cross-Compiler
-
-To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V.   This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. 
-
-	$ git clone https://github.com/riscv/riscv-gnu-toolchain 
-	$ cd riscv-gnu-toolchain 
-	$ git checkout 2023.01.31 
-	$ ./configure --prefix=$RISCV --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
-	$ make --jobs
-
-Note: make --jobs will reduce compile time by compiling in parallel.  However, adding this option could dramatically increase the memory utilization of your local machine.
-
-### Install elf2hex
-
-We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with:
-
-	$ cd $RISCV
-	$ export PATH=$RISCV/bin:$PATH
-	$ git clone https://github.com/sifive/elf2hex.git
-	$ cd elf2hex
-	$ autoreconf -i
-	$ ./configure --target=riscv64-unknown-elf --prefix=$RISCV
-	$ make 
-	$ make install 
-
-Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t handle programs that start at 0x80000000. The SiFive version above is touchy to install. For example, if Python version 2.x is in your path, it won’t install correctly.  Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin at the time of compilation, or elf2hex won’t work properly.
-
-### Install RISC-V Spike Simulator
-
-Spike also takes a while to install and compile, but this can be done concurrently with the GCC installation.  After the build, we need to change two Makefiles to support atomic instructions .
-
-	$ cd $RISCV
-	$ git clone https://github.com/riscv-software-src/riscv-isa-sim
-	$ mkdir riscv-isa-sim/build
-	$ cd riscv-isa-sim/build
-	$ ../configure --prefix=$RISCV 
-	$ make --jobs
-	$ make install 
-	$ cd ../arch_test_target/spike/device
-	$ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
-	$ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include 
-
-### Install Sail Simulator
-
-Sail is the new golden reference model for RISC-V.  Sail is written in OCaml, which is an object-oriented extension of ML, which in turn is a functional programming language suited to formal verification.  OCaml is installed with the opam OCcaml package manager. Sail has so many dependencies that it can be difficult to install.
-
-On Ubuntu, apt-get makes opam installation fairly simple.
-
-$ sudo apt-get install opam  build-essential libgmp-dev z3 pkg-config zlib1g-dev
-
-If you are on RedHat/Rocky Linux 8, installation is much more difficult because packages are not available in the default package manager and some need to be built from source.
-
-	$ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)"
-	When prompted, put it in /usr/bin
-	$ sudo yum groupinstall 'Development Tools'
-	$ sudo yum -y install gmp-devel
-	$ sudo yum -y install zlib-devel
-	$ git clone https://github.com/Z3Prover/z3.git 
-	$ cd z3
-	$ python scripts/mk_make.py
-	$ cd build
-	$ make
-	$ sudo make install
-	$ cd ../..
-	$ sudo pip3 install chardet==3.0.4
-	$ sudo pip3 install urllib3==1.22
-
-Once you have installed the packages on either Ubuntu or RedHat, use opam to install the OCaml compiler and Sail.  Run as the cad user because you will be installing Sail in $RISCV.
-
-	$ sudo su cad
-	$ opam init -y --disable-sandboxing
-	$ opam switch create ocaml-base-compiler.4.06.1
-	$ opam install sail -y
-
-Now you can clone and compile Sail-RISCV.  This will take a while.
-
-	$ eval $(opam config env)
-	$ cd $RISCV
-	$ git clone https://github.com/riscv/sail-riscv.git
-	$ cd sail-riscv
-	$ make
-	$ ARCH=RV32 make
-	$ ARCH=RV64 make
-	$ exit
-	$ sudo su
-	$ export RISCV=/opt/riscv
-	$ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
-	$ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
-	$ exit
-
-### Install riscof
-
-riscof is a Python library used as the RISC-V compatibility framework test an implementation such as Wally or Spike against the Sail golden reference. It will be used to compile the riscv-arch-test suite.  
-
-It is most convenient if the sysadmin installs riscof into the server’s Python libraries:
-
-	$ sudo pip3 install testresources
-	$ sudo pip3 install riscof --ignore-installed PyYAML
-
-However, riscof can also be installed and run locally by individual users.
-
-### Other Python libraries
-
-While a sysadmin is installing Python libraries, it's worth doing some more that will be needed by visualization scripts.
-
-	$ sudo pip3 install matplotlib scipy sklearn adjustText lief
-
-### Install Verilator
-
-Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code.  It is needed to run regression.
-$ sudo apt install verilator 
-
-### Install QEMU Simulator
-
-QEMU is another simulator used when booting Linux in Chapter 17. You can optionally install it using the following commands. 
-
-<SIDEBAR>
-The QEMU patch changes the VirtIO driver to match the Wally peripherals, and also adds print statements to log the state of the CSRs (see Section 2.5XREF).
-</END>
-
-	$ cd $RISCV
-	$ git clone --recurse-submodules https://github.com/qemu/qemu
-	$ cd qemu
-	$ git checkout v6.2.0    # last version tested; newer versions might be ok
-	$ ./configure --target-list=riscv64-softmmu --prefix=$RISCV
-	$ make --jobs
-	$ make install
-
-### Cross-Compile Buildroot Linux
-
-Building Linux is only necessary for exploring the boot process in Chapter 17.  Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details.
-
-Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2.  However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot.
-
-To configure and build Buildroot:
-
-	$ cd $RISCV
-	$ export WALLY=~/riscv-wally  # make sure you haven’t sourced ~/riscv-wally/setup.sh by now
-	$ git clone https://github.com/buildroot/buildroot.git
-	$ cd buildroot
-	$ git checkout 2021.05 # last tested working version
-	$ cp -r $WALLY/linux/buildroot-config-src/wally ./board
-	$ cp ./board/wally/main.config .config
-	$ make --jobs
-
-To generate disassembly files and the device tree, run another make script.  Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb.
-
-$ source ~/riscv-wally/setup.sh
-$ cd $WALLY/linux/buildroot-scripts
-$ make all
-
-Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images.
-
-### Generate load images for linux boot
-
-The Questa linux boot uses preloaded bootram and ram memory.  We use QEMU to generate these preloaded memory files.  Files output in $RISCV/linux-testvectors
-
-	cd cvw/linux/testvector-generation
-	./genInitMem.sh
-
-This may require changing file permissions to the linux-testvectors directory.
-
-### Generate QEMU linux trace
-
-The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU.  To do this QEMU outputs a log file consisting of all instructions executed.  Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU.  Generating this trace will take more than 24 hours.
-
-	cd cvw/linux/testvector-generation
-	./genTrace.sh
-=======
 This section describes the open source toolchain installation.  The
 current version of the toolchain has been tested on Ubuntu and Red
-Hat/Rocky 8.  The latter is more difficult to install and Ubuntu may
-be more recommended for new users.  The <pre>wally-tool-chain-install.sh</pre> script inside
-the bin directory can be utilized to install the toolchain on Ubuntu
-using sudo.
->>>>>>> a7e00e438681f72433225abccf3aef5f3c8913e7
+Hat/Rocky 8 Linux.  Ubuntu works more smoothly and is recommended
+unless you have a compelling need for RedHat.  
+Ubuntu users can install the tools by running
+
+	$ sudo $WALLY/bin/wally-tool-chain-install.sh
 
 ### Download Synthesis Libraries
 

From 16d9fac00474bcecee19663f12d263f01ea2ddf6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 09:05:37 -0700
Subject: [PATCH 06/12] README updates

---
 README.md                       | 4 ++++
 bin/wally-tool-chain-install.sh | 9 +++++++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 64243248d..b93a5fc50 100644
--- a/README.md
+++ b/README.md
@@ -65,10 +65,14 @@ This section describes the open source toolchain installation.  The
 current version of the toolchain has been tested on Ubuntu and Red
 Hat/Rocky 8 Linux.  Ubuntu works more smoothly and is recommended
 unless you have a compelling need for RedHat.  
+
 Ubuntu users can install the tools by running
 
 	$ sudo $WALLY/bin/wally-tool-chain-install.sh
 
+See wally-tool-chain-install.sh for a detailed description of each component,
+or to issue the commands one at a time to install on the command line.
+
 ### Download Synthesis Libraries
 
 For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library.  Clone the OSU 12-track cell library for the Skywater 130 nm process:
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 7def96852..2f058c46f 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -34,18 +34,19 @@ export PATH=$PATH:$RISCV/bin
 set -e # break on error
 
 # Modify accordingly for your machine
+# Increasing NUM_THREADS will speed up parallel compilation of the tools
 NUM_THREADS=1 # for low memory machines > 16GiB
 #NUM_THREADS=8  # for >= 32GiB
 #NUM_THREADS=16  # for >= 64GiB
 
 sudo mkdir -p $RISCV
 
-# Update and Upgrade (see https://itsfoss.com/apt-update-vs-upgrade/)
+# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
 apt update
 apt upgrade
 
 # INSTALL 
-apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev
+apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev
 
 # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
 if ! command -v python &> /dev/null
@@ -55,6 +56,10 @@ then
 fi
 
 # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain)
+# To install GCC from source can take hours to compile. 
+#This configuration enables multilib to target many flavors of RISC-V.   
+# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. 
+
 cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain

From f4b252522eb5fd349d1adbfa47b94258cef4c45e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 09:06:05 -0700
Subject: [PATCH 07/12] Coverage improvements

---
 sim/regression-wally      | 8 ++++++--
 tests/coverage/badinstr.S | 1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/sim/regression-wally b/sim/regression-wally
index d10e35655..77ab05c15 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -126,10 +126,14 @@ for test in ahbTests:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
+tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", 
+             "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
 if (coverage):  # delete all but 64gc tests when running coverage
     configs = []
-    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
+    tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
+                 "arch64zi", "wally64a", "wally64periph", "wally64priv", 
+                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
+                 "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
     coverStr = '-coverage'
 else:
    coverStr = ''
diff --git a/tests/coverage/badinstr.S b/tests/coverage/badinstr.S
index 7714ab07b..174ea0aef 100644
--- a/tests/coverage/badinstr.S
+++ b/tests/coverage/badinstr.S
@@ -36,6 +36,7 @@ main:
     .word 0x00004023  // Illegal store instruction
     .word 0x0400003B  // Illegal RW or MulDivW instruction
     .word 0x00007067  // Illegal JALR instruction
+    .word 0x00002063  // Illegal branch instruction
 
     j done
 

From 3a9b40ff1dc9f0f21187bb38d73a4b217fa23da6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 09:31:17 -0700
Subject: [PATCH 08/12] installation script update

---
 bin/wally-tool-chain-install.sh | 82 ++++++++++++++++++++++-----------
 synthDC/ppa/ppaAnalyze.py       |  2 +-
 2 files changed, 56 insertions(+), 28 deletions(-)

diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 2f058c46f..4d484be60 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -44,9 +44,10 @@ sudo mkdir -p $RISCV
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
 apt update
 apt upgrade
+apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator
 
-# INSTALL 
-apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev
+# Other python libraries used through the book.
+pip3 install matplotlib scipy scikit-learn adjustText lief
 
 # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
 if ! command -v python &> /dev/null
@@ -59,6 +60,10 @@ fi
 # To install GCC from source can take hours to compile. 
 #This configuration enables multilib to target many flavors of RISC-V.   
 # This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. 
+# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes
+# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly.
+# However GCC12.x is needed for bit manipulation instructions.  There is an open issue to fix this:
+# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188
 
 cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
@@ -69,6 +74,12 @@ make -j ${NUM_THREADS}
 make install
 
 # elf2hex (https://github.com/sifive/elf2hex)
+#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. 
+# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t 
+# handle programs that start at 0x80000000. The SiFive version above is touchy to install. 
+# For example, if Python version 2.x is in your path, it won’t install correctly. 
+# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin 
+# at the time of compilation, or elf2hex won’t work properly.
 cd $RISCV
 export PATH=$RISCV/bin:$PATH
 git clone https://github.com/sifive/elf2hex.git
@@ -78,11 +89,6 @@ autoreconf -i
 make
 make install
 
-# Update Python3.6 for QEMU
-apt-get -y update
-apt-get -y install python3-pip
-apt-get -y install pkg-config
-apt-get -y install libglib2.0-dev
 
 # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html)
 cd $RISCV
@@ -105,17 +111,23 @@ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
 sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 
 # Sail (https://github.com/riscv/sail-riscv)
-cd $RISCV
-apt-get install -y opam  build-essential libgmp-dev z3 pkg-config zlib1g-dev
-git clone https://github.com/Z3Prover/z3.git
-cd z3
-python scripts/mk_make.py
-cd build
-make  -j ${NUM_THREADS}
-make install
-cd ../..
-pip3 install chardet==3.0.4
-pip3 install urllib3==1.22
+#Sail is the new golden reference model for RISC-V.  Sail is written in OCaml, which 
+# is an object-oriented extension of ML, which in turn is a functional programming 
+#language suited to formal verification.  OCaml is installed with the opam OCcaml 
+#package manager. Sail has so many dependencies that it can be difficult to install.
+# This script forks for Ubuntu.
+
+#cd $RISCV
+#git clone https://github.com/Z3Prover/z3.git
+#cd z3
+#python scripts/mk_make.py
+#cd build
+#make  -j ${NUM_THREADS}
+#make install
+#cd ../..
+#pip3 install chardet==3.0.4
+#pip3 install urllib3==1.22
+
 opam init -y --disable-sandboxing
 opam switch create ocaml-base-compiler.4.06.1
 opam install sail -y 
@@ -135,16 +147,32 @@ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 pip3 install testresources
 pip3 install riscof --ignore-installed PyYAML
 
+# RedHat / Rocky 8 Linux doesn't have the packages in the default pacakge
+# manager.  Instead, build them form source using:
+#	$ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)"
+#	When prompted, put it in /usr/bin
+#	$ sudo yum groupinstall 'Development Tools'
+#	$ sudo yum -y install gmp-devel
+#	$ sudo yum -y install zlib-devel
+#	$ git clone https://github.com/Z3Prover/z3.git 
+#	$ cd z3
+#	$ python scripts/mk_make.py
+#	$ cd build
+#	$ make
+#	$ sudo make install
+#	$ cd ../..
+#	$ sudo pip3 install chardet==3.0.4
+#	$ sudo pip3 install urllib3==1.22
+
+
 # Verilator
-apt install -y verilator
+#apt install -y verilator
 
 # install github cli (gh)
-type -p curl >/dev/null || sudo apt install curl -y
-curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \
-&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
-&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
-&& sudo apt update \
-&& sudo apt install gh -y
+#type -p curl >/dev/null || sudo apt install curl -y
+#curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \
+#&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
+#&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
+#&& sudo apt update \
+#&& sudo apt install gh -y
 
-# Other python libraries used through the book.
-pip3 install matplotlib scipy scikit-learn adjustText lief
diff --git a/synthDC/ppa/ppaAnalyze.py b/synthDC/ppa/ppaAnalyze.py
index 2dce62ae5..03758cdf6 100755
--- a/synthDC/ppa/ppaAnalyze.py
+++ b/synthDC/ppa/ppaAnalyze.py
@@ -11,7 +11,7 @@ import matplotlib.lines as lines
 import matplotlib as mpl
 import numpy as np
 from collections import namedtuple
-import sklearn.metrics as skm
+import sklearn.metrics as skm  # depricated, will need to replace with scikit-learn
 import os
 
 def synthsfromcsv(filename):

From 67186c44982b9251b98668df03ec23a9b53d4f18 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 09:33:56 -0700
Subject: [PATCH 09/12] install docs

---
 bin/wally-tool-chain-install.sh | 40 ++++++---------------------------
 1 file changed, 7 insertions(+), 33 deletions(-)

diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 4d484be60..dfe72896f 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -99,6 +99,8 @@ make -j ${NUM_THREADS}
 make install
 
 # Spike (https://github.com/riscv-software-src/riscv-isa-sim)
+# Spike also takes a while to install and compile, but this can be done concurrently 
+#with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions.
 cd $RISCV
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 mkdir -p riscv-isa-sim/build
@@ -111,12 +113,13 @@ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
 sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
 
 # Sail (https://github.com/riscv/sail-riscv)
-#Sail is the new golden reference model for RISC-V.  Sail is written in OCaml, which 
+# Sail is the new golden reference model for RISC-V.  Sail is written in OCaml, which 
 # is an object-oriented extension of ML, which in turn is a functional programming 
-#language suited to formal verification.  OCaml is installed with the opam OCcaml 
-#package manager. Sail has so many dependencies that it can be difficult to install.
-# This script forks for Ubuntu.
+# language suited to formal verification.  OCaml is installed with the opam OCcaml 
+# package manager. Sail has so many dependencies that it can be difficult to install.
+# This script works for Ubuntu.
 
+# Do these commands only for RedHat / Rocky 8 to build from source.
 #cd $RISCV
 #git clone https://github.com/Z3Prover/z3.git
 #cd z3
@@ -147,32 +150,3 @@ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 pip3 install testresources
 pip3 install riscof --ignore-installed PyYAML
 
-# RedHat / Rocky 8 Linux doesn't have the packages in the default pacakge
-# manager.  Instead, build them form source using:
-#	$ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)"
-#	When prompted, put it in /usr/bin
-#	$ sudo yum groupinstall 'Development Tools'
-#	$ sudo yum -y install gmp-devel
-#	$ sudo yum -y install zlib-devel
-#	$ git clone https://github.com/Z3Prover/z3.git 
-#	$ cd z3
-#	$ python scripts/mk_make.py
-#	$ cd build
-#	$ make
-#	$ sudo make install
-#	$ cd ../..
-#	$ sudo pip3 install chardet==3.0.4
-#	$ sudo pip3 install urllib3==1.22
-
-
-# Verilator
-#apt install -y verilator
-
-# install github cli (gh)
-#type -p curl >/dev/null || sudo apt install curl -y
-#curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \
-#&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
-#&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
-#&& sudo apt update \
-#&& sudo apt install gh -y
-

From 533972d178a84840401d0cc2a657b232946f2c4a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 09:36:50 -0700
Subject: [PATCH 10/12] Increased NumThreads to 0

---
 bin/wally-tool-chain-install.sh | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index dfe72896f..798fe51bb 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -35,15 +35,15 @@ set -e # break on error
 
 # Modify accordingly for your machine
 # Increasing NUM_THREADS will speed up parallel compilation of the tools
-NUM_THREADS=1 # for low memory machines > 16GiB
+NUM_THREADS=2 # for low memory machines > 16GiB
 #NUM_THREADS=8  # for >= 32GiB
 #NUM_THREADS=16  # for >= 64GiB
 
 sudo mkdir -p $RISCV
 
 # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/)
-apt update
-apt upgrade
+apt update -y
+apt upgrade -y
 apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator
 
 # Other python libraries used through the book.

From 60d807f1b080aad030a2902adeb1bfd795fb6896 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 09:39:03 -0700
Subject: [PATCH 11/12] Removed 130 nm library and cli from README

---
 README.md | 22 ----------------------
 1 file changed, 22 deletions(-)

diff --git a/README.md b/README.md
index b93a5fc50..a03625217 100644
--- a/README.md
+++ b/README.md
@@ -72,28 +72,6 @@ Ubuntu users can install the tools by running
 
 See wally-tool-chain-install.sh for a detailed description of each component,
 or to issue the commands one at a time to install on the command line.
-
-### Download Synthesis Libraries
-
-For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library.  Clone the OSU 12-track cell library for the Skywater 130 nm process:
-
-	$ cd $RISCV
-	$ mkdir cad
-	$ mkdir cad/lib
-	$ cd cad/lib
-	$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12
-
-### Install github cli
-
-The github cli allows users to directly issue pull requests from their fork back to openhwgroup/cvw using the command line.
-
-	$ type -p curl >/dev/null || sudo apt install curl -y
-	$ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ && sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \
-	&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \
-	&& sudo apt update \
-	&& sudo apt install gh -y
-
-
 ## Installing EDA Tools
 
 Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs.   Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text.  The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally.  It is anticipated that additional tools may be documented later after this is text is published to improve use and access.

From 121d1cea62edb765a3a83483e0729b48a7b892ba Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 23 Mar 2023 10:55:32 -0700
Subject: [PATCH 12/12] Added csrwrites.S test case for privileged tests

---
 .gitignore                 |   1 -
 sim/regression-wally       |   6 +-
 src/ieu/bmu/bmuctrl.sv     | 174 ++++++++++++++++---------------------
 src/privileged/csrs.sv     |   6 +-
 testbench/tests.vh         |   3 +-
 tests/coverage/Makefile    |   5 +-
 tests/coverage/csrwrites.S |  35 ++++++++
 7 files changed, 123 insertions(+), 107 deletions(-)
 create mode 100644 tests/coverage/csrwrites.S

diff --git a/.gitignore b/.gitignore
index 1f8e8b158..6e9920603 100644
--- a/.gitignore
+++ b/.gitignore
@@ -111,6 +111,5 @@ sim/imperas.log
 sim/results-error/
 sim/test1.rep
 sim/vsim.log
-tests/coverage/*.S
 tests/coverage/*.elf
 *.elf.memfile
\ No newline at end of file
diff --git a/sim/regression-wally b/sim/regression-wally
index 77ab05c15..122b04b51 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -130,10 +130,14 @@ tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64z
              "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
 if (coverage):  # delete all but 64gc tests when running coverage
     configs = []
-    tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
+    tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", 
                  "arch64zi", "wally64a", "wally64periph", "wally64priv", 
                  "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
                  "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
+#    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
+#                 "arch64zi", "wally64a", "wally64periph", "wally64priv", 
+#                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
+#                 "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
     coverStr = '-coverage'
 else:
    coverStr = ''
diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index ae401ef88..645e711cc 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -76,106 +76,84 @@ module bmuctrl(
 
   // Main Instruction Decoder
   always_comb begin
-    BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1};  // default: Illegal instruction
-    casez({OpD, Funct7D, Funct3D})
     // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
-      // ZBS
-      17'b0010011_0100100_001: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0;  // bclri
-      17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0;  // bclri (rv64)
-      17'b0010011_0100100_101: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0;  // bexti
-      17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0;  // bexti (rv64)
-      17'b0010011_0110100_001: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0;  // binvi
-      17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0;  // binvi (rv64)
-      17'b0010011_0010100_001: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0;  // bseti
-      17'b0010011_0010101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) 
-                                 BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0;  // bseti (rv64)
-      17'b0110011_0100100_001: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0;  // bclr
-      17'b0110011_0100100_101: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0;  // bext
-      17'b0110011_0110100_001: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0;  // binv
-      17'b0110011_0010100_001: if (`ZBS_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0;  // bset
-      17'b0110011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0;  // sra, srl, sll
-      17'b0010011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0;  // srai, srli, slli
-      17'b0111011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0;  // sraw, srlw, sllw
-      17'b0011011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0;  // sraiw, srliw, slliw
+    BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1};  // default: Illegal instruction
+    if (`ZBA_SUPPORTED)
+      casez({OpD, Funct7D, Funct3D})
+        17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh1add
+        17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh2add
+        17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh3add
+      endcase
+    if (`ZBA_SUPPORTED & `XLEN==64)
+      casez({OpD, Funct7D, Funct3D})
+        17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh1add.uw
+        17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh2add.uw
+        17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh3add.uw
+        17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0;  // add.uw
+        17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0;  // slli.uw
+      endcase
+    if (`ZBB_SUPPORTED)
+      casez({OpD, Funct7D, Funct3D})
+        17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0;  // rol
+        17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0;  // ror
+        17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010))
+                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // sign extend instruction
+                                else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
+                                  BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0;  // count instruction
+        17'b0110011_0000100_100: if (`XLEN == 32)
+                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
+        17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0;  // andn
+        17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0;  // orn
+        17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0;  // xnor
+        17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
+                                  BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0;  // rev8
+        17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
+                                  BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0;  // orc.b
+        17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0;  // max
+        17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0;  // maxu
+        17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0;  // min
+        17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0;  // minu
+      endcase
+    if (`ZBB_SUPPORTED & `XLEN==64)
+      casez({OpD, Funct7D, Funct3D})
+        17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0;  // rolw
+        17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0;  // rorw
+        17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0;  // rori (rv64)
+        17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0;  // roriw 
+        17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
+                                  BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0;  // count word instruction
+        17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0;  // zexth (rv64)
+      endcase
+    if (`ZBC_SUPPORTED)
+      casez({OpD, Funct7D, Funct3D})
+        17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0;  // ZBC instruction
+      endcase
+    if (`ZBS_SUPPORTED) // ZBS
+      casez({OpD, Funct7D, Funct3D})
+        17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0;  // bclri
+        17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0;  // bexti
+        17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0;  // binvi
+        17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0;  // bseti
+        17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0;  // bclr
+        17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0;  // bext
+        17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0;  // binv
+        17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0;  // bset
+      endcase
+    if (`ZBS_SUPPORTED & `XLEN==64) // ZBS 64-bit
+      casez({OpD, Funct7D, Funct3D})
+        17'b0010011_0100101_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0;  // bclri (rv64)
+        17'b0010011_0100101_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0;  // bexti (rv64)
+        17'b0010011_0110101_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0;  // binvi (rv64)
+        17'b0010011_0010101_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0;  // bseti (rv64)
+      endcase
+    if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used
+      casez({OpD, Funct7D, Funct3D})
+        17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0;  // sra, srl, sll
+        17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0;  // srai, srli, slli
+        17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0;  // sraw, srlw, sllw
+        17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0;  // sraiw, srliw, slliw
+      endcase
       // ZBC
-      17'b0110011_0000101_0??: if (`ZBC_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0;  // ZBC instruction
-      // ZBA
-      17'b0110011_0010000_010: if (`ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh1add
-      17'b0110011_0010000_100: if (`ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh2add
-      17'b0110011_0010000_110: if (`ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh3add
-      17'b0111011_0010000_010: if (`XLEN == 64 & `ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh1add.uw
-      17'b0111011_0010000_100: if (`XLEN == 64 & `ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh2add.uw
-      17'b0111011_0010000_110: if (`XLEN == 64 & `ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0;  // sh3add.uw
-      17'b0111011_0000100_000: if (`XLEN == 64 & `ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0;  // add.uw
-      17'b0011011_000010?_001: if (`XLEN == 64 & `ZBA_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0;  // slli.uw
-      // ZBB
-      17'b0110011_0110000_001: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0;  // rol
-      17'b0111011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0;  // rolw
-      17'b0110011_0110000_101: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0;  // ror
-      17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0;  // rorw
-      //17'b0010011_0110000_101: if (`ZBB_SUPPORTED)
-      //                           BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0;  // rori (rv32)
-      17'b0010011_011000?_101: if ((`XLEN == 64 | ~Funct7D[0]) & `ZBB_SUPPORTED) 
-                                 BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0;  // rori (rv64)
-      17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) 
-                                 BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0;  // roriw 
-      17'b0010011_0110000_001: if (`ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010))
-                                 BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // sign extend instruction
-                               else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])))
-                                 BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0;  // count instruction
-      17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])))
-                                 BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0;  // count word instruction
-      17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0;  // zexth (rv64)
-      17'b0110011_0000100_100: if (`XLEN == 32 & `ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
-      17'b0110011_0100000_111: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0;  // andn
-      17'b0110011_0100000_110: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0;  // orn
-      17'b0110011_0100000_100: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0;  // xnor
-      17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000))
-                                 BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0;  // rev8
-      17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111)
-                                 BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0;  // orc.b
-      17'b0110011_0000101_110: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0;  // max
-      17'b0110011_0000101_111: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0;  // maxu
-      17'b0110011_0000101_100: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0;  // min
-      17'b0110011_0000101_101: if (`ZBB_SUPPORTED)
-                                 BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0;  // minu
-    endcase
   end
 
   // Unpack Control Signals
diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv
index 1a5906653..b13b620b0 100644
--- a/src/privileged/csrs.sv
+++ b/src/privileged/csrs.sv
@@ -100,10 +100,10 @@ module csrs #(parameter
   else
     assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
   flopenr #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
-  if (`SSTC_SUPPORTED) begin
-    if (`XLEN == 64)
+  if (`SSTC_SUPPORTED) begin : sstc
+    if (`XLEN == 64) begin : sstc64
       flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
-    else begin
+    end else begin : sstc32
       flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]);
       flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]);
     end
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 67152fe7c..83729f964 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -44,7 +44,8 @@ string tvpaths[] = '{
 
   string coverage64gc[] = '{
     `COVERAGE,
-    "badinstr"
+    "badinstr",
+    "csrwrites"
   };
 
   string coremark[] = '{
diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile
index 8742dee63..d3686f8eb 100644
--- a/tests/coverage/Makefile
+++ b/tests/coverage/Makefile
@@ -15,12 +15,11 @@ all: $(OBJECTS)
 
 %.elf.objdump: %.elf
 
+# Change many things if bit width isn't 64
 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
-	# Change many things if bit width isn't 64
-	echo $@
 	riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \
 	    -nostartfiles -T../../examples/link/link.ld $<
-	riscv64-unknown-elf-objdump -D $@ > $@.objdump
+	riscv64-unknown-elf-objdump -S $@ > $@.objdump
 	riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
 	extractFunctionRadix.sh $@.objdump
     
diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S
new file mode 100644
index 000000000..76e310e5f
--- /dev/null
+++ b/tests/coverage/csrwrites.S
@@ -0,0 +1,35 @@
+///////////////////////////////////////////
+// csrwrites.S
+//
+// Written: David_Harris@hmc.edu 21 March 2023
+//
+// Purpose: Test writes to CSRs
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+#include "WALLY-init-lib.h"
+
+main:
+    csrrw t0, stimecmp, t0
+    csrrw t0, satp, t0
+    csrrw t0, stvec, t0
+    csrrw t0, sscratch, t0
+
+    j done