From d8170e9dd341f6557c509d542cfb7866624ef471 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 15 Feb 2022 19:50:44 +0000
Subject: [PATCH] Mostly removed N_SUPPORTED

---
 pipelined/src/privileged/csri.sv | 9 ---------
 pipelined/src/privileged/csrm.sv | 5 ++---
 pipelined/src/privileged/trap.sv | 1 -
 3 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv
index 9520ffb7b..974b3616f 100644
--- a/pipelined/src/privileged/csri.sv
+++ b/pipelined/src/privileged/csri.sv
@@ -111,14 +111,5 @@ module csri #(parameter
       SIP_REGW = 12'b0;
       SIE_REGW = 12'b0;
     end
-
-    // User Modes iterrupts depricated
-    /*if (`U_SUPPORTED & `N_SUPPORTED) begin
-      UIP_REGW = IP_REGW & MIDELEG_REGW & SIDELEG_REGW & 'h111; // only delegated interrupts visible
-      UIE_REGW = IE_REGW & MIDELEG_REGW & SIDELEG_REGW & 'h111; // only delegated interrupts visible
-    end else begin
-      UIP_REGW = 12'b0;
-      UIE_REGW = 12'b0;
-    end */
   end
 endmodule
diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv
index ecb705e18..c66d2d38a 100644
--- a/pipelined/src/privileged/csrm.sv
+++ b/pipelined/src/privileged/csrm.sv
@@ -146,7 +146,7 @@ module csrm #(parameter
 
   // CSRs
   flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); 
-  if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist
+  if (`S_SUPPORTED) begin:deleg // DELEG registers should exist
     flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW);
     flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW);
   end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0;
@@ -165,8 +165,7 @@ module csrm #(parameter
   logic [5:0] entry;
   always_comb begin
     entry = '0;
-    IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) & 
-                          (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
+    IllegalCSRMAccessM = !(`S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
     if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
       CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0];
     else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index da80c8993..a5273225b 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -84,7 +84,6 @@ module trap (
   assign TrapM = ExceptionM | InterruptM; // *** clean this up later DH
   assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
   assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
-  assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED;
   assign RetM = mretM | sretM;
 
   always_comb