From 44e87f3e3e2a6a23fc43b71ef8e991cfae38bab0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 Feb 2024 12:46:14 -0600 Subject: [PATCH 1/8] First cut at removing the linux testbench and merging build root into the main testbench. --- sim/wally-batch.do | 33 +++------------------------------ testbench/testbench.sv | 22 ++++++++++++++++++++-- testbench/tests.vh | 6 ++++++ 3 files changed, 29 insertions(+), 32 deletions(-) diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 83a4da90c..127cb9ec7 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -51,35 +51,7 @@ if {$argc >= 3} { # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32imc rv32imc -if {$2 eq "buildroot"} { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - if { $coverage } { - echo "wally-batch buildroot coverage" - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt +cover=sbecf - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 -cover - } else { - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 - } - - run -all - run -all - exec ./slack-notifier/slack-notifier.py -} elseif {$2 eq "buildroot-no-trace"} { - vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 - - #-- Run the Simulation - echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" - echo "Don't forget to change DEBUG_LEVEL = 0." - echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" - run -all - run -all - exec ./slack-notifier/slack-notifier.py -} elseif {$2 eq "configOptions"} { +if {$2 eq "configOptions"} { # set arguments " " # for {set i 5} {$i <= $argc} {incr i} { # append arguments "\$$i " @@ -111,12 +83,13 @@ if {$2 eq "buildroot"} { vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbecf vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -coverage } else { - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt + vopt +acc wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 } # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 # power add generates the logging necessary for said generation. # power add -r /dut/core/* + do wave.do run -all # power off -r /dut/core/* } diff --git a/testbench/testbench.sv b/testbench/testbench.sv index e86c5a9e1..04ec74407 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -40,6 +40,7 @@ module testbench; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; + parameter RISCV_DIR = "/opt/riscv"; `include "parameter-defs.vh" @@ -134,6 +135,7 @@ module testbench; "arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; "arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad; + "buildroot": tests = buildroot; endcase end else begin // RV32 case (TEST) @@ -210,7 +212,7 @@ module testbench; logic ResetCntRst; logic CopyRAM; - string signame, memfilename, pathname; + string signame, memfilename, bootmemfilename, pathname; integer begin_signature_addr, end_signature_addr, signature_size; assign ResetThreshold = 3'd5; @@ -279,7 +281,12 @@ module testbench; always @(posedge clk) begin if(SelectTest) begin if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; + else if(TEST == "buildroot") begin + memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"}; + bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; + end else memfilename = {pathname, tests[test], ".elf.memfile"}; + $display("!!!!!!!!!!!!!!!!!!!!!memfilename is %s \n", memfilename); if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; @@ -352,6 +359,8 @@ module testbench; integer StartIndex; integer EndIndex; integer BaseIndex; + integer memFile; + integer readResult; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin @@ -373,7 +382,16 @@ module testbench; end else if (P.BUS_SUPPORTED) begin : bus_supported always @(posedge clk) begin if (LoadMem) begin - $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (TEST == "buildroot") begin + memFile = $fopen(bootmemfilename, "rb"); + readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile); + $fclose(memFile); + memFile = $fopen(memfilename, "rb"); + readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile); + $fclose(memFile); + end else + $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64 diff --git a/testbench/tests.vh b/testbench/tests.vh index 42f3d703a..7282895e2 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -31,6 +31,7 @@ `define EMBENCH "4" `define CUSTOM "5" `define COVERAGE "6" +`define BUILDROOT "7" string tvpaths[] = '{ "$RISCV/imperas-riscv-tests/work/", @@ -71,6 +72,11 @@ string tvpaths[] = '{ "pmpadrdecs" }; + string buildroot[] = '{ + `BUILDROOT, + "buildroot" + }; + string coremark[] = '{ `COREMARK, "coremark.bare.riscv" From 17380a68d5fade4aa4f07a0d26c2be68c167d26c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 Feb 2024 13:03:48 -0600 Subject: [PATCH 2/8] Moved buildroot testbench to the main testbench. However I don't have a positive control or negative indicator to say when the test completes or passes. --- sim/wally-batch.do | 3 +-- testbench/testbench.sv | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 127cb9ec7..1b157ffed 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -83,13 +83,12 @@ if {$2 eq "configOptions"} { vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbecf vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -coverage } else { - vopt +acc wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 } # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 # power add generates the logging necessary for said generation. # power add -r /dut/core/* - do wave.do run -all # power off -r /dut/core/* } diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 04ec74407..feec06c01 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -384,10 +384,10 @@ module testbench; if (LoadMem) begin if (TEST == "buildroot") begin memFile = $fopen(bootmemfilename, "rb"); - readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile); + readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile); $fclose(memFile); memFile = $fopen(memfilename, "rb"); - readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile); + readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile); $fclose(memFile); end else $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); From d5a7cb0ab0dc71b528e52d3c409b32e1914fb689 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 Feb 2024 13:05:11 -0600 Subject: [PATCH 3/8] Updated comments in do file. --- sim/wally-batch.do | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 1b157ffed..74bb5417d 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -58,8 +58,8 @@ if {$2 eq "configOptions"} { # } # puts $arguments # set options eval $arguments - # **** fix this so we can pass any number of +defines. - # only allows 3 right now + # **** fix this so we can pass any number of +defines or top level params. + # only allows 1 right now vlog -lint -work wkdir/work_${1}_${3}_${4} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation From c9176f108e6626e1bd097ec7bc8457595032f039 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 Feb 2024 13:09:31 -0600 Subject: [PATCH 4/8] Fixed paths to buildroot objdump label and addr files. --- testbench/testbench.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index feec06c01..33ffa8c61 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -290,6 +290,9 @@ module testbench; if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; + end else if (TEST == "buildroot") begin + ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"}; + ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"}; end else begin ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; From 8b5970fdc4442cfdfadca12bfffe8a303908a29f Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 Feb 2024 13:19:48 -0600 Subject: [PATCH 5/8] Buildroot now reports every 100K instructions as before. --- testbench/testbench.sv | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 33ffa8c61..b55d8e515 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -286,7 +286,6 @@ module testbench; bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"}; end else memfilename = {pathname, tests[test], ".elf.memfile"}; - $display("!!!!!!!!!!!!!!!!!!!!!memfilename is %s \n", memfilename); if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; @@ -540,6 +539,12 @@ module testbench; DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); + logic [P.XLEN-1:0] Minstret; + assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + always @(negedge clk) begin + if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); + end + task automatic CheckSignature; // This task must be declared inside this module as it needs access to parameter P. There is // no way to pass P to the task unless we convert it to a module. From 58580445ab97be3504134157f8581e76489b93ce Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 5 Feb 2024 14:41:52 -0600 Subject: [PATCH 6/8] Only output instruction count when the csrs are implemented. --- testbench/testbench.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b55d8e515..c65ab8a42 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -539,10 +539,12 @@ module testbench; DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); - logic [P.XLEN-1:0] Minstret; - assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; - always @(negedge clk) begin - if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); + if(P.ZICSR_SUPPORTED) begin + logic [P.XLEN-1:0] Minstret; + assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + always @(negedge clk) begin + if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); + end end task automatic CheckSignature; From da65928f04e147a6c6a4ee00f361647646b1ac05 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 6 Feb 2024 16:07:41 -0600 Subject: [PATCH 7/8] Fixed issue with branch deriv configs. --- config/rv32gc/config.vh | 11 ----------- sim/regression-wally | 2 +- testbench/testbench.sv | 6 ++++-- 3 files changed, 5 insertions(+), 14 deletions(-) diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 8b4b78a4f..843f55530 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -154,22 +154,11 @@ localparam PLIC_SPI_ID = 32'd6; localparam PLIC_SDC_ID = 32'd9; localparam BPRED_SUPPORTED = 1; -// this is an annoying hack for the branch predictor parameterization override. -`ifdef BPRED_OVERRIDE -localparam BPRED_TYPE = `BPRED_TYPE; -localparam BPRED_SIZE = `BPRED_SIZE; -`else localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT localparam BPRED_SIZE = 32'd10; -`endif localparam BPRED_NUM_LHR = 32'd6; -`ifdef BTB_OVERRIDE -localparam BTB_SIZE = `BTB_SIZE; -localparam RAS_SIZE = `RAS_SIZE; -`else localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; -`endif localparam INSTR_CLASS_PRED = 1; localparam SVADU_SUPPORTED = 1; diff --git a/sim/regression-wally b/sim/regression-wally index 4c3b630c4..757282b7c 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -72,7 +72,7 @@ def getBuildrootTC(boot): BRcmd="vsim > {} -c < {} -c < {} -c < Date: Tue, 6 Feb 2024 16:11:41 -0600 Subject: [PATCH 8/8] All regression tests run using the main testbench.sv script now. Still need to remove configOptions. --- sim/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/regression-wally b/sim/regression-wally index 757282b7c..ebdac0a1e 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -72,7 +72,7 @@ def getBuildrootTC(boot): BRcmd="vsim > {} -c < {} -c < {} -c <