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Added comments to signals added so the bus is easier to analyze

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slmnemo 2022-06-10 20:30:04 -07:00
parent 31852fdb19
commit d6a1ee1141
1 changed files with 3 additions and 1 deletions
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pipelined/src/lsu/busfsm.sv
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@ -164,6 +164,8 @@ module busfsm #(parameter integer WordCountThreshold,
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
// Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache.
assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead;
assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) |