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Merge branch 'main' of github.com:openhwgroup/cvw

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This commit is contained in:
Jacob Pease 2024-08-24 21:57:44 -05:00
commit d649473ec8
69 changed files with 613 additions and 1418 deletions
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2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit 2a4f56ec97db7cdd6fd13fb928122d408fefbf1e Subproject commit 9d54f3f8e902bb85db74305993d2fc03796b57bc

2
bin/extractFunctionRadix.sh
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@ -3,7 +3,7 @@
###################### ######################
## extractFunctionRadix.sh ## extractFunctionRadix.sh
## ##
## Written: Ross Thompson ## Written: Rose Thompson
## email: ross1728@gmail.com ## email: ross1728@gmail.com
## Created: March 1, 2021 ## Created: March 1, 2021
## Modified: March 10, 2021 ## Modified: March 10, 2021

2
bin/wally-tool-chain-install.sh
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@ -2,7 +2,7 @@
########################################### ###########################################
## Tool chain install script. ## Tool chain install script.
## ##
## Written: Ross Thompson ross1728@gmail.com ## Written: Rose Thompson ross1728@gmail.com
## Created: 18 January 2023 ## Created: 18 January 2023
## Modified: 22 January 2023 ## Modified: 22 January 2023
## Modified: 23 March 2023 ## Modified: 23 March 2023

2
fpga/comport.setup
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@ -1,3 +1,3 @@
sudo chown ross:ross /dev/ttyUSB1 sudo chown rose:rose /dev/ttyUSB1
stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
cat /dev/ttyUSB1 cat /dev/ttyUSB1

173
fpga/constraints/constraints-ArtyA7.xdc
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@ -7,34 +7,34 @@
create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
##### clock ##### ##### clock #####
set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}] set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk]
set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}] set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk]
##### RVVI Ethernet #### ##### RVVI Ethernet ####
# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc # taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc
set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk] set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}] set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}] set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}] set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}] set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv] set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv]
set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er] set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er]
set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk] set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk]
set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}]
set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}]
set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}]
set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}]
set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en] set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en]
set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col] set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col]
set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs] set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs]
set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk] set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk]
set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk] create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk] create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
set_false_path -to [get_ports {phy_ref_clk phy_reset_n}] set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}] set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}]
##### GPI #### ##### GPI ####
set_property PACKAGE_PIN A8 [get_ports {GPI[0]}] set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
@ -87,16 +87,16 @@ set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [ge
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn] set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
set_max_delay -from [get_ports resetn] 20.000 set_max_delay -from [get_ports resetn] 20.000
set_false_path -from [get_ports resetn] set_false_path -from [get_ports resetn]
set_property PACKAGE_PIN C2 [get_ports {resetn}] set_property PACKAGE_PIN C2 [get_ports resetn]
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}] set_property IOSTANDARD LVCMOS33 [get_ports resetn]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset] set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset] set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
set_max_delay -from [get_ports south_reset] 20.000 set_max_delay -from [get_ports south_reset] 20.000
set_false_path -from [get_ports south_reset] set_false_path -from [get_ports south_reset]
set_property PACKAGE_PIN D9 [get_ports {south_reset}] set_property PACKAGE_PIN D9 [get_ports south_reset]
set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}] set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
@ -125,15 +125,27 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
#set_property PULLUP true [get_ports {SDCCD}] #set_property PULLUP true [get_ports {SDCCD}]
# SDCDat[3] # SDCDat[3]
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}] set_property PACKAGE_PIN D4 [get_ports SDCCS]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
set_property PULLTYPE PULLUP [get_ports SDCCS]
# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}] # set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}] # set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
# SDCDat[0] # SDCDat[0]
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}] set_property PACKAGE_PIN F4 [get_ports SDCIn]
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}] set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] set_property PULLTYPE PULLUP [get_ports SDCIn]
set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] set_property PACKAGE_PIN F3 [get_ports SDCCLK]
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}] set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
set_property PULLTYPE PULLUP [get_ports SDCCLK]
set_property PACKAGE_PIN D3 [get_ports SDCCmd]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
set_property PULLTYPE PULLUP [get_ports SDCCmd]
set_property PACKAGE_PIN H2 [get_ports SDCCD]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
set_property PULLTYPE PULLUP [get_ports SDCCD]
set_property PACKAGE_PIN G2 [get_ports SDCWP]
set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
set_property PULLTYPE PULLUP [get_ports SDCWP]
set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
@ -158,54 +170,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc
# ddr3 # ddr3
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]] set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]] set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]] set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
@ -257,3 +269,28 @@ set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]] set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000}
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]

80
fpga/constraints/constraints-vcu108.xdc
View File

@ -3,21 +3,22 @@
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] # create_generated_clock -name CLKDiv64_Gen -source [get_pins #wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] #create_generated_clock -name CLKDiv64_Gen -source [get_pins ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q]
create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
##### GPI #### ##### GPI ####
set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
set_property PACKAGE_PIN M22 [get_ports {GPI[1]}] set_property PACKAGE_PIN M22 [get_ports {GPI[1]}]
set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}] set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}]
set_property PACKAGE_PIN A10 [get_ports {GPI[3]}] #set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}] #set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
set_max_delay -from [get_ports {GPI[*]}] 10.000n set_max_delay -from [get_ports {GPI[*]}] 10.000
##### GPO #### ##### GPO ####
set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
@ -58,7 +59,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_port
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
set_max_delay -from [get_ports reset] 15.000 set_max_delay -from [get_ports reset] 15.000
set_false_path -from [get_ports reset] set_false_path -from [get_ports reset]
set_property PACKAGE_PIN E34 [get_ports {reset}] set_property PACKAGE_PIN A10 [get_ports {reset}]
set_property IOSTANDARD LVCMOS12 [get_ports {reset}] set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
@ -69,15 +70,6 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
##### calib #####
set_property PACKAGE_PIN BA37 [get_ports calib]
set_property IOSTANDARD LVCMOS12 [get_ports calib]
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
##### ahblite_resetn ##### ##### ahblite_resetn #####
set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}] set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}] set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
@ -94,44 +86,34 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
##### SD Card I/O ##### ##### SD Card I/O #####
# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
# set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
# set_property PULLUP true [get_ports {SDCDat[3]}]
# set_property PULLUP true [get_ports {SDCDat[2]}]
# set_property PULLUP true [get_ports {SDCDat[1]}]
# set_property PULLUP true [get_ports {SDCDat[0]}]
# set_property PULLUP true [get_ports {SDCCmd}]
set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}] set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]
set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}] set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}]
set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}]
set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}]
set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}]
set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}] set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}]
set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK] set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK]
set_property PACKAGE_PIN AW12 [get_ports SDCCD]
set_property IOSTANDARD LVCMOS18 [get_ports SDCCD]
set_property PULLTYPE PULLUP [get_ports SDCCD]
set_property PACKAGE_PIN BC16 [get_ports SDCWP]
set_property IOSTANDARD LVCMOS18 [get_ports SDCWP]
set_property PULLTYPE PULLUP [get_ports SDCWP]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] #set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] #set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] #set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] #set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
#set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
#set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
@ -264,8 +246,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] #set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] #set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]

5
fpga/constraints/marked_debug.txt
View File

@ -3,8 +3,5 @@ wally/wallypipelinedcore.sv: logic TrapM
wally/wallypipelinedcore.sv: logic InstrValidM wally/wallypipelinedcore.sv: logic InstrValidM
wally/wallypipelinedcore.sv: logic InstrM wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic PAdrM
lsu/lsu.sv: logic ReadDataM
lsu/lsu.sv: logic WriteDataM
lsu/lsu.sv: logic MemRWM lsu/lsu.sv: logic MemRWM
privileged/csrc.sv: logic HPMCOUNTER_REGW mmu/hptw.sv: logic SATP_REGW

10
fpga/constraints/marked_debug_rvvi.txt Normal file
View File

@ -0,0 +1,10 @@
wally/wallypipelinedcore.sv: logic PCM
wally/wallypipelinedcore.sv: logic TrapM
wally/wallypipelinedcore.sv: logic InstrValidM
wally/wallypipelinedcore.sv: logic InstrM
lsu/lsu.sv: logic IEUAdrM
lsu/lsu.sv: logic PAdrM
lsu/lsu.sv: logic ReadDataM
lsu/lsu.sv: logic WriteDataM
lsu/lsu.sv: logic MemRWM
privileged/csrc.sv: logic HPMCOUNTER_REGW

2
fpga/constraints/vcu-small-debug.xdc
View File

@ -1,6 +1,6 @@
create_debug_core u_ila_0 ila create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]

20
fpga/generator/Makefile
View File

@ -27,19 +27,15 @@ FPGA_VCU: PreProcessFiles IP_VCU
# Generate IP Blocks # Generate IP Blocks
.PHONY: IP_Arty IP_VCU .PHONY: IP_Arty IP_VCU
IP_VCU: $(dst)/xlnx_proc_sys_reset.log \ IP_VCU: $(dst)/sysrst.log \
MEM_VCU \ MEM_VCU \
$(dst)/xlnx_axi_clock_converter.log \ $(dst)/clkconverter.log \
$(dst)/xlnx_ahblite_axi_bridge.log \ $(dst)/ahbaxibridge.log
$(dst)/xlnx_axi_crossbar.log \ IP_Arty: $(dst)/sysrst.log \
$(dst)/xlnx_axi_dwidth_conv_32to64.log \
$(dst)/xlnx_axi_dwidth_conv_64to32.log \
$(dst)/xlnx_axi_prtcl_conv.log
IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
MEM_Arty \ MEM_Arty \
$(dst)/xlnx_mmcm.log \ $(dst)/xlnx_mmcm.log \
$(dst)/xlnx_axi_clock_converter.log \ $(dst)/clkconverter.log \
$(dst)/xlnx_ahblite_axi_bridge.log $(dst)/ahbaxibridge.log
#$(dst)/xlnx_axi_crossbar.log \ #$(dst)/xlnx_axi_crossbar.log \
#$(dst)/xlnx_axi_dwidth_conv_32to64.log \ #$(dst)/xlnx_axi_dwidth_conv_32to64.log \
#$(dst)/xlnx_axi_dwidth_conv_64to32.log \ #$(dst)/xlnx_axi_dwidth_conv_64to32.log \
@ -48,9 +44,9 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
# Generate Memory IP Blocks # Generate Memory IP Blocks
.PHONY: MEM_VCU MEM_Arty .PHONY: MEM_VCU MEM_Arty
MEM_VCU: MEM_VCU:
$(MAKE) $(dst)/xlnx_ddr4-$(board).log $(MAKE) $(dst)/ddr4-$(board).log
MEM_Arty: MEM_Arty:
$(MAKE) $(dst)/xlnx_ddr3-$(board).log $(MAKE) $(dst)/ddr3-$(board).log
# Copy files and make necessary modifications # Copy files and make necessary modifications
.PHONY: PreProcessFiles .PHONY: PreProcessFiles

10
fpga/generator/xlnx_ahblite_axi_bridge.tcl → fpga/generator/ahbaxibridge.tcl
View File

@ -2,15 +2,7 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
# vcu118 board set ipName ahbaxibridge
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_ahblite_axi_bridge
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
if {$boardName!="ArtyA7"} { if {$boardName!="ArtyA7"} {

2
fpga/generator/xlnx_axi_clock_converter.tcl → fpga/generator/clkconverter.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e #set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4 #set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_axi_clock_converter set ipName clkconverter
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
if {$boardName!="ArtyA7"} { if {$boardName!="ArtyA7"} {

2
fpga/generator/xlnx_ddr3-ArtyA7.tcl → fpga/generator/ddr3-ArtyA7.tcl
View File

@ -2,7 +2,7 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
set ipName xlnx_ddr3 set ipName ddr3
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]

18
fpga/generator/xlnx_ddr4-vcu108.tcl → fpga/generator/ddr4-vcu108.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e #set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4 #set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_ddr4 set ipName ddr4
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]
@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.No_Controller {1} \ CONFIG.No_Controller {1} \
CONFIG.Phy_Only {Complete_Memory_Controller} \ CONFIG.Phy_Only {Complete_Memory_Controller} \
CONFIG.C0.DDR4_PhyClockRatio {4:1} \ CONFIG.C0.DDR4_PhyClockRatio {4:1} \
CONFIG.C0.DDR4_TimePeriod {1200} \ CONFIG.C0.DDR4_TimePeriod {833} \
CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \ CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
CONFIG.C0.DDR4_BurstLength {8} \ CONFIG.C0.DDR4_BurstLength {8} \
CONFIG.C0.DDR4_BurstType {Sequential} \ CONFIG.C0.DDR4_BurstType {Sequential} \
CONFIG.C0.DDR4_CasLatency {13} \ CONFIG.C0.DDR4_CasLatency {16} \
CONFIG.C0.DDR4_CasWriteLatency {10} \ CONFIG.C0.DDR4_CasWriteLatency {12} \
CONFIG.C0.DDR4_Slot {Single} \ CONFIG.C0.DDR4_Slot {Single} \
CONFIG.C0.DDR4_MemoryVoltage {1.2V} \ CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
CONFIG.C0.DDR4_DataWidth {64} \ CONFIG.C0.DDR4_DataWidth {64} \
@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiIDWidth {4} \ CONFIG.C0.DDR4_AxiIDWidth {4} \
CONFIG.C0.DDR4_AxiAddressWidth {31} \ CONFIG.C0.DDR4_AxiAddressWidth {31} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
CONFIG.Reference_Clock {Differential} \ CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \ CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \ CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
@ -106,7 +103,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_CustomParts {no_file_loaded} \ CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
CONFIG.C0.DDR4_EN_PARITY {false} \ CONFIG.C0.DDR4_EN_PARITY {false} \
CONFIG.C0.DDR4_Enable_LVAUX {false} \ CONFIG.C0.DDR4_Enable_LVAUX {false} \
CONFIG.C0.DDR4_InputClockPeriod {3359} \ CONFIG.C0.DDR4_InputClockPeriod {3332} \
CONFIG.C0.DDR4_LR_SKEW_0 {0} \ CONFIG.C0.DDR4_LR_SKEW_0 {0} \
CONFIG.C0.DDR4_LR_SKEW_1 {0} \ CONFIG.C0.DDR4_LR_SKEW_1 {0} \
CONFIG.C0.DDR4_MemoryName {MainMemory} \ CONFIG.C0.DDR4_MemoryName {MainMemory} \
@ -115,6 +112,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_ODT_SKEW_2 {0} \ CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
CONFIG.C0.DDR4_ODT_SKEW_3 {0} \ CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \ CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
CONFIG.C0.DDR4_PAR_SKEW {0} \ CONFIG.C0.DDR4_PAR_SKEW {0} \
CONFIG.C0.DDR4_Specify_MandD {false} \ CONFIG.C0.DDR4_Specify_MandD {false} \
CONFIG.C0.DDR4_TREFI {0} \ CONFIG.C0.DDR4_TREFI {0} \

2
fpga/generator/xlnx_ddr4-vcu118.tcl → fpga/generator/ddr4-vcu118.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e #set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4 #set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_ddr4 set ipName ddr4
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]

4
fpga/generator/xlnx_mmcm.tcl → fpga/generator/mmcm.tcl
View File

@ -1,7 +1,7 @@
set partNumber $::env(XILINX_PART) set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD) set boardName $::env(XILINX_BOARD)
set ipName xlnx_mmcm set ipName mmcm
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]
@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
CONFIG.CLKIN1_JITTER_PS {10.0} \ CONFIG.CLKIN1_JITTER_PS {10.0} \
] [get_ips $ipName] ] [get_ips $ipName]

2
fpga/generator/xlnx_proc_sys_reset.tcl → fpga/generator/sysrst.tcl
View File

@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD)
#set partNumber xcvu9p-flga2104-2L-e #set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4 #set boardName xilinx.com:vcu118:part0:2.4
set ipName xlnx_proc_sys_reset set ipName sysrst
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
if {$boardName!="ArtyA7"} { if {$boardName!="ArtyA7"} {

42
fpga/generator/wally.tcl
View File

@ -5,6 +5,11 @@ set boardName $::env(XILINX_BOARD)
set boardSubName [lindex [split ${boardName} :] 1] set boardSubName [lindex [split ${boardName} :] 1]
set board $::env(board) set board $::env(board)
#set partNumber xc7a100tcsg324-1
#set boardName digilentinc.com:arty-a7-100:part0:1.1
#set boardSubName arty-a7-100
#set board ArtyA7
set ipName WallyFPGA set ipName WallyFPGA
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
@ -23,20 +28,15 @@ if {$board=="ArtyA7"} {
} }
# read in ip # read in ip
read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
# Added crossbar - Jacob Pease <2023-01-12 Thu>
#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci
#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci
#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci
#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
} else { } else {
read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
} }
# read in all other rtl # read in all other rtl
@ -46,13 +46,6 @@ read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
} else {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
}
# define top level # define top level
set_property top fpgaTop [current_fileset] set_property top fpgaTop [current_fileset]
@ -62,6 +55,14 @@ update_compile_order -fileset sources_1
exec mkdir -p reports/ exec mkdir -p reports/
exec rm -rf reports/* exec rm -rf reports/*
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
} else {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
}
report_compile_order -constraints > reports/compile_order.rpt report_compile_order -constraints > reports/compile_order.rpt
# this is elaboration not synthesis. # this is elaboration not synthesis.
@ -89,10 +90,11 @@ report_clock_interaction -file re
write_verilog -force -mode funcsim sim/syn-funcsim.v write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
source ../constraints/small-debug.xdc #source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc #source ../constraints/small-debug-rvvi.xdc
} else { } else {
source ../constraints/vcu-small-debug.xdc #source ../constraints/vcu-small-debug.xdc
source ../constraints/small-debug.xdc
} }

32
fpga/generator/xlnx_axi_crossbar.tcl
View File

@ -1,32 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_crossbar
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.NUM_SI {2} \
CONFIG.DATA_WIDTH {64} \
CONFIG.ID_WIDTH {4} \
CONFIG.M01_S01_READ_CONNECTIVITY {0} \
CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \
CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \
CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \
CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

25
fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl
View File

@ -1,25 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_dwidth_conv_32to64
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

27
fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl
View File

@ -1,27 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_dwidth_conv_64to32
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \
CONFIG.SI_DATA_WIDTH {64} \
CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

25
fpga/generator/xlnx_axi_dwidth_converter.tcl
View File

@ -1,25 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_dwidth_converter
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

23
fpga/generator/xlnx_axi_prtcl_conv.tcl
View File

@ -1,23 +0,0 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
# vcu118 board
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_axi_prtcl_conv
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1

2
fpga/generator/xlnx_ddr4.tcl
View File

@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e
set boardName xilinx.com:vcu108:part0:1.2 set boardName xilinx.com:vcu108:part0:1.2
set ipName xlnx_ddr4 set ipName ddr4
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project] set_property board_part $boardName [current_project]

1018
fpga/src/fpgaTop.sv
View File

File diff suppressed because it is too large Load Diff

314
fpga/src/fpgaTopArtyA7.sv
View File

@ -29,183 +29,183 @@
import cvw::*; import cvw::*;
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
(input default_100mhz_clk, (input logic default_100mhz_clk,
(* mark_debug = "true" *) input resetn, input logic resetn,
input south_reset, input logic south_reset,
// GPIO signals // GPIO signals
input [3:0] GPI, input logic [3:0] GPI,
output [4:0] GPO, output logic [4:0] GPO,
// UART Signals // UART Signals
input UARTSin, input logic UARTSin,
output UARTSout, output logic UARTSout,
// SDC Signals connecting to an SPI peripheral // SDC Signals connecting to an SPI peripheral
input SDCIn, input logic SDCIn,
output SDCCLK, output logic SDCCLK,
output SDCCmd, output logic SDCCmd,
output SDCCS, output logic SDCCS,
input SDCCD, input logic SDCCD,
input SDCWP, input logic SDCWP,
/* /*
* Ethernet: 100BASE-T MII * Ethernet: 100BASE-T MII
*/ */
output phy_ref_clk, output logic phy_ref_clk,
input phy_rx_clk, input logic phy_rx_clk,
input [3:0] phy_rxd, input logic [3:0] phy_rxd,
input phy_rx_dv, input logic phy_rx_dv,
input phy_rx_er, input logic phy_rx_er,
input phy_tx_clk, input logic phy_tx_clk,
output [3:0] phy_txd, output logic [3:0] phy_txd,
output phy_tx_en, output logic phy_tx_en,
input phy_col, // nc input logic phy_col, // nc
input phy_crs, // nc input logic phy_crs, // nc
output phy_reset_n, output logic phy_reset_n,
inout [15:0] ddr3_dq, inout logic [15:0] ddr3_dq,
inout [1:0] ddr3_dqs_n, inout logic [1:0] ddr3_dqs_n,
inout [1:0] ddr3_dqs_p, inout logic [1:0] ddr3_dqs_p,
output [13:0] ddr3_addr, output logic [13:0] ddr3_addr,
output [2:0] ddr3_ba, output logic [2:0] ddr3_ba,
output ddr3_ras_n, output logic ddr3_ras_n,
output ddr3_cas_n, output logic ddr3_cas_n,
output ddr3_we_n, output logic ddr3_we_n,
output ddr3_reset_n, output logic ddr3_reset_n,
output [0:0] ddr3_ck_p, output logic [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n, output logic [0:0] ddr3_ck_n,
output [0:0] ddr3_cke, output logic [0:0] ddr3_cke,
output [0:0] ddr3_cs_n, output logic [0:0] ddr3_cs_n,
output [1:0] ddr3_dm, output logic [1:0] ddr3_dm,
output [0:0] ddr3_odt output logic [0:0] ddr3_odt
); );
// MMCM Signals // MMCM Signals
wire CPUCLK; logic CPUCLK;
wire c0_ddr4_ui_clk_sync_rst; logic c0_ddr4_ui_clk_sync_rst;
wire bus_struct_reset; logic bus_struct_reset;
wire peripheral_reset; logic peripheral_reset;
wire interconnect_aresetn; logic interconnect_aresetn;
wire peripheral_aresetn; logic peripheral_aresetn;
wire mb_reset; logic mb_reset;
// AHB Signals from Wally // AHB Signals from Wally
wire HCLKOpen; logic HCLKOpen;
wire HRESETnOpen; logic HRESETnOpen;
wire [63:0] HRDATAEXT; logic [63:0] HRDATAEXT;
wire HREADYEXT; logic HREADYEXT;
wire HRESPEXT; logic HRESPEXT;
wire HSELEXT; logic HSELEXT;
wire [55:0] HADDR; logic [55:0] HADDR;
wire [63:0] HWDATA; logic [63:0] HWDATA;
wire [64/8-1:0] HWSTRB; logic [64/8-1:0] HWSTRB;
wire HWRITE; logic HWRITE;
wire [2:0] HSIZE; logic [2:0] HSIZE;
wire [2:0] HBURST; logic [2:0] HBURST;
wire [1:0] HTRANS; logic [1:0] HTRANS;
wire HREADY; logic HREADY;
wire [3:0] HPROT; logic [3:0] HPROT;
wire HMASTLOCK; logic HMASTLOCK;
// GPIO Signals // GPIO Signals
wire [31:0] GPIOIN, GPIOOUT, GPIOEN; logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
// AHB to AXI Bridge Signals // AHB to AXI Bridge Signals
wire [3:0] m_axi_awid; logic [3:0] m_axi_awid;
wire [7:0] m_axi_awlen; logic [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize; logic [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst; logic [1:0] m_axi_awburst;
wire [3:0] m_axi_awcache; logic [3:0] m_axi_awcache;
wire [31:0] m_axi_awaddr; logic [31:0] m_axi_awaddr;
wire [2:0] m_axi_awprot; logic [2:0] m_axi_awprot;
wire m_axi_awvalid; logic m_axi_awvalid;
wire m_axi_awready; logic m_axi_awready;
wire m_axi_awlock; logic m_axi_awlock;
wire [63:0] m_axi_wdata; logic [63:0] m_axi_wdata;
wire [7:0] m_axi_wstrb; logic [7:0] m_axi_wstrb;
wire m_axi_wlast; logic m_axi_wlast;
wire m_axi_wvalid; logic m_axi_wvalid;
wire m_axi_wready; logic m_axi_wready;
wire [3:0] m_axi_bid; logic [3:0] m_axi_bid;
wire [1:0] m_axi_bresp; logic [1:0] m_axi_bresp;
wire m_axi_bvalid; logic m_axi_bvalid;
wire m_axi_bready; logic m_axi_bready;
wire [3:0] m_axi_arid; logic [3:0] m_axi_arid;
wire [7:0] m_axi_arlen; logic [7:0] m_axi_arlen;
wire [2:0] m_axi_arsize; logic [2:0] m_axi_arsize;
wire [1:0] m_axi_arburst; logic [1:0] m_axi_arburst;
wire [2:0] m_axi_arprot; logic [2:0] m_axi_arprot;
wire [3:0] m_axi_arcache; logic [3:0] m_axi_arcache;
wire m_axi_arvalid; logic m_axi_arvalid;
wire [31:0] m_axi_araddr; logic [31:0] m_axi_araddr;
wire m_axi_arlock; logic m_axi_arlock;
wire m_axi_arready; logic m_axi_arready;
wire [3:0] m_axi_rid; logic [3:0] m_axi_rid;
wire [63:0] m_axi_rdata; logic [63:0] m_axi_rdata;
wire [1:0] m_axi_rresp; logic [1:0] m_axi_rresp;
wire m_axi_rvalid; logic m_axi_rvalid;
wire m_axi_rlast; logic m_axi_rlast;
wire m_axi_rready; logic m_axi_rready;
// AXI Signals going out of Clock Converter // AXI Signals going out of Clock Converter
wire [3:0] BUS_axi_arregion; logic [3:0] BUS_axi_arregion;
wire [3:0] BUS_axi_arqos; logic [3:0] BUS_axi_arqos;
wire [3:0] BUS_axi_awregion; logic [3:0] BUS_axi_awregion;
wire [3:0] BUS_axi_awqos; logic [3:0] BUS_axi_awqos;
wire [3:0] BUS_axi_awid; logic [3:0] BUS_axi_awid;
wire [7:0] BUS_axi_awlen; logic [7:0] BUS_axi_awlen;
wire [2:0] BUS_axi_awsize; logic [2:0] BUS_axi_awsize;
wire [1:0] BUS_axi_awburst; logic [1:0] BUS_axi_awburst;
wire [3:0] BUS_axi_awcache; logic [3:0] BUS_axi_awcache;
wire [31:0] BUS_axi_awaddr; logic [31:0] BUS_axi_awaddr;
wire [2:0] BUS_axi_awprot; logic [2:0] BUS_axi_awprot;
wire BUS_axi_awvalid; logic BUS_axi_awvalid;
wire BUS_axi_awready; logic BUS_axi_awready;
wire BUS_axi_awlock; logic BUS_axi_awlock;
wire [63:0] BUS_axi_wdata; logic [63:0] BUS_axi_wdata;
wire [7:0] BUS_axi_wstrb; logic [7:0] BUS_axi_wstrb;
wire BUS_axi_wlast; logic BUS_axi_wlast;
wire BUS_axi_wvalid; logic BUS_axi_wvalid;
wire BUS_axi_wready; logic BUS_axi_wready;
wire [3:0] BUS_axi_bid; logic [3:0] BUS_axi_bid;
wire [1:0] BUS_axi_bresp; logic [1:0] BUS_axi_bresp;
wire BUS_axi_bvalid; logic BUS_axi_bvalid;
wire BUS_axi_bready; logic BUS_axi_bready;
wire [3:0] BUS_axi_arid; logic [3:0] BUS_axi_arid;
wire [7:0] BUS_axi_arlen; logic [7:0] BUS_axi_arlen;
wire [2:0] BUS_axi_arsize; logic [2:0] BUS_axi_arsize;
wire [1:0] BUS_axi_arburst; logic [1:0] BUS_axi_arburst;
wire [2:0] BUS_axi_arprot; logic [2:0] BUS_axi_arprot;
wire [3:0] BUS_axi_arcache; logic [3:0] BUS_axi_arcache;
wire BUS_axi_arvalid; logic BUS_axi_arvalid;
wire [31:0] BUS_axi_araddr; logic [31:0] BUS_axi_araddr;
wire BUS_axi_arlock; logic BUS_axi_arlock;
wire BUS_axi_arready; logic BUS_axi_arready;
wire [3:0] BUS_axi_rid; logic [3:0] BUS_axi_rid;
wire [63:0] BUS_axi_rdata; logic [63:0] BUS_axi_rdata;
wire [1:0] BUS_axi_rresp; logic [1:0] BUS_axi_rresp;
wire BUS_axi_rvalid; logic BUS_axi_rvalid;
wire BUS_axi_rlast; logic BUS_axi_rlast;
wire BUS_axi_rready; logic BUS_axi_rready;
wire BUSCLK; logic BUSCLK;
wire sdio_reset_open; logic sdio_reset_open;
wire c0_init_calib_complete; logic c0_init_calib_complete;
wire dbg_clk; logic dbg_clk;
wire [511 : 0] dbg_bus; logic [511 : 0] dbg_bus;
wire ui_clk_sync_rst; logic ui_clk_sync_rst;
wire CLK208; logic CLK208;
wire clk167; logic clk167;
wire clk200; logic clk200;
wire app_sr_active; logic app_sr_active;
wire app_ref_ack; logic app_ref_ack;
wire app_zq_ack; logic app_zq_ack;
wire mmcm_locked; logic mmcm_locked;
wire [11:0] device_temp; logic [11:0] device_temp;
wire mmcm1_locked; logic mmcm1_locked;
(* mark_debug = "true" *) logic RVVIStall; (* mark_debug = "true" *) logic RVVIStall;
@ -225,7 +225,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
// 2. a second clock which is 200 MHz // 2. a second clock which is 200 MHz
// Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz. // Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz.
// the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot. // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
xlnx_mmcm xln_mmcm(.clk_out1(clk167), mmcm mmcm(.clk_out1(clk167),
.clk_out2(clk200), .clk_out2(clk200),
.clk_out3(CPUCLK), .clk_out3(CPUCLK),
.clk_out4(phy_ref_clk), .clk_out4(phy_ref_clk),
@ -236,7 +236,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
// reset controller XILINX IP // reset controller XILINX IP
xlnx_proc_sys_reset xlnx_proc_sys_reset_0 sysrst sysrst
(.slowest_sync_clk(CPUCLK), (.slowest_sync_clk(CPUCLK),
.ext_reset_in(1'b0), .ext_reset_in(1'b0),
.aux_reset_in(south_reset), .aux_reset_in(south_reset),
@ -262,7 +262,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
// ahb lite to axi bridge // ahb lite to axi bridge
xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 ahbaxibridge ahbaxibridge
(.s_ahb_hclk(CPUCLK), (.s_ahb_hclk(CPUCLK),
.s_ahb_hresetn(peripheral_aresetn), .s_ahb_hresetn(peripheral_aresetn),
.s_ahb_hsel(HSELEXT), .s_ahb_hsel(HSELEXT),
@ -314,7 +314,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
.m_axi_rready(m_axi_rready)); .m_axi_rready(m_axi_rready));
// AXI Clock Converter // AXI Clock Converter
xlnx_axi_clock_converter xlnx_axi_clock_converter_0 clkconverter clkconverter
(.s_axi_aclk(CPUCLK), (.s_axi_aclk(CPUCLK),
.s_axi_aresetn(peripheral_aresetn), .s_axi_aresetn(peripheral_aresetn),
.s_axi_awid(m_axi_awid), .s_axi_awid(m_axi_awid),
@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
.m_axi_rready(BUS_axi_rready)); .m_axi_rready(BUS_axi_rready));
// DDR3 Controller // DDR3 Controller
xlnx_ddr3 xlnx_ddr3_c0 ddr3 ddr3
( (
// ddr3 I/O // ddr3 I/O
.ddr3_dq(ddr3_dq), .ddr3_dq(ddr3_dq),

2
fpga/src/wallypipelinedsocwrapper.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// wallypipelinedsocwrapper.sv // wallypipelinedsocwrapper.sv
// //
// Written: Ross Thompson ross1728@gmail.com 16 June 2023 // Written: Rose Thompson ross1728@gmail.com 16 June 2023
// Modified: // Modified:
// //
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, // Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,

2
fpga/zsbl/boot.c
View File

@ -214,7 +214,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) {
int ret = 0; int ret = 0;
// Initialize UART for messages // Initialize UART for messages
init_uart(20000000, 115200); init_uart(SYSTEMCLOCK, 115200);
// Print the wally banner // Print the wally banner
print_uart(BANNER); print_uart(BANNER);

8
linux/devicetree/wally-artya7.dts
View File

@ -21,8 +21,8 @@
cpus { cpus {
#address-cells = <0x01>; #address-cells = <0x01>;
#size-cells = <0x00>; #size-cells = <0x00>;
clock-frequency = <0x1312D00>; clock-frequency = <0x17D7840>;
timebase-frequency = <0x1312D00>; timebase-frequency = <0x17D7840>;
cpu@0 { cpu@0 {
phandle = <0x01>; phandle = <0x01>;
@ -54,7 +54,7 @@
refclk: refclk { refclk: refclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <0x1312D00>; clock-frequency = <0x17D7840>;
clock-output-names = "xtal"; clock-output-names = "xtal";
}; };
@ -73,7 +73,7 @@
uart@10000000 { uart@10000000 {
interrupts = <0x0a>; interrupts = <0x0a>;
interrupt-parent = <0x03>; interrupt-parent = <0x03>;
clock-frequency = <0x1312D00>; clock-frequency = <0x17D7840>;
reg = <0x00 0x10000000 0x00 0x100>; reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a"; compatible = "ns16550a";
}; };

58
linux/devicetree/wally-vcu108.dts
View File

@ -9,7 +9,7 @@
chosen { chosen {
linux,initrd-end = <0x85c43a00>; linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>; linux,initrd-start = <0x84200000>;
bootargs = "console=ttyS0,115200 root=/dev/vda ro"; bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7";
stdout-path = "/soc/uart@10000000"; stdout-path = "/soc/uart@10000000";
}; };
@ -21,8 +21,8 @@
cpus { cpus {
#address-cells = <0x01>; #address-cells = <0x01>;
#size-cells = <0x00>; #size-cells = <0x00>;
clock-frequency = <0x14FB180>; clock-frequency = <0x2FAF080>;
timebase-frequency = <0x14FB180>; timebase-frequency = <0x2FAF080>;
cpu@0 { cpu@0 {
phandle = <0x01>; phandle = <0x01>;
@ -31,6 +31,9 @@
status = "okay"; status = "okay";
compatible = "riscv"; compatible = "riscv";
riscv,isa = "rv64imafdcsu"; riscv,isa = "rv64imafdcsu";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
riscv,cbom-block-size = <64>;
mmu-type = "riscv,sv48"; mmu-type = "riscv,sv48";
interrupt-controller { interrupt-controller {
@ -48,10 +51,29 @@
compatible = "simple-bus"; compatible = "simple-bus";
ranges; ranges;
refclk: refclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0x2FAF080>;
clock-output-names = "xtal";
};
gpio0: gpio@10060000 {
compatible = "sifive,gpio0";
interrupt-parent = <0x03>;
interrupts = <3>;
reg = <0x00 0x10060000 0x00 0x1000>;
reg-names = "control";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart@10000000 { uart@10000000 {
interrupts = <0x0a>; interrupts = <0x0a>;
interrupt-parent = <0x03>; interrupt-parent = <0x03>;
clock-frequency = <0x14FB180>; clock-frequency = <0x2FAF080>;
reg = <0x00 0x10000000 0x00 0x100>; reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a"; compatible = "ns16550a";
}; };
@ -67,18 +89,24 @@
#address-cells = <0x00>; #address-cells = <0x00>;
}; };
mmc@13000 { spi@13000 {
interrupts = <0x14>; compatible = "sifive,spi0";
compatible = "riscv,axi-sd-card-1.0";
reg = <0x00 0x13000 0x00 0x7F>;
fifo-depth = <256>;
bus-width = <4>;
interrupt-parent = <0x03>; interrupt-parent = <0x03>;
clock = <0x14FB180>; interrupts = <0x14>;
max-frequency = <0xA7D8C0>; reg = <0x0 0x13000 0x0 0x1000>;
cap-sd-highspeed; reg-names = "control";
cap-mmc-highspeed; clocks = <&refclk>;
no-sdio;
#address-cells = <1>;
#size-cells = <0>;
mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
spi-max-frequency = <5000000>;
voltage-ranges = <3300 3300>;
disable-wp;
// gpios = <&gpio0 6 1>;
};
}; };
clint@2000000 { clint@2000000 {

2
linux/testvector-generation/parseGDBtoTrace.py
View File

@ -1,7 +1,7 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
import sys, fileinput, re import sys, fileinput, re
# Ross Thompson # Rose Thompson
# July 27, 2021 # July 27, 2021
# Rewrite of the linux trace parser. # Rewrite of the linux trace parser.

12
sim/Makefile
View File

@ -30,14 +30,22 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
# vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt # vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt
vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb
QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb
vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log
vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcov/fcov.summary.log vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcov/fcov.summary.log
grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcov/fcov.log grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcov/fcov.log
QuestaFunctCoverageRvvi: ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb
vcover merge -out ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_arch64i.ucdb ${WALLY}/addins/cvw-arch-verif/work/rv64gc_*.ucdb -logfile ${SIM}/questa/fcovrvvi/log
vcover report -details -html ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.log
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -testdetails -cvg > ${SIM}/questa/fcovrvvi/fcovrvvi.testdetails.log
vcover report ${SIM}/questa/fcovrvvi_ucdb/fcovrvvi.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcovrvvi/fcovrvvi.summary.log
grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcovrvvi/fcovrvvi.log
imperasdv_cov: imperasdv_cov:
touch ${SIM}/seed0.txt touch ${SIM}/seed0.txt
echo "0" > ${SIM}/seed0.txt echo "0" > ${SIM}/seed0.txt

2
sim/questa/wally.do
View File

@ -211,7 +211,7 @@ set temp3 [lindex $PlusArgs 3]
# "Extra checking for conflicts with always_comb done at vopt time" # "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt # because vsim will run vopt
vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${FCdefineRVVI_COVERAGE} ${idvFiles} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv +incdir+${FCRVVI}/common +incdir+${FCRVVI} ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 vlog -lint +nowarnRDGN -suppress 2244 -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${FCdefineRVVI_COVERAGE} ${idvFiles} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv +incdir+${FCRVVI}/common +incdir+${FCRVVI} ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals

20
sim/questa/wave.do
View File

@ -204,7 +204,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
@ -657,22 +657,6 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/clk
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/rvvi
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/valid
add wave -noupdate -group packetizer -color Gold /testbench/rvvi_synth/packetizer/CurrState
add wave -noupdate -group packetizer -radix unsigned /testbench/rvvi_synth/packetizer/WordCount
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/RVVIStall
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/rvviDelay
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWdata
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWlast
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWstrb
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWvalid
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWready
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_clk
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_txd
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_en
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_er
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0} WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0}
quietly wave cursor active 4 quietly wave cursor active 4
@ -690,4 +674,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ns} {1033211 ns} WaveRestoreZoom {0 ns} {755549 ns}

2
src/cache/cache.sv vendored
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// cache.sv // cache.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 7 July 2021 // Created: 7 July 2021
// Modified: 20 January 2023 // Modified: 20 January 2023
// //

2
src/cache/cachefsm.sv vendored
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// cachefsm.sv // cachefsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 25 August 2021 // Created: 25 August 2021
// Modified: 20 January 2023 // Modified: 20 January 2023
// //

2
src/cache/subcachelineread.sv vendored
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// subcachelineread.sv // subcachelineread.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 4 February 2022 // Created: 4 February 2022
// Modified: 20 January 2023 // Modified: 20 January 2023
// //

2
src/ebu/ahbcacheinterface.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ahbcacheinterface.sv // ahbcacheinterface.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022 // Created: August 29, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/ahbinterface.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ahbinterface.sv // ahbinterface.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022 // Created: August 29, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/buscachefsm.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// busfsm.sv // busfsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021 // Created: December 29, 2021
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/busfsm.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// busfsm.sv // busfsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021 // Created: December 29, 2021
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/controllerinput.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// controllerinput.sv // controllerinput.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 31, 2022 // Created: August 31, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/ebu.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// abhmulticontroller // abhmulticontroller
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022 // Created: August 29, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/ebufsmarb.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ebufsmarb.sv // ebufsmarb.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 23 January 2023 // Created: 23 January 2023
// Modified: 23 January 2023 // Modified: 23 January 2023
// //

2
src/generic/arrs.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// arrs.sv // arrs.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Modified: November 12, 2021 // Modified: November 12, 2021
// //
// Purpose: resets are typically asynchronous but need to be synchronized to // Purpose: resets are typically asynchronous but need to be synchronized to

2
src/ifu/bpred/RASPredictor.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// RASPredictor.sv // RASPredictor.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Rose Thomposn ross1728@gmail.com
// Created: 15 February 2021 // Created: 15 February 2021
// Modified: 25 January 2023 // Modified: 25 January 2023
// //

2
src/ifu/bpred/bpred.sv
View File

@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// bpred.sv // bpred.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Rose Thomposn ross1728@gmail.com
// Created: 12 February 2021 // Created: 12 February 2021
// Modified: 19 January 2023 // Modified: 19 January 2023
// //

2
src/ifu/bpred/btb.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// btb.sv // btb.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: February 15, 2021 // Created: February 15, 2021
// Modified: 24 January 2023 // Modified: 24 January 2023
// //

2
src/ifu/bpred/gshare.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// gshare.sv // gshare.sv
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) // Adapted from ssanghai@hmc.edu (Shreya Sanghai)

2
src/ifu/bpred/gsharebasic.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// gsharebasic.sv // gsharebasic.sv
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation. // Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.

2
src/ifu/bpred/icpred.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// icpred.sv // icpred.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Rose Thomposn ross1728@gmail.com
// Created: February 26, 2023 // Created: February 26, 2023
// Modified: February 26, 2023 // Modified: February 26, 2023
// //

2
src/ifu/bpred/localaheadbp.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// localaheadbp // localaheadbp
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// //

2
src/ifu/bpred/localbpbasic.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// localbpbasic // localbpbasic
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// //

2
src/ifu/bpred/localrepairbp.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// localrepairbp // localrepairbp
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 15 April 2023 // Created: 15 April 2023
// //

2
src/ifu/bpred/satCounter2.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// satCounter2.sv // satCounter2.sv
// //
// Written: Ross Thomposn // Written: Rose Thomposn
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: February 13, 2021 // Created: February 13, 2021
// Modified: // Modified:

2
src/ifu/bpred/twoBitPredictor.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// twoBitPredictor.sv // twoBitPredictor.sv
// //
// Written: Ross Thomposn // Written: Rose Thomposn
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: February 14, 2021 // Created: February 14, 2021
// Modified: // Modified:

2
src/ifu/irom.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// irom.sv // irom.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022 // Created: 30 January 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ifu/spill.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// spill.sv // spill.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 28 January 2022 // Created: 28 January 2022
// Modified: 19 January 2023 // Modified: 19 January 2023
// //

2
src/lsu/atomic.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// atomic.sv // atomic.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 31 January 2022 // Created: 31 January 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/lsu/dtim.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// dtim.sv // dtim.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022 // Created: 30 January 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
testbench/common/DCacheFlushFSM.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// DCacheFlushFSM.sv // DCacheFlushFSM.sv
// //
// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com // Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023 // Modified: 14 June 2023
// //
// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty // Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty

2
testbench/common/functionName.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// functionName.sv // functionName.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// //
// Purpose: decode name of function // Purpose: decode name of function
// //

6
testbench/common/loggers.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// loggers.sv // loggers.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023 // Modified: 14 June 2023
// //
// Purpose: Log branch instructions, log instruction fetches, // Purpose: Log branch instructions, log instruction fetches,
@ -246,8 +246,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
flop #(1) ResetDReg(clk, reset, resetD); flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD; assign resetEdge = ~reset & resetD;
initial begin initial begin
LogFile = "branch.log"; // will break some of Ross's research analysis scripts LogFile = "branch.log"; // will break some of Rose's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts CFILogFile = "cfi.log"; // will break some of Rose's research analysis scripts
//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE); //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
file = $fopen(LogFile, "w"); file = $fopen(LogFile, "w");
CFIfile = $fopen(CFILogFile, "w"); CFIfile = $fopen(CFILogFile, "w");

2
testbench/common/watchdog.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// watchdog.sv // watchdog.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023 // Modified: 14 June 2023
// //
// Purpose: Detects if the processor is stuck and halts the simulation // Purpose: Detects if the processor is stuck and halts the simulation

2
testbench/sdc/sdModel.sv
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@ -917,7 +917,7 @@ module sdModel
WRITE_DATA: begin WRITE_DATA: begin
oeDat<=1; oeDat<=1;
outdly_cnt<=outdly_cnt+1; outdly_cnt<=outdly_cnt+1;
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Ross) datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Rose)
if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed

2
tests/custom/fpga-test-sdc/copyFlash.c
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// copyFlash.sv // copyFlash.sv
// //
// Written: Ross Thompson September 25, 2021 // Written: Rose Thompson September 25, 2021
// Modified: // Modified:
// //
// Purpose: copies flash card into memory // Purpose: copies flash card into memory

2
tests/custom/fpga-test-sdc/sdcDriver.c
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// SDC.sv // SDC.sv
// //
// Written: Ross Thompson September 25, 2021 // Written: Rose Thompson September 25, 2021
// Modified: // Modified:
// //
// Purpose: driver for sdc reader. // Purpose: driver for sdc reader.

2
tests/custom/simple/fail.s
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@ -1,4 +1,4 @@
# Ross Thompson # Rose Thompson
# March 17, 2021 # March 17, 2021
# Oklahoma State University # Oklahoma State University

7
tests/riscof/Makefile
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@ -4,8 +4,6 @@ work_dir = ./riscof_work
work = ./work work = ./work
arch_workdir = $(work)/riscv-arch-test arch_workdir = $(work)/riscv-arch-test
wally_workdir = $(work)/wally-riscv-arch-test wally_workdir = $(work)/wally-riscv-arch-test
custom_test_dir = ../../addins/cvw-arch-verif/test
submodule_work_dir = ../../addins/cvw-arch-verif/riscof_work
nproc = $(shell nproc --ignore=1) nproc = $(shell nproc --ignore=1)
current_dir = $(shell pwd) current_dir = $(shell pwd)
@ -15,8 +13,6 @@ all: root arch32 wally32 arch32e arch64 wally64
wally-riscv-arch-test: root wally64 wally32 wally-riscv-arch-test: root wally64 wally32
custom: new_test
root: root:
mkdir -p $(work_dir) mkdir -p $(work_dir)
mkdir -p $(work) mkdir -p $(work)
@ -54,9 +50,6 @@ wally64:
quad64: quad64:
riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/ --env=$(wally_dir)/riscv-test-suite/env riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/ --env=$(wally_dir)/riscv-test-suite/env
new_test:
riscof run --work-dir=$(submodule_work_dir) --config=config64.ini --suite=$(custom_test_dir)/ --env=$(wally_dir)/riscv-test-suite/env --no-browser
#wally32e: #wally32e:
# riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run # riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
# rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed" # rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"