From ab689334669ff44f222c544392f77d610bc4e2c0 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Mon, 3 May 2021 17:54:57 -0400 Subject: [PATCH 01/20] Fix bug that caused stvec to get the wrong value --- wally-pipelined/src/privileged/csrm.sv | 2 +- wally-pipelined/src/privileged/csrn.sv | 3 ++- wally-pipelined/src/privileged/csrs.sv | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 4cfc533d0..6d0cde8df 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -146,7 +146,7 @@ module csrm #(parameter assign IllegalCSRMWriteReadonlyM = CSRMWriteM && (CSRAdrM == MVENDORID || CSRAdrM == MARCHID || CSRAdrM == MIMPID || CSRAdrM == MHARTID); // CSRs - flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0 + flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0 generate if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, ZERO, MEDELEG_REGW); diff --git a/wally-pipelined/src/privileged/csrn.sv b/wally-pipelined/src/privileged/csrn.sv index 2aa44bdfe..e82ff59f3 100644 --- a/wally-pipelined/src/privileged/csrn.sv +++ b/wally-pipelined/src/privileged/csrn.sv @@ -3,6 +3,7 @@ // // Written: David_Harris@hmc.edu 9 January 2021 // Modified: +// dottolia@hmc.edu 3 May 2021 - fix bug with utvec getting wrong value // // Purpose: User-Mode Control and Status Registers for User Mode Exceptions // See RISC-V Privileged Mode Specification 20190608 Table 2.2 @@ -64,7 +65,7 @@ module csrn #(parameter assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL)) && ~StallW; // CSRs - flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, `RESET_VECTOR, UTVEC_REGW); + flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW); flopenr #(`XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW); flopenr #(`XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW); flopenr #(`XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW); diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index 3d07cc840..7fff94dbd 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -3,6 +3,7 @@ // // Written: David_Harris@hmc.edu 9 January 2021 // Modified: +// dottolia@hmc.edu 3 May 2021 - fix bug with stvec getting wrong value // // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 @@ -83,7 +84,7 @@ module csrs #(parameter assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN) && ~StallW; // CSRs - flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, ZERO, STVEC_REGW); //busybear: change reset to 0 + flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, ZERO, STVEC_REGW); //busybear: change reset to 0 flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, ZERO, SCAUSE_REGW); From ed4f2ecb24ec31bf602b82763818517a6dc58ec7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 3 May 2021 16:55:36 -0500 Subject: [PATCH 02/20] fixed subtle typo in icache fsm. Was messing up hit spill hit. I believe the mibench qsort benchmark runs after this icache fix. --- wally-pipelined/config/rv64BP/wally-config.vh | 38 ++-- .../config/rv64BP/wally-constants.vh | 2 + wally-pipelined/regression/wave.do | 195 +++++++++--------- wally-pipelined/src/ifu/icache.sv | 18 +- 4 files changed, 124 insertions(+), 129 deletions(-) diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 4d19d24e1..17a8c284a 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -24,11 +24,15 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// +// RV32 or RV64: XLEN = 32 or 64 +`define BUILDROOT 0 +`define BUSYBEAR 0 + // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 -//`define MISA (32'h00000104) -`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20) +//`define MISA (32'h00000105) +`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) `define A_SUPPORTED ((`MISA >> 0) % 2 == 1) `define C_SUPPORTED ((`MISA >> 2) % 2 == 1) `define D_SUPPORTED ((`MISA >> 3) % 2 == 1) @@ -54,7 +58,8 @@ `define MEM_DCACHE 0 `define MEM_DTIM 1 `define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 +`define MEM_VIRTMEM 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 // Address space `define RESET_VECTOR 64'h0000000000000000 @@ -69,20 +74,20 @@ `define BOOTTIMBASE 32'h00800000 `define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h00000000 -`define TIMRANGE 32'h007FFFFF -`define CLINTBASE 32'h02000000 -`define CLINTRANGE 32'h0000FFFF -`define GPIOBASE 32'h10012000 -`define GPIORANGE 32'h000000FF -`define UARTBASE 32'h10000000 -`define UARTRANGE 32'h00000007 -`define PLICBASE 32'h0C000000 -`define PLICRANGE 32'h03FFFFFF +`define TIMRANGE 32'h07FFFFFF +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 +`define PLICBASE 32'h0C000000 +`define PLICRANGE 32'h03FFFFFF // Test modes // Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 +`define GPIO_LOOPBACK_TEST 1 // Busybear special CSR config to match OVPSim `define OVPSIM_CSR_CONFIG 0 @@ -90,6 +95,13 @@ // Hardware configuration `define UART_PRESCALE 1 +// Interrupt configuration +`define PLIC_NUM_SRC 4 +// comment out the following if >=32 sources +`define PLIC_NUM_SRC_LT_32 +`define PLIC_GPIO_ID 3 +`define PLIC_UART_ID 4 + /* verilator lint_off STMTDLY */ /* verilator lint_off WIDTH */ /* verilator lint_off ASSIGNDLY */ diff --git a/wally-pipelined/config/rv64BP/wally-constants.vh b/wally-pipelined/config/rv64BP/wally-constants.vh index 55fb4e947..43d958632 100644 --- a/wally-pipelined/config/rv64BP/wally-constants.vh +++ b/wally-pipelined/config/rv64BP/wally-constants.vh @@ -26,6 +26,8 @@ /////////////////////////////////////////// // Virtual Memory Constants (sv39) +`define VPN_SEGMENT_BITS 9 `define VPN_BITS 27 `define PPN_BITS 44 +`define PPN_HIGH_SEGMENT_BITS 26 `define PA_BITS 56 diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index ec9194a01..5ba353aab 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -1,5 +1,4 @@ onerror {resume} -quietly virtual function -install /testbench/dut/hart/ifu/icache/cachemem -env /testbench/dut/hart/ifu/icache/cachemem { &{/testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[4], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[3], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[2], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[1], /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr[0] }} offset quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset @@ -8,68 +7,68 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall -add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DataStall +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPPredF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF +add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePC +add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdateEN +add wave -noupdate -expand -group Bpred -expand -group update -expand -group dir /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/UpdatePrediction +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -expand -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD @@ -89,18 +88,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemReadM add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM add wave -noupdate -group {dcache memory} /testbench/dut/hart/dmem/MemAckW @@ -158,9 +157,9 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0 add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill -add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave @@ -177,28 +176,21 @@ add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/i add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LINESIZE -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData -add wave -noupdate -expand -group icache -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWritePAdr -add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit -add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid -add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadTag -add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag -add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadAddr -add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData -add wave -noupdate -expand -group icache -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/ReadPAdr -add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable -add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine -add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WritePAdr -add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteSet -add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteTag -add wave -noupdate -expand -group icache -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen @@ -223,12 +215,11 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF -add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {9951515 ns} 0} {{Cursor 4} {1318991 ns} 0} +WaveRestoreCursors {{Cursor 2} {252630976 ns} 1} {{Cursor 4} {72696935 ns} 0} {{Cursor 3} {252631405 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 -configure wave -valuecolwidth 513 +configure wave -valuecolwidth 189 configure wave -justifyvalue left configure wave -signalnamewidth 1 configure wave -snapdistance 10 @@ -241,4 +232,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {9951431 ns} {9951599 ns} +WaveRestoreZoom {252630882 ns} {252631198 ns} diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index 2b8ee703e..a6f841242 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -216,14 +216,13 @@ module icachecontroller #(parameter LINESIZE = 256) ( // Cache fault signals //logic FaultStall; - //flopenl #(`XLEN) PCPFFlop(clk, reset, SavePC & ~StallF, PCPFinalF, `RESET_VECTOR, PCPF); // on spill we want to get the first 2 bytes of the next cache block. // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can // simply add 2 to land on the next cache block. assign PCSpillF = PCPF + 2'b10; // now we have to select between these three PCs - assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf + assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF; // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later. @@ -283,7 +282,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( end else if (~hit & ~spill) begin CntReset = 1'b1; NextState = STATE_MISS_FETCH_WDV; - end else if (~hit & spill) begin + end else if (~hit & spill) begin CntReset = 1'b1; PCMux = 2'b10; NextState = STATE_MISS_SPILL_FETCH_WDV; @@ -299,9 +298,10 @@ module icachecontroller #(parameter LINESIZE = 256) ( ICacheReadEn = 1'b1; if (hit) begin NextState = STATE_HIT_SPILL_FINAL; - end else + end else begin CntReset = 1'b1; NextState = STATE_HIT_SPILL_MISS_FETCH_WDV; + end end STATE_HIT_SPILL_MISS_FETCH_WDV: begin PCMux = 2'b10; @@ -424,16 +424,7 @@ module icachecontroller #(parameter LINESIZE = 256) ( endcase end - // fsm outputs - // stall CPU any time we are not in the ready state. any other state means the - // cache is either requesting data from the memory interface or handling a - // spill over two cycles. - // *** BUG this logic will need to change - //assign ICacheStallF = ((CurrState != STATE_READY) | ~hit | spill) | reset_q ? 1'b1 : 1'b0; - // save the PC anytime we are in the ready state. The saved value will be used as the PC may not be stable. - //assign SavePC = ((CurrState == STATE_READY) & hit) & ~spill ? 1'b1 : 1'b0; assign CntEn = PreCntEn & InstrAckF; - assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) || (CurrState == STATE_MISS_FETCH_WDV) || (CurrState == STATE_MISS_SPILL_FETCH_WDV) || @@ -456,7 +447,6 @@ module icachecontroller #(parameter LINESIZE = 256) ( // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with // more zeros after the addition. This will be the number of offset bits less the AHBByteLength. - // *** now a bug need to mux between PCPF and PCPF+2 assign InstrPAdrF = {{PCPTrunkF, {{LOGWPL}{1'b0}}} + FetchCount, {{OFFSETWIDTH-LOGWPL}{1'b0}}}; From 1f2da4c457556caba84a1c9ef100ea6b2097f554 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 3 May 2021 19:25:28 -0400 Subject: [PATCH 03/20] Flush uart print statements on \n --- wally-pipelined/src/uncore/uartPC16550D.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index a98543cab..c3e5af1cf 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -377,6 +377,7 @@ module uartPC16550D( txhrfull <= #1 1; end $write("%c",Din); // for testbench + if (Din == '\n') $flush; end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin From 81ed9b5d0604d11bd495c2941cec54d8f5500117 Mon Sep 17 00:00:00 2001 From: Elizabeth Hedenberg Date: Wed, 14 Apr 2021 23:09:37 -0400 Subject: [PATCH 04/20] coremark directory changes --- wally-pipelined/regression/wally-coremark_bare.do | 4 ++-- wally-pipelined/testbench/testbench-coremark_bare.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 9318c494a..64e20c1f2 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -54,7 +54,7 @@ add wave -divider add wave -divider Fetch add wave -hex /testbench/dut/hart/ifu/PCF -add wave -hex /testbench/dut/hart/ifu/InstrF +add wave -hex /testbench/dut/hart/ifu/ic/InstrF add wave /testbench/InstrFName add wave -divider Decode add wave -hex /testbench/dut/hart/ifu/PCD @@ -93,7 +93,7 @@ add wave -divider RAM add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -#add wave -hex -r /testbench/* +add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 3f2af76b6..860820bfd 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -48,7 +48,7 @@ module testbench(); // pick tests based on modes supported initial - tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"}; + tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"}; string signame, memfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -65,7 +65,7 @@ module testbench(); // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.InstrF, + dut.hart.ifu.ic.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); From 800f799b7cc5ba67d2f18e57b20018e5a1f13202 Mon Sep 17 00:00:00 2001 From: Elizabeth Hedenberg Date: Wed, 28 Apr 2021 14:21:53 -0400 Subject: [PATCH 07/20] coremark updates --- wally-pipelined/testbench/testbench-coremark_bare.sv | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 860820bfd..e7dbb9008 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -81,11 +81,12 @@ module testbench(); // read test vectors into memory memfilename = tests[0]; $readmemh(memfilename, dut.uncore.dtim.RAM); - for(j=268437702; j < 268566528; j = j+1) - dut.uncore.dtim.RAM[j] = 64'b0; + //for(j=268437955; j < 268566528; j = j+1) + //dut.uncore.dtim.RAM[j] = 64'b0; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr"; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab"; - reset = 1; # 22; reset = 0; + //dut.uncore.dtim.RAM[268437713]=64'b1; + reset = 1; # 22; reset = 0; end // generate clock to sequence tests always @@ -94,7 +95,7 @@ module testbench(); end always @(negedge clk) begin - if (dut.hart.priv.ebreakM) begin + if (dut.hart.priv.ecallM) begin #20; $display("Code ended with ebreakM"); $stop; From 08bfaeffe352639aed6faab149438d2c40af3cdb Mon Sep 17 00:00:00 2001 From: Elizabeth Hedenberg Date: Mon, 3 May 2021 19:27:34 -0400 Subject: [PATCH 08/20] coremark print statment --- wally-pipelined/config/coremark_bare/wally-config.vh | 12 ++++++++---- wally-pipelined/regression/wally-coremark_bare.do | 8 +++++--- wally-pipelined/testbench/testbench-coremark_bare.sv | 6 +++--- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index a6d64c6be..b42dd678d 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -57,7 +57,8 @@ `define MEM_DCACHE 0 `define MEM_DTIM 1 `define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 +`define MEM_VIRTMEM 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 // Address space `define RESET_VECTOR 64'h0000000080000000 @@ -85,7 +86,7 @@ // Test modes // Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 +`define GPIO_LOOPBACK_TEST 1 // Busybear special CSR config to match OVPSim `define OVPSIM_CSR_CONFIG 0 @@ -94,7 +95,10 @@ `define UART_PRESCALE 1 // Interrupt configuration -`define PLIC_NUM_SRC 53 +`define PLIC_NUM_SRC 4 +//comment out the following if >= 32 sources +`define PLIC_NUM_SRC_LT_32 +`define PLIC_GPIO_ID 3 `define PLIC_UART_ID 4 /* verilator lint_off STMTDLY */ @@ -105,5 +109,5 @@ `define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" `define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" +`define BPTYPE "BPGSHARE"//comments `define TESTSBP 0 diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 64e20c1f2..3f71fcbdf 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -35,6 +35,8 @@ vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../ vopt +acc work.testbench -o workopt vsim workopt +mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM + view wave -- display input and output signals as hexidecimal values @@ -54,7 +56,7 @@ add wave -divider add wave -divider Fetch add wave -hex /testbench/dut/hart/ifu/PCF -add wave -hex /testbench/dut/hart/ifu/ic/InstrF +add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF add wave /testbench/InstrFName add wave -divider Decode add wave -hex /testbench/dut/hart/ifu/PCD @@ -90,10 +92,10 @@ add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* add wave -divider Regfile_itself add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf add wave -divider RAM -add wave -hex -r /testbench/dut/uncore/dtim/RAM +#add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -add wave -hex -r /testbench/* +#add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index e7dbb9008..c0441eb24 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -65,7 +65,7 @@ module testbench(); // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.ic.InstrF, + dut.hart.ifu.icache.controller.FinalInstrRawF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); @@ -103,8 +103,8 @@ module testbench(); end initial begin - $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.Predictor.DirPredictor.PHT.memory); - $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); + $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); + $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); end endmodule From 8758b6efa14e66b2ced557ea84b37a68a3fa48e2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 3 May 2021 19:37:45 -0400 Subject: [PATCH 09/20] Flush uart print statements on \n --- wally-pipelined/src/uncore/uartPC16550D.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index c3e5af1cf..5871c9e60 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -377,7 +377,7 @@ module uartPC16550D( txhrfull <= #1 1; end $write("%c",Din); // for testbench - if (Din == '\n') $flush; + if (Din == 13) $flush; end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin From 743011194bc101303eb1a9e71834457b9f04f96a Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 3 May 2021 19:41:37 -0400 Subject: [PATCH 10/20] Flush uart print statements on \n --- wally-pipelined/src/uncore/uartPC16550D.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index 5871c9e60..3509b5b0b 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -377,7 +377,7 @@ module uartPC16550D( txhrfull <= #1 1; end $write("%c",Din); // for testbench - if (Din == 13) $flush; + if (Din == 13) $fflush; end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin From 062120f94476cd2cd8c337508d70267b636496d5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 3 May 2021 19:51:51 -0400 Subject: [PATCH 12/20] Flush uart print statements on \n --- wally-pipelined/src/uncore/uartPC16550D.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index 3509b5b0b..d4029fafa 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -377,7 +377,8 @@ module uartPC16550D( txhrfull <= #1 1; end $write("%c",Din); // for testbench - if (Din == 13) $fflush; + //if (Din == 13) $fflush; + $fflush; end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin From 96e90402c553ca5c1fcc49db326084e9f5a549cc Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 3 May 2021 20:04:44 -0400 Subject: [PATCH 13/20] Rolled back fflush on uart. Use -syncio in Modelsim command line instead. --- wally-pipelined/src/uncore/uartPC16550D.sv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index d4029fafa..6e173d59e 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -377,9 +377,7 @@ module uartPC16550D( txhrfull <= #1 1; end $write("%c",Din); // for testbench - //if (Din == 13) $fflush; - $fflush; - end + end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin if (~txfifoempty) begin From 0282aebec7b44fe6ea3950707259e6959229a899 Mon Sep 17 00:00:00 2001 From: Shriya Nadgauda Date: Mon, 3 May 2021 22:07:36 -0400 Subject: [PATCH 14/20] updated pipeline tests --- wally-pipelined/config/rv32ic/wally-config.vh | 2 +- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- .../testbench/testbench-imperas.sv | 37 ++- wally-pipelined/testgen/testgen-PIPELINE.py | 297 ++++++++++++++---- 4 files changed, 259 insertions(+), 79 deletions(-) diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index fa16fdb86..0d5d0bf70 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -69,7 +69,7 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +`define TIMRANGE 32'h0FFFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 3ef92055a..78653f896 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -73,7 +73,7 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF `define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0007FFFF +`define TIMRANGE 32'h0FFFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index f7a77b6b1..aeb0a9e8d 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -34,9 +34,11 @@ module testbench(); logic clk; logic reset; + parameter SIGNATURESIZE = 5000000; + int test, i, errors, totalerrors; - logic [31:0] sig32[0:10000]; - logic [`XLEN-1:0] signature[0:10000]; + logic [31:0] sig32[0:SIGNATURESIZE]; + logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; @@ -115,6 +117,7 @@ module testbench(); }; string tests64i[] = '{ + "rv64i/WALLY-PIPELINE-100K", "f7ff0", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", @@ -260,6 +263,7 @@ module testbench(); }; string tests32i[] = { + "rv32i/WALLY-PIPELINE-100K", "10a800", "rv32i/I-ADD-01", "2000", "rv32i/I-ADDI-01","2000", "rv32i/I-AND-01","2000", @@ -275,7 +279,7 @@ module testbench(); "rv32i/I-EBREAK-01","2000", "rv32i/I-ECALL-01","2000", "rv32i/I-ENDIANESS-01","2010", - "rv32i/I-IO-01","2030", + "rv32i/I-IO-01","2030rv", "rv32i/I-JAL-01","3000", "rv32i/I-JALR-01","3000", "rv32i/I-LB-01","3020", @@ -334,8 +338,7 @@ module testbench(); "rv32i/WALLY-CSRRC", "4000", "rv32i/WALLY-CSRRWI", "3000", "rv32i/WALLY-CSRRSI", "3000", - "rv32i/WALLY-CSRRCI", "3000", - "rv32i/WALLY-PIPELINE", "1a800" + "rv32i/WALLY-CSRRCI", "3000" }; string testsBP64[] = '{ @@ -358,16 +361,16 @@ module testbench(); }; string tests32p[] = '{ - "rv32p/WALLY-MCAUSE", "2000", - "rv32p/WALLY-SCAUSE", "2000", - "rv32p/WALLY-MEPC", "5000", - "rv32p/WALLY-SEPC", "4000", - "rv32p/WALLY-MTVAL", "5000", - "rv32p/WALLY-STVAL", "4000", - "rv32p/WALLY-MARCHID", "4000", - "rv32p/WALLY-MIMPID", "4000", - "rv32p/WALLY-MHARTID", "4000", - "rv32p/WALLY-MVENDORID", "4000" + // "rv32p/WALLY-MCAUSE", "2000", + // "rv32p/WALLY-SCAUSE", "2000", + // "rv32p/WALLY-MEPC", "5000", + // "rv32p/WALLY-SEPC", "4000", + // "rv32p/WALLY-MTVAL", "5000", + // "rv32p/WALLY-STVAL", "4000", + // "rv32p/WALLY-MARCHID", "4000", + // "rv32p/WALLY-MIMPID", "4000", + // "rv32p/WALLY-MHARTID", "4000", + // "rv32p/WALLY-MVENDORID", "4000" }; string tests64periph[] = '{ @@ -499,7 +502,7 @@ module testbench(); $display("Code ended with ecall with gp = 1"); #60; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests - for(i=0; i<10000; i=i+1) begin + for(i=0; i 0: + newValueBin = bin(newValue)[2:] + elif newValue == 0: + newValueBin = "0" * model.xlen + else: + newValueBin = bin(newValue)[3:] + newValueBinTrunk = newValueBin[-model.xlen:] + rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) + model.pc += 4 + return 'addiw {}, {}, MASK_XLEN({})'.format(rd.getRegName(), rs1.getRegName(), imm.getDecValue()) + + @classmethod + def Instr_slliw(self, model, rd = None, rs1 = None, imm = None): + bits = rs1.bits + immBits = imm.bits[-5:] + immShift = int(immBits, 2) + shifted = bits[-(len(bits) - immShift):] + shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) + rd.setValue(newValue = shiftedExt, signed = 1) + model.pc += 4 + return 'slliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) + + @classmethod + def Instr_srliw(self, model, rd = None, rs1 = None, imm = None): + bits = rs1.bits + immBits = imm.bits[-5:] + immShift = int(immBits, 2) + shifted = bits[0:len(bits) - immShift] + extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'srliw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) + + @classmethod + def Instr_sraiw(self, model, rd = None, rs1 = None, imm = None): + bits = rs1.bits + immBits = imm.bits[-5:] + immShift = int(immBits, 2) + shifted = bits[0:len(bits) - immShift] + extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'sraiw {}, {}, 0b{}'.format(rd.getRegName(), rs1.getRegName(), immBits) + + @classmethod + def Instr_Sd(self, model, rs1 = None, rs2 = None, imm = None): + addr = imm.getDecValue() + model.memory.updateMemory(addr = addr, value = rs2.bits, granularity = GRANULARITY.WORD) + model.pc += 4 + return 'Sd {}, {}({})'.format(rs2.getRegName(), imm.getDecValue(), rs1.getRegName()) + + @classmethod + def Instr_addw(self, model, rd = None, rs1 = None, rs2 = None): + newValue = rs1.getDecValue() + rs2.getDecValue() + newValueBin = 0 + if newValue > 0: + newValueBin = bin(newValue)[2:] + elif newValue == 0: + newValueBin = "0" * model.xlen + else: + newValueBin = bin(newValue)[3:] + newValueBinTrunk = newValueBin[-model.xlen:] + rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) + model.pc += 4 + return 'addw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_subw(self, model, rd = None, rs1 = None, rs2 = None): + newValue = rs1.getDecValue() - rs2.getDecValue() + newValueBin = 0 + if newValue > 0: + newValueBin = bin(newValue)[2:] + elif newValue == 0: + newValueBin = "0" * model.xlen + else: + newValueBin = bin(newValue)[3:] + newValueBinTrunk = newValueBin[-model.xlen:] + rd.setBits(newBits = signExtend(inputBits = newValueBinTrunk, resultNumBits = model.xlen), signed = 1) + model.pc += 4 + return 'subw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_sllw(self, model, rd = None, rs1 = None, rs2 = None): + bits = rs1.bits + rs2Bin = rs2.bits[-5:] + rs2Shift = int(rs2Bin,2) + shifted = bits[-(len(bits) - rs2Shift):] + shiftedExt = binToDec(inputBits = shifted + '0'*(model.xlen - len(shifted))) + rd.setValue(newValue = shiftedExt, signed = 1) + model.pc += 4 + return 'sllw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_srlw(self, model, rd = None, rs1 = None, rs2 = None): + bits = rs1.bits + rs2Bin = rs2.bits[-5:] + rs2Shift = int(rs2Bin,2) + shifted = bits[0:len(bits) - rs2Shift] + extShifted = zeroExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'srlw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + @classmethod + def Instr_sraw(self, model, rd = None, rs1 = None, rs2 = None): + bits = rs1.bits + rs2Bin = rs2.bits[-5:] + rs2Shift = int(rs2Bin,2) + shifted = bits[0:len(bits) - rs2Shift] + extShifted = signExtend(inputBits = shifted, resultNumBits = model.xlen) + rd.setBits(newBits = extShifted, signed = 1) + model.pc += 4 + return 'sraw {}, {}, {}'.format(rd.getRegName(), rs1.getRegName(), rs2.getRegName()) + + ################################################################################################### # Global Constants ################################################################################################### @@ -1693,7 +1870,7 @@ GRANULARITY = Enum('granularity', ['WORD', 'HALFWORD', 'BYTE']) INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ - 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal'], \ + 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'jal', 'jalr'], \ 'RV64I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', \ 'srli', 'srai', 'ori', 'andi', 'auipc', 'sb', 'sh', 'sw', 'add', 'sub', \ 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', 'lui', 'beq', \ @@ -1703,9 +1880,11 @@ INSTRSETS = {'RV32I': ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', } -InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and'], \ - 'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr'], \ - 'S' : ['sw', 'sh', 'sb'], \ +InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and', \ + 'addw', 'subw', 'sllw', 'srlw', 'sraw'], \ + 'I' : ['lb', 'lh', 'lw', 'lbu', 'lhu', 'addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi', 'jalr', \ + 'ld', 'lwu', 'addiw', 'slliw', 'srliw', 'sraiw'], \ + 'S' : ['sw', 'sh', 'sb', 'Sd'], \ 'B' : ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu'], \ 'U' : ['lui', 'auipc'], \ 'J' : ['jal'], \ @@ -1714,27 +1893,25 @@ InstrTypes = { 'R' : ['add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', # Main Body ################################################################################################### -XLEN = ['32'] +XLEN = ['32', '64'] INSTRUCTION_TYPE = ['I'] -NUMINSTR = 70000 +NUMINSTR = [100000, 1000000] IMPERASPATH = "../../imperas-riscv-tests/riscv-test-suite/" seed(42) np.random.seed(42) -for xlen in XLEN: - memInit = {} - for i in range(0, 400, 4): - val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1) - memInit[i] = val - for instrType in INSTRUCTION_TYPE: - instrSet = 'RV' + xlen + instrType - - print('Generating Assembly for {}'.format(instrSet)) - - dut = TestGen(numInstr=NUMINSTR, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH) - # regFile = - dut.model.memory.populateMemory(memDict = memInit) - dut.exportASM(instrSet = instrSet, instrTypes = instrType) - - +for num_instructions in NUMINSTR: + for xlen in XLEN: + memInit = {} + for i in range(0, 400, 4): + val = randBinary(signed = 0, numBits = int(xlen), valueAlignment = 1) + memInit[i] = val + for instrType in INSTRUCTION_TYPE: + instrSet = 'RV' + xlen + instrType + print('Generating {} Assembly Instructions for {}'.format(num_instructions, instrSet)) + + dut = TestGen(numInstr=num_instructions, immutableRegsDict = {0 : 0, 6 : 0, 7 : 0}, instrSet=instrSet, imperasPath=IMPERASPATH) + # regFile = + dut.model.memory.populateMemory(memDict = memInit) + dut.exportASM(instrSet = instrSet, instrTypes = instrType) \ No newline at end of file From 0be6b81df90ea2845ef2a597014458c46a6e663f Mon Sep 17 00:00:00 2001 From: Shriya Nadgauda Date: Mon, 3 May 2021 22:15:05 -0400 Subject: [PATCH 15/20] finishing merge conflict changes --- wally-pipelined/config/rv32ic/wally-config.vh | 5 ----- wally-pipelined/config/rv64ic/wally-config.vh | 5 ----- wally-pipelined/testbench/testbench-imperas.sv | 5 ----- 3 files changed, 15 deletions(-) diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index e835136f5..17daa5722 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -68,13 +68,8 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF -<<<<<<< HEAD -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0FFFFFFF -======= `define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF ->>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 6bcd9273c..2e0d92fb8 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -72,13 +72,8 @@ `define BOOTTIMBASE 32'h00000000 `define BOOTTIMRANGE 32'h00003FFF -<<<<<<< HEAD -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h0FFFFFFF -======= `define TIMBASE 32'h80000000 `define TIMRANGE 32'h07FFFFFF ->>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0 `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index c17d6e2d7..e2561db77 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -38,13 +38,8 @@ module testbench(); parameter SIGNATURESIZE = 5000000; int test, i, errors, totalerrors; -<<<<<<< HEAD - logic [31:0] sig32[0:SIGNATURESIZE]; - logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; -======= logic [31:0] sig32[0:MAXSIGLEN]; logic [`XLEN-1:0] signature[0:MAXSIGLEN]; ->>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0 logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; From c10d332c6ee96b3806292eb204bbcbb8a7973747 Mon Sep 17 00:00:00 2001 From: Shriya Nadgauda Date: Mon, 3 May 2021 22:16:58 -0400 Subject: [PATCH 16/20] working testbench-imperas --- .../testbench/testbench-imperas.sv | 204 +----------------- 1 file changed, 8 insertions(+), 196 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index e2561db77..aeb0a9e8d 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -29,8 +29,7 @@ module testbench(); parameter DEBUG = 0; parameter TESTSBP = 0; - parameter TESTSPERIPH = 0 ; // set to 0 for regression - localparam MAXSIGLEN = 1000000; + parameter TESTSPERIPH = 0; // set to 0 for regression logic clk; logic reset; @@ -38,8 +37,8 @@ module testbench(); parameter SIGNATURESIZE = 5000000; int test, i, errors, totalerrors; - logic [31:0] sig32[0:MAXSIGLEN]; - logic [`XLEN-1:0] signature[0:MAXSIGLEN]; + logic [31:0] sig32[0:SIGNATURESIZE]; + logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; @@ -55,71 +54,7 @@ module testbench(); string tests64f[] = '{ "rv64f/I-FADD-S-01", "2000", - "rv64f/I-FCLASS-S-01", "2000", - "rv64f/I-FCVT-S-L-01", "2000", - "rv64f/I-FCVT-S-LU-01", "2000", - "rv64f/I-FCVT-S-W-01", "2000", - "rv64f/I-FCVT-S-WU-01", "2000", - "rv64f/I-FCVT-L-S-01", "2000", - "rv64f/I-FCVT-LU-S-01", "2000", - "rv64f/I-FCVT-W-S-01", "2000", - "rv64f/I-FCVT-WU-S-01", "2000", - "rv64f/I-FDIV-S-01", "2000", - "rv64f/I-FEQ-S-01", "2000", - "rv64f/I-FLE-S-01", "2000", - "rv64f/I-FLT-S-01", "2000", - "rv64f/I-FMADD-S-01", "2000", - "rv64f/I-FMAX-S-01", "2000", - "rv64f/I-FMIN-S-01", "2000", - "rv64f/I-FMSUB-S-01", "2000", - "rv64f/I-FMUL-S-01", "2000", - "rv64f/I-FMV-W-X-01", "2000", - "rv64f/I-FMV-X-W-01", "2000", - "rv64f/I-FNMADD-S-01", "2000", - "rv64f/I-FNMSUB-S-01", "2000", - "rv64f/I-FSGNJ-S-01", "2000", - "rv64f/I-FSGNJN-S-01", "2000", - "rv64f/I-FSGNJX-S-01", "2000", - "rv64f/I-FSQRT-S-01", "2000", - "rv64f/I-FSW-01", "2000", - "rv64f/I-FLW-01", "2110", - "rv64f/I-FSUB-S-01", "2000" - }; - - - string tests64d[] = '{ - "rv64d/I-FADD-D-01", "2000", - "rv64d/I-FCLASS-D-01", "2000", - "rv64d/I-FCVT-D-L-01", "2000", - "rv64d/I-FCVT-D-LU-01", "2000", - "rv64d/I-FCVT-D-S-01", "2000", - "rv64d/I-FCVT-D-W-01", "2000", - "rv64d/I-FCVT-D-WU-01", "2000", - "rv64d/I-FCVT-L-D-01", "2000", - "rv64d/I-FCVT-LU-D-01", "2000", - "rv64d/I-FCVT-S-D-01", "2000", - "rv64d/I-FCVT-W-D-01", "2000", - "rv64d/I-FCVT-WU-D-01", "2000", - "rv64d/I-FDIV-D-01", "2000", - "rv64d/I-FEQ-D-01", "2000", - "rv64d/I-FLD-D-01", "2420", - "rv64d/I-FLE-D-01", "2000", - "rv64d/I-FLT-D-01", "2000", - "rv64d/I-FMADD-D-01", "2000", - "rv64d/I-FMAX-D-01", "2000", - "rv64d/I-FMIN-D-01", "2000", - "rv64d/I-FMSUB-D-01", "2000", - "rv64d/I-FMUL-D-01", "2000", - "rv64d/I-FMV-D-X-01", "2000", - "rv64d/I-FMV-X-D-01", "2000", - "rv64d/I-FNMADD-D-01", "2000", - "rv64d/I-FNMSUB-D-01", "2000", - "rv64d/I-FSD-01", "2000", - "rv64d/I-FSGNJ-D-01", "2000", - "rv64d/I-FSGNJN-D-01", "2000", - "rv64d/I-FSGNJX-D-01", "2000", - "rv64d/I-FSQRTD-01", "2000", - "rv64d/I-FSUB-D-01", "2000" + "rv64f/I-FCLASS-S-01", "2000" }; string tests64a[] = '{ @@ -327,40 +262,6 @@ module testbench(); "rv32i/I-MISALIGN_JMP-01","2000" }; -string tests32f[] = '{ - "rv32f/I-FADD-S-01", "2000", - "rv32f/I-FCLASS-S-01", "2000", - "rv32f/I-FCVT-S-L-01", "2000", - "rv32f/I-FCVT-S-LU-01", "2000", - "rv32f/I-FCVT-S-W-01", "2000", - "rv32f/I-FCVT-S-WU-01", "2000", - "rv32f/I-FCVT-L-S-01", "2000", - "rv32f/I-FCVT-LU-S-01", "2000", - "rv32f/I-FCVT-W-S-01", "2000", - "rv32f/I-FCVT-WU-S-01", "2000", - "rv32f/I-FDIV-S-01", "2000", - "rv32f/I-FEQ-S-01", "2000", - "rv32f/I-FLE-S-01", "2000", - "rv32f/I-FLT-S-01", "2000", - "rv32f/I-FMADD-S-01", "2000", - "rv32f/I-FMAX-S-01", "2000", - "rv32f/I-FMIN-S-01", "2000", - "rv32f/I-FMSUB-S-01", "2000", - "rv32f/I-FMUL-S-01", "2000", - "rv32f/I-FMV-W-X-01", "2000", - "rv32f/I-FMV-X-W-01", "2000", - "rv32f/I-FNMADD-S-01", "2000", - "rv32f/I-FNMSUB-S-01", "2000", - "rv32f/I-FSGNJ-S-01", "2000", - "rv32f/I-FSGNJN-S-01", "2000", - "rv32f/I-FSGNJX-S-01", "2000", - "rv32f/I-FSQRT-S-01", "2000", - "rv32f/I-FSW-01", "2000", - "rv32f/I-FLW-01", "2110", - "rv32f/I-FSUB-S-01", "2000" - }; - - string tests32i[] = { "rv32i/WALLY-PIPELINE-100K", "10a800", "rv32i/I-ADD-01", "2000", @@ -447,23 +348,19 @@ string tests32f[] = '{ }; string tests64p[] = '{ - "rv64p/WALLY-MCAUSE", "4000", - "rv64p/WALLY-SCAUSE", "3000", + "rv64p/WALLY-MCAUSE", "2000", + "rv64p/WALLY-SCAUSE", "2000", "rv64p/WALLY-MEPC", "5000", "rv64p/WALLY-SEPC", "4000", "rv64p/WALLY-MTVAL", "6000", "rv64p/WALLY-STVAL", "4000", - "rv64p/WALLY-MTVEC", "2000", "rv64p/WALLY-MARCHID", "4000", "rv64p/WALLY-MIMPID", "4000", "rv64p/WALLY-MHARTID", "4000", - "rv64p/WALLY-MVENDORID", "4000", - "rv64p/WALLY-MIE", "3000", - "rv64p/WALLY-MEDELEG", "4000" + "rv64p/WALLY-MVENDORID", "4000" }; string tests32p[] = '{ -<<<<<<< HEAD // "rv32p/WALLY-MCAUSE", "2000", // "rv32p/WALLY-SCAUSE", "2000", // "rv32p/WALLY-MEPC", "5000", @@ -474,20 +371,6 @@ string tests32f[] = '{ // "rv32p/WALLY-MIMPID", "4000", // "rv32p/WALLY-MHARTID", "4000", // "rv32p/WALLY-MVENDORID", "4000" -======= - "rv32p/WALLY-MCAUSE", "4000", - "rv32p/WALLY-SCAUSE", "3000", - "rv32p/WALLY-MEPC", "5000", - "rv32p/WALLY-SEPC", "4000", - "rv32p/WALLY-MTVAL", "5000", - "rv32p/WALLY-STVAL", "4000", - "rv32p/WALLY-MARCHID", "4000", - "rv32p/WALLY-MIMPID", "4000", - "rv32p/WALLY-MHARTID", "4000", - "rv32p/WALLY-MVENDORID", "4000" - //"rv32p/WALLY-MEDELEG", "4000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though. - //"rv32p/WALLY-MTVEC", "2000" // all 32 bit tests are currently failing, so haven't been able to confirm this test works yet. It should, though. ->>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0 }; string tests64periph[] = '{ @@ -542,7 +425,7 @@ string tests32f[] = '{ if (TESTSPERIPH) begin tests = tests32periph; end else begin - tests = {tests32i, tests32p, tests32periph}; + tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; else tests = {tests, tests32iNOc}; if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; @@ -619,11 +502,7 @@ string tests32f[] = '{ $display("Code ended with ecall with gp = 1"); #60; // give time for instructions in pipeline to finish // clear signature to prevent contamination from previous tests -<<<<<<< HEAD for(i=0; i>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0 sig32[i] = 'bx; end @@ -631,11 +510,7 @@ string tests32f[] = '{ signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"}; $readmemh(signame, sig32); i = 0; -<<<<<<< HEAD while (i < SIGNATURESIZE) begin -======= - while (i < MAXSIGLEN) begin ->>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0 if (`XLEN == 32) begin signature[i] = sig32[i]; i = i+1; @@ -740,13 +615,11 @@ module instrNameDecTB( logic [2:0] funct3; logic [6:0] funct7; logic [11:0] imm; - logic [4:0] rs2; assign op = instr[6:0]; assign funct3 = instr[14:12]; assign funct7 = instr[31:25]; assign imm = instr[31:20]; - assign rs2 = instr[24:20]; // it would be nice to add the operands to the name // create another variable called decoded @@ -870,67 +743,6 @@ module instrNameDecTB( else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D"; else name = "ILLEGAL"; 10'b0001111_???: name = "FENCE"; - 10'b1000011_???: name = "FMADD"; - 10'b1000111_???: name = "FMSUB"; - 10'b1001011_???: name = "FNMSUB"; - 10'b1001111_???: name = "FNMADD"; - 10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD"; - else if (funct7[6:2] == 5'b00001) name = "FSUB"; - else if (funct7[6:2] == 5'b00010) name = "FMUL"; - else if (funct7[6:2] == 5'b00011) name = "FDIV"; - else if (funct7[6:2] == 5'b01011) name = "FSQRT"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU"; - else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W"; - else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X"; - else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.W"; // DOUBLE - else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.W.X"; // DOUBLE - else if (funct7[6:2] == 5'b00100) name = "FSGNJ"; - else if (funct7[6:2] == 5'b00101) name = "FMIN"; - else if (funct7[6:2] == 5'b10100) name = "FLE"; - else name = "ILLEGAL"; - 10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD"; - else if (funct7[6:2] == 5'b00001) name = "FSUB"; - else if (funct7[6:2] == 5'b00010) name = "FMUL"; - else if (funct7[6:2] == 5'b00011) name = "FDIV"; - else if (funct7[6:2] == 5'b01011) name = "FSQRT"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU"; - else if (funct7[6:2] == 5'b00100) name = "FSGNJN"; - else if (funct7[6:2] == 5'b00101) name = "FMAX"; - else if (funct7[6:2] == 5'b10100) name = "FLT"; - else if (funct7[6:2] == 5'b11100) name = "FCLASS"; - else name = "ILLEGAL"; - 10'b0101111_010: if (funct7[6:2] == 5'b00000) name = "FADD"; - else if (funct7[6:2] == 5'b00001) name = "FSUB"; - else if (funct7[6:2] == 5'b00010) name = "FMUL"; - else if (funct7[6:2] == 5'b00011) name = "FDIV"; - else if (funct7[6:2] == 5'b01011) name = "FSQRT"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU"; - else if (funct7[6:2] == 5'b00100) name = "FSGNJX"; - else if (funct7[6:2] == 5'b10100) name = "FEQ"; - else name = "ILLEGAL"; - 10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD"; - else if (funct7[6:2] == 5'b00001) name = "FSUB"; - else if (funct7[6:2] == 5'b00010) name = "FMUL"; - else if (funct7[6:2] == 5'b00011) name = "FDIV"; - else if (funct7[6:2] == 5'b01011) name = "FSQRT"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S"; - else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W"; - else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU"; - else name = "ILLEGAL"; - 10'b0000111_010: name = "FLW"; - 10'b0100111_010: name = "FSW"; - 10'b0000111_010: name = "FLD"; - 10'b0100111_010: name = "FSD"; default: name = "ILLEGAL"; endcase endmodule From db4e447a251296ccab922735d8501eb6c2843da6 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Mon, 3 May 2021 22:19:50 -0400 Subject: [PATCH 17/20] Add mtvec and stvec tests to testbench --- .../testbench/testbench-imperas.sv | 4 + .../testgen/privileged/testgen-TVAL.py | 4 +- .../testgen/privileged/testgen-TVEC.py | 496 +++++++++--------- 3 files changed, 263 insertions(+), 241 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index aeb0a9e8d..e08768425 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -354,6 +354,8 @@ module testbench(); "rv64p/WALLY-SEPC", "4000", "rv64p/WALLY-MTVAL", "6000", "rv64p/WALLY-STVAL", "4000", + "rv64p/WALLY-MTVEC", "2000", + "rv64p/WALLY-STVEC", "2000", "rv64p/WALLY-MARCHID", "4000", "rv64p/WALLY-MIMPID", "4000", "rv64p/WALLY-MHARTID", "4000", @@ -371,6 +373,8 @@ module testbench(); // "rv32p/WALLY-MIMPID", "4000", // "rv32p/WALLY-MHARTID", "4000", // "rv32p/WALLY-MVENDORID", "4000" + // "rv32p/WALLY-MTVEC", "2000", + // "rv32p/WALLY-STVEC", "2000" }; string tests64periph[] = '{ diff --git a/wally-pipelined/testgen/privileged/testgen-TVAL.py b/wally-pipelined/testgen/privileged/testgen-TVAL.py index 9cb6b6d81..8a728f7a6 100644 --- a/wally-pipelined/testgen/privileged/testgen-TVAL.py +++ b/wally-pipelined/testgen/privileged/testgen-TVAL.py @@ -190,7 +190,9 @@ for xlen in xlens: # This is the address we write results to # x6: Starting address we should write expected results to # ... - # x1 - x5 can be freely written + # x4 & x5 can be freely written + # x3 — DO NOT WRITE ANY NON-ZERO VALUE TO THIS — test exits on ecall if x3 = 1 (x3 is gp) + # x1 & x2 can be freely written diff --git a/wally-pipelined/testgen/privileged/testgen-TVEC.py b/wally-pipelined/testgen/privileged/testgen-TVEC.py index a6eef5d22..8b731be81 100644 --- a/wally-pipelined/testgen/privileged/testgen-TVEC.py +++ b/wally-pipelined/testgen/privileged/testgen-TVEC.py @@ -51,52 +51,39 @@ def writeVectors(storecmd, returningInstruction): # Illegal Instruction - writeTest(storecmd, f, r, f""" - .fill 1, 4, 0 - """, False, 0) + # writeTest(storecmd, f, r, f""" + # .fill 1, 4, 0 + # """, False, 0) - # Breakpoint - if returningInstruction != "ebreak": + # # Breakpoint + # if returningInstruction != "ebreak": + # writeTest(storecmd, f, r, f""" + # ebreak + # """, False, 0) + + # # Load Address Misaligned + # writeTest(storecmd, f, r, f""" + # lw x0, 11(x0) + # """, False, 0) + + # # Load Access fault: False, 5 + + # # Store/AMO address misaligned + # writeTest(storecmd, f, r, f""" + # sw x0, 11(x0) + # """, False, 0) + + # # Environment call from u-mode: only for when only M and U mode enabled? + # # writeTest(storecmd, f, r, f""" + # # ecall + # # """, False, 8, "u") + if returningInstruction != "ecall": writeTest(storecmd, f, r, f""" - ebreak + ecall """, False, 0) - # Load Address Misaligned - writeTest(storecmd, f, r, f""" - lw x0, 11(x0) - """, False, 0) - # Load Access fault: False, 5 - - # Store/AMO address misaligned - writeTest(storecmd, f, r, f""" - sw x0, 11(x0) - """, False, 0) - - # Environment call from u-mode: only for when only M and U mode enabled? - # writeTest(storecmd, f, r, f""" - # ecall - # """, False, 8, "u") - if returningInstruction != "ecall": - if fromMode == "u": - writeTest(storecmd, f, r, f""" - ecall - """, False, 0) - - # Environment call from s-mode - if fromMode == "s": - writeTest(storecmd, f, r, f""" - ecall - """, False, 0) - - # Environment call from m-mode - if fromMode == "m": - writeTest(storecmd, f, r, f""" - ecall - """, False, 0) - - - if fromMode == "m": + if fromMode == "m" and testMode == "m": expectedCode = 7 if fromMode == "m" else 5 clintAddr = "0x2004000" @@ -105,9 +92,9 @@ def writeVectors(storecmd, returningInstruction): csrrs x0, {fromMode}status, x1 la x18, {clintAddr} - lw x11, 0(x18) - li x1, 0x3fffffffffffffff - {storecmd} x1, 0(x18) + # lw x11, 0(x18) + # li x1, 0x3fffffffffffffff + # {storecmd} x1, 0(x18) li x1, 0x80 csrrs x0, {fromMode}ie, x1 @@ -132,7 +119,7 @@ def writeVectors(storecmd, returningInstruction): def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""): - global testnum, storeAddressOffset + global testnum, storeAddressOffset, xlen expected = code @@ -156,19 +143,27 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""): {test} """ - lines += f""" + + if not areVectoredTrapsSupported or not vectoredInterrupts: + expected = 0 + + writeGeneralTest(storecmd, f, r, lines, expected) + +def writeGeneralTest(storecmd, f, r, test, expected): + global testnum, storeAddressOffset, xlen + + lines = f""" + {test} {storecmd} x25, {testnum * wordsize}(x6) """ - if not areVectoredTrapsSupported: - expected = 0 - f.write(lines) if (xlen == 32): line = formatrefstr.format(expected)+"\n" else: line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" r.write(line) + testnum = testnum+1 ################################## @@ -177,7 +172,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""): author = "dottolia@hmc.edu" xlens = [32, 64] -testCount = 16; +testCount = 4; # setup # Change this seed to a different constant value for every test @@ -219,6 +214,25 @@ for xlen in xlens: for line in h: f.write(line) + # Ensure MODE of *tvec (last 2 bits) is either 00 or 01 + f.write(f""" + csrr x19, {testMode}tvec + """) + + for i in range(0, 16): + i = i; + trySet = i | 0b10; + expected = trySet & 0xFFFF_FFFFD; + writeGeneralTest(storecmd, f, r, f""" + li x1, {trySet} + csrw {testMode}tvec, x1 + csrr x25, {testMode}tvec + """, expected) + + f.write(f""" + csrw {testMode}tvec, x19 + """) + # We need to leave at least one bit in medeleg unset so that we have a way to get # back to machine mode when the tests are complete (otherwise we'll only ever be able # to get up to supervisor mode). @@ -233,211 +247,218 @@ for xlen in xlens: # For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole # returning instruction. For others, like testgen-CAUSE, we'll need to put # both ebreak and ecall here. + + for returningInstruction in ["ebreak"]: + for vectoredInterrupts in [True, False]: - # All registers used: - # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise - # ... - # x28: address trap handler should jump to for the test - # x27: address the test should return to after the test - # ... - # x25: value to write to memory - # ... - # x20: intermediate value in trap handler. Don't overwrite this! - # x19: mtvec old value - # x18: medeleg old value - # x17: sedeleg old value (currently unused — user mode traps deprecated) - # x16: mideleg old value - # ... - # x10 - x14 can be freely written - # ... - # x7: copy of x6. Increment this instead of using an offset on x6. - # this allows us to create more than 2048/wordlen tests. - # This is the address we write results to - # x6: Starting address we should write expected results to - # ... - # x1 - x5 can be freely written + # All registers used: + # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise + # ... + # x28: address trap handler should jump to for the test + # x27: address the test should return to after the test + # ... + # x25: value to write to memory + # ... + # x20: intermediate value in trap handler. Don't overwrite this! + # x19: mtvec old value + # x18: medeleg old value + # x17: sedeleg old value (currently unused — user mode traps deprecated) + # x16: mideleg old value + # ... + # x10 - x14 can be freely written + # ... + # x7: copy of x6. Increment this instead of using an offset on x6. + # this allows us to create more than 2048/wordlen tests. + # This is the address we write results to + # x6: Starting address we should write expected results to + # ... + # x1 - x5 can be freely written - # Set up x7 and store old value of mtvec - lines = f""" - add x7, x6, x0 - csrr x19, mtvec - """ - - # Not used — user mode traps are deprecated - if testMode == "u": - lines += f""" - csrr x17, sedeleg - li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"} - csrs sedeleg, x9 - """ - - # Code that will jump to the test (x28 is set in writeTest above) - testJumpCode = f""" - auipc x27, 0 - addi x27, x27, 12 - jr x28 - """ - - beforeCode = "" - for i in range(0, 16): - beforeCode+=f""" - nop - nop - li x25, {i} - j _j_m_trap_end_{returningInstruction} + # Set up x7 and store old value of mtvec + lines = f""" + # add x7, x6, x0 + csrr x19, mtvec """ - ######## - ####### FIXME: wally is causing exception code 1 when you put non 4-bit aligned into mtvec. Bad wally. - ######## - - # Code for handling traps in different modes - # Some comments are inside of the below strings (prefixed with a #, as you might expected) - lines += f""" - # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode - li x30, 0 - - # Set up - la x1, _j_m_trap_{returningInstruction} - #addi x1, 1 - csrw mtvec, x1 - la x1, _j_s_trap_{returningInstruction} - csrw stvec, x1 - la x1, _j_u_trap_{returningInstruction} - # csrw utvec, x1 # user mode traps are not supported - - # Start the tests! - j _j_t_begin_{returningInstruction} - - # Machine mode traps - _j_m_trap_{returningInstruction}: - {beforeCode} - - _j_m_trap_end_{returningInstruction}: - {testJumpCode} - - csrrs x20, mepc, x0 - addi x20, x20, 4 - csrrw x0, mepc, x20 - bnez x30, _j_all_end_{returningInstruction} - mret - - # Supervisor mode traps - _j_s_trap_{returningInstruction}: - {testJumpCode if testMode == "s" else "li x25, 0xBAD00001"} - - csrrs x20, sepc, x0 - addi x20, x20, 4 - csrrw x0, sepc, x20 - bnez x30, _j_goto_machine_mode_{returningInstruction} - sret - - # Unused: user mode traps are no longer supported - _j_u_trap_{returningInstruction}: - {testJumpCode if testMode == "u" else "li x25, 0xBAD00000"} - - csrrs x20, uepc, x0 - addi x20, x20, 4 - csrrw x0, uepc, x20 - bnez x30, _j_goto_supervisor_mode_{returningInstruction} - uret - - # Currently unused. Just jumps to _j_goto_machine_mode. If you actually - # want to implement this, you'll likely need to reset sedeleg here - # and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong) - _j_goto_supervisor_mode_{returningInstruction}: - j _j_goto_machine_mode_{returningInstruction} - - _j_goto_machine_mode_{returningInstruction}: - li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking... - {returningInstruction} # ... this instruction! - - # Run the actual tests! - _j_t_begin_{returningInstruction}: - """ - - fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"]) - - # We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting - # back to machine mode at the end! (and we need to be in machine mode to complete the tests) - medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111" - - # Set medeleg and mideleg - lines += f""" - csrr x18, medeleg - li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"} - csrw medeleg, x9 - - csrr x16, mideleg - li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"} - csrw mideleg, x9 - """ - - f.write(lines) - - for fromMode in fromModeOptions: - lines = "" - - # Code to bring us down to supervisor mode - if fromMode == "s" or fromMode == "u": + # Not used — user mode traps are deprecated + if testMode == "u": lines += f""" - li x1, 0b110000000000 - csrrc x28, mstatus, x1 - li x1, 0b0100000000000 - csrrs x28, mstatus, x1 + csrr x17, sedeleg + li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"} + csrs sedeleg, x9 + """ - auipc x1, 0 - addi x1, x1, 16 # x1 is now right after the mret instruction - csrw mepc, x1 - mret + # Code that will jump to the test (x28 is set in writeTest above) + testJumpCode = f""" + auipc x27, 0 + addi x27, x27, 12 + jr x28 + """ - # We're now in supervisor mode... - """ + beforeCode = {"m": "", "s": ""} + for pm in ["m", "s"]: + for i in range(0, 16): + beforeCode[pm] = beforeCode[pm] + f""" + nop + nop + li x25, {i} + j _j_{pm}_trap_end_{returningInstruction}_{vectoredInterrupts} + """ - # Code to bring us down to user mode - if fromMode == "u": - lines += f""" + # Code for handling traps in different modes + # Some comments are inside of the below strings (prefixed with a #, as you might expected) + enableVectored = "addi x1, x1, 1" if vectoredInterrupts else "" - li x1, 0b110000000000 - csrrc x28, sstatus, x1 + lines += f""" + # Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode + li x30, 0 - auipc x1, 0 - addi x1, x1, 16 # x1 is now right after the sret instruction - csrw sepc, x1 + # Set up + la x1, _j_m_trap_{returningInstruction}_{vectoredInterrupts} + {enableVectored} # enable/don't enable vectored interrupts + csrw mtvec, x1 + la x1, _j_s_trap_{returningInstruction}_{vectoredInterrupts} + {enableVectored} # enable/don't enable vectored interrupts + csrw stvec, x1 + la x1, _j_u_trap_{returningInstruction}_{vectoredInterrupts} + {enableVectored} # enable/don't enable vectored interrupts + # csrw utvec, x1 # user mode traps are not supported + + # Start the tests! + j _j_t_begin_{returningInstruction}_{vectoredInterrupts} + + # Machine mode traps + _j_m_trap_{returningInstruction}_{vectoredInterrupts}: + {beforeCode['m']} + + _j_m_trap_end_{returningInstruction}_{vectoredInterrupts}: + {testJumpCode} + + csrrs x20, mepc, x0 + addi x20, x20, 4 + csrrw x0, mepc, x20 + bnez x30, _j_all_end_{returningInstruction}_{vectoredInterrupts} + mret + + # Supervisor mode traps + _j_s_trap_{returningInstruction}_{vectoredInterrupts}: + {beforeCode['s']} + + _j_s_trap_end_{returningInstruction}_{vectoredInterrupts}: + {testJumpCode} + + csrrs x20, sepc, x0 + addi x20, x20, 4 + csrrw x0, sepc, x20 + bnez x30, _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts} sret - # We're now in user mode... - """ + # Unused: user mode traps are no longer supported + _j_u_trap_{returningInstruction}_{vectoredInterrupts}: + {testJumpCode if testMode == "u" else "li x25, 0xBAD00000"} + + csrrs x20, uepc, x0 + addi x20, x20, 4 + csrrw x0, uepc, x20 + bnez x30, _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts} + uret + + # Currently unused. Just jumps to _j_goto_machine_mode. If you actually + # want to implement this, you'll likely need to reset sedeleg here + # and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong) + _j_goto_supervisor_mode_{returningInstruction}_{vectoredInterrupts}: + j _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts} + + _j_goto_machine_mode_{returningInstruction}_{vectoredInterrupts}: + li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction}_{vectoredInterrupts} in the machine trap handler, which we'll get into by invoking... + {returningInstruction} # ... this instruction! + + # Run the actual tests! + _j_t_begin_{returningInstruction}_{vectoredInterrupts}: + """ + + fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"]) + + # We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting + # back to machine mode at the end! (and we need to be in machine mode to complete the tests) + medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111" + + # Set medeleg and mideleg + lines += f""" + csrr x18, medeleg + li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"} + csrw medeleg, x9 + + csrr x16, mideleg + li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"} + csrw mideleg, x9 + """ f.write(lines) - for i in range(0,testCount): - writeVectors(storecmd, returningInstruction) + + for fromMode in fromModeOptions: + lines = "" + + # Code to bring us down to supervisor mode + if fromMode == "s" or fromMode == "u": + lines += f""" + li x1, 0b110000000000 + csrrc x28, mstatus, x1 + li x1, 0b0100000000000 + csrrs x28, mstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the mret instruction + csrw mepc, x1 + mret + + # We're now in supervisor mode... + """ + + # Code to bring us down to user mode + if fromMode == "u": + lines += f""" + + li x1, 0b110000000000 + csrrc x28, sstatus, x1 + + auipc x1, 0 + addi x1, x1, 16 # x1 is now right after the sret instruction + csrw sepc, x1 + sret + + # We're now in user mode... + """ + + f.write(lines) + for i in range(0,testCount): + writeVectors(storecmd, returningInstruction) - # Very end of test. Bring us back up to machine mode - # We set x30 to 1, which will cause us to branch to _j_all_end in the - # machine mode trap handler, before executing the mret instruction. This will - # make us stay in machine mode. - # - # If we're currently in user mode, this will first bump us up to the supervisor mode - # trap handler, which will call returningInstruction again before it's sret instruction, - # bumping us up to machine mode - # - # Get into the trap handler by running returningInstruction (either an ecall or ebreak) - f.write(f""" - li x30, 1 - li gp, 0 - {returningInstruction} - _j_all_end_{returningInstruction}: + # Very end of test. Bring us back up to machine mode + # We set x30 to 1, which will cause us to branch to _j_all_end in the + # machine mode trap handler, before executing the mret instruction. This will + # make us stay in machine mode. + # + # If we're currently in user mode, this will first bump us up to the supervisor mode + # trap handler, which will call returningInstruction again before it's sret instruction, + # bumping us up to machine mode + # + # Get into the trap handler by running returningInstruction (either an ecall or ebreak) + f.write(f""" + li x30, 1 + li gp, 0 + {returningInstruction} + _j_all_end_{returningInstruction}_{vectoredInterrupts}: - # Reset trap handling csrs to old values - csrw mtvec, x19 - csrw medeleg, x18 - csrw mideleg, x16 - """) + # Reset trap handling csrs to old values + csrw mtvec, x19 + csrw medeleg, x18 + csrw mideleg, x16 + """) # print footer h = open("../testgen_footer.S", "r") @@ -450,8 +471,3 @@ for xlen in xlens: f.write(lines) f.close() r.close() - - - - - From 353d4e9238b0fd4c3027b84deebfc6f36d292b83 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Mon, 3 May 2021 22:38:26 -0400 Subject: [PATCH 18/20] Update cause tests to be longer --- wally-pipelined/testbench/testbench-imperas.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index e08768425..4ad3b96d9 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -348,8 +348,8 @@ module testbench(); }; string tests64p[] = '{ - "rv64p/WALLY-MCAUSE", "2000", - "rv64p/WALLY-SCAUSE", "2000", + "rv64p/WALLY-MCAUSE", "4000", + "rv64p/WALLY-SCAUSE", "3000", "rv64p/WALLY-MEPC", "5000", "rv64p/WALLY-SEPC", "4000", "rv64p/WALLY-MTVAL", "6000", @@ -363,8 +363,8 @@ module testbench(); }; string tests32p[] = '{ - // "rv32p/WALLY-MCAUSE", "2000", - // "rv32p/WALLY-SCAUSE", "2000", + // "rv32p/WALLY-MCAUSE", "4000", + // "rv32p/WALLY-SCAUSE", "3000", // "rv32p/WALLY-MEPC", "5000", // "rv32p/WALLY-SEPC", "4000", // "rv32p/WALLY-MTVAL", "5000", @@ -423,7 +423,7 @@ module testbench(); end //tests = {tests64a, tests}; - //tests = tests64p; + tests = tests64p; end else begin // RV32 // *** add the 32 bit bp tests if (TESTSPERIPH) begin From 12d8ff617b320bc714518cca984e595ceda9f310 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Mon, 3 May 2021 22:38:59 -0400 Subject: [PATCH 19/20] Run all tests --- wally-pipelined/testbench/testbench-imperas.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 4ad3b96d9..18539fda6 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -423,7 +423,7 @@ module testbench(); end //tests = {tests64a, tests}; - tests = tests64p; + //tests = tests64p; end else begin // RV32 // *** add the 32 bit bp tests if (TESTSPERIPH) begin From a7e89f43c10c62a6d5e78e002ab75a3fbec08665 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Mon, 3 May 2021 22:48:03 -0400 Subject: [PATCH 20/20] Fix bug with IllegalInstrFaultM not getting correct value --- wally-pipelined/src/privileged/privdec.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/privileged/privdec.sv b/wally-pipelined/src/privileged/privdec.sv index 59ff536df..5e3581ff8 100644 --- a/wally-pipelined/src/privileged/privdec.sv +++ b/wally-pipelined/src/privileged/privdec.sv @@ -47,7 +47,7 @@ module privdec ( assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); - assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | IllegalFPUInstrM; // *** generalize this for other instructions + assign IllegalInstrFaultM = IllegalIEUInstrFaultM | IllegalFPUInstrM | IllegalPrivilegedInstrM | IllegalCSRAccessM | IllegalFPUInstrM; // *** generalize this for other instructions // *** initially, wfi and sfencevma are nop // *** zfenci extension?