diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 39975aa4b..4a1b00b57 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -52,7 +52,7 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( // AHB-Lite external signals output logic HCLK, HRESETn, input logic HREADY, // AHB peripheral ready - input logic HRESP, // AHB peripheral response. 0: OK 1: Error + input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored. output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index bdc61f784..a9e187205 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -41,7 +41,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision input logic [6:0] OpD, // bits 6:0 of instruction input logic [4:0] Rs2D, // bits 24:20 of instruction - input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode + input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode // input mux selections output logic XEnD, YEnD, ZEnD, // enable inputs output logic XEnE, YEnE, ZEnE, // enable inputs diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index cf243a84b..bbb2d9360 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -30,8 +30,7 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) ( input logic [P.FMTBITS-1:0] Fmt, input logic [P.NE-1:0] Xe, Ye, // input exponents input logic Sqrt, - input logic XZero, - input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye + input logic [P.DIVBLEN-1:0] ell, m, // number of leading 0s in Xe and Ye output logic [P.NE+1:0] Ue // result exponent ); diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 145bf9a68..939b9c133 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -210,7 +210,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D); // Floating-point exponent - fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Ue(UeE)); + fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .ell, .m(mE), .Ue(UeE)); flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM); // Number of FSM cycles (to FSM) diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index ffd9cf49a..7d7574a45 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -167,7 +167,7 @@ module fpu import cvw::*; #(parameter cvw_t P) ( // calculate FP control signals fctrl #(P) fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), - .Funct3E, .IntDivE, .InstrD, + .IntDivE, .InstrD, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE, .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM, diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 12bd83bc5..0bea0a5d0 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -32,7 +32,6 @@ module hazard import cvw::*; #(parameter cvw_t P) ( input logic LSUStallM, IFUStallF, input logic FCvtIntStallD, FPUStallD, input logic DivBusyE, FDivBusyE, - input logic EcallFaultM, BreakpointFaultM, input logic wfiM, IntPendingM, // Stall & flush outputs output logic StallF, StallD, StallE, StallM, StallW, diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 55946a411..4c203b1a7 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -45,7 +45,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) ( logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux - logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic Asign, Bsign; // Sign bits of A, B diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 32fdba23e..a489b7f86 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -103,7 +103,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic BaseRegWriteD; // Indicates if Base instruction register write instruction logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu logic BaseALUSrcBD; // Base instruction ALU B source select signal - logic [2:0] ALUControlD; // Determines ALU operation logic ALUSrcAD, ALUSrcBD; // ALU inputs logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR @@ -118,7 +117,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions - logic ALUOpE; // 0 for address generationm 1 for ALU operations logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 2fa8c96d7..831d9e6bb 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -33,7 +33,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( // Command from CPU input logic InvalidateICacheM, // Clears all instruction cache valid bits input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE) - input logic InstrValidD, InstrValidE, InstrValidM, + input logic InstrValidD, InstrValidE, input logic BranchD, BranchE, input logic JumpD, JumpE, // Bus interface @@ -103,7 +103,6 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed) logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed) logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill - logic [P.XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j) logic [P.XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F logic [P.XLEN-1:0] PCD; // Decode stage instruction address logic [P.XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence @@ -228,7 +227,6 @@ module ifu import cvw::*; #(parameter cvw_t P) ( logic [P.PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; logic [1:0] CacheBusRW, BusRW, CacheRWF; - logic [1:0] CacheBusRWTemp; assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index bb5a0bca8..396fa1515 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -40,7 +40,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input logic [1:0] AtomicM, // Atomic memory operation input logic FlushDCacheM, // Flush D cache to next level of memory input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero - input logic LSUPrefetchM, // Prefetch + input logic LSUPrefetchM, // Prefetch; presently unused output logic CommittedM, // Delay interrupts while memory operation in flight output logic SquashSCW, // Store conditional failed disable write to GPR output logic DCacheMiss, // D cache miss for performance counters diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 7b590c077..79beb4410 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -38,8 +38,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU input logic CSRReadM, CSRWriteM, // read or write CSR input logic TrapM, // trap is occurring - input logic mretM, sretM, wfiM, // return or WFI instruction - input logic IntPendingM, // at least one interrupt is pending and could occur if enabled + input logic mretM, sretM, // return instruction input logic InterruptM, // interrupt is occurring input logic ExceptionM, // interrupt is occurring input logic MTimerInt, // timer interrupt @@ -248,7 +247,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( csrs #(P) csrs(.clk, .reset, .CSRSWriteM, .STrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, - .STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]), + .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index fa329f363..3d914aef3 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -35,7 +35,6 @@ module csrs import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, input logic [4:0] NextCauseM, input logic STATUS_TVM, - input logic MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear input logic [P.XLEN-1:0] CSRWriteValM, input logic [1:0] PrivilegeModeW, output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW, diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index eb17b8d04..9a4027571 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -29,7 +29,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, - input logic StallM, StallW, FlushW, + input logic StallW, FlushW, input logic [31:15] InstrM, // privileged instruction function field input logic PrivilegedM, // is this a privileged instruction (from IEU controller) input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index d777e0bf9..9d2ba3788 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -93,7 +93,6 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic InvalidateICacheM, // fence instruction output logic BigEndianM, // Use big endian in current privilege mode // Fault outputs - output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout ); @@ -114,6 +113,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( logic InterruptM; // interrupt occuring logic ExceptionM; // Memory stage instruction caused a fault logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE + logic BreakpointFaultM, EcallFaultM; // breakpoint and Ecall traps should retire logic wfiW; @@ -122,7 +122,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); // decode privileged instructions - privdec #(P) pmd(.clk, .reset, .StallM, .StallW, .FlushW, .InstrM(InstrM[31:15]), + privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]), .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM); @@ -130,7 +130,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( // Control and Status Registers csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW, .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF, - .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, + .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM, diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index b0649bf93..626487f91 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -68,11 +68,10 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1] logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark; logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty; - logic TransmitFIFOReadIncrement; logic TransmitFIFOWriteIncrement; logic ReceiveFIFOReadIncrement; logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty; - logic [7:0] TransmitFIFOReadData, ReceiveFIFOWriteData; + logic [7:0] TransmitFIFOReadData; logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission) @@ -92,7 +91,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Frame counting signals logic [3:0] FrameCount; // Counter for number of frames in transmission - logic [3:0] ReceivePenultimateFrameCount; // Counter logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached // State fsm signals diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 46ffcac09..071ecbea2 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -158,7 +158,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic DCacheAccess; logic ICacheMiss; logic ICacheAccess; - logic BreakpointFaultM, EcallFaultM; logic InstrUpdateDAF; logic BigEndianM; logic FCvtIntE; @@ -170,7 +169,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( // instruction fetch unit: PC, branch prediction, instruction cache ifu #(P) ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .InstrValidM, .InstrValidE, .InstrValidD, + .InstrValidE, .InstrValidD, .BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF, // Fetch .HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF, @@ -270,7 +269,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .LSUStallM, .IFUStallF, .FCvtIntStallD, .FPUStallD, .DivBusyE, .FDivBusyE, - .EcallFaultM, .BreakpointFaultM, .wfiM, .IntPendingM, // Stall & flush outputs .StallF, .StallD, .StallE, .StallM, .StallW, @@ -298,7 +296,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM); + .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_HADE, .wfiM, .IntPendingM, .BigEndianM); end else begin assign CSRReadValW = 0; assign UnalignedPCNextF = PC2NextF;