Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals

Browse Source
This commit is contained in:
David Harris 2021-06-20 22:59:04 -04:00
parent 23f479d225
commit d2ec04564b
3 changed files with 35 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
wally-pipelined/config/shared/wally-constants.vh
View File

@ -37,7 +37,6 @@
// Virtual Memory Constants // Virtual Memory Constants
`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) `define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) `define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
`define PPN_HIGH_SEGMENT_BITS (`XLEN==32 ? 12 : 17)
`define PPN_BITS (`XLEN==32 ? 22 : 44) `define PPN_BITS (`XLEN==32 ? 22 : 44)
`define PA_BITS (`XLEN==32 ? 34 : 56) `define PA_BITS (`XLEN==32 ? 34 : 56)
`define SVMODE_BITS (`XLEN == 32 ? 1 : 4) `define SVMODE_BITS (`XLEN == 32 ? 1 : 4)

10
wally-pipelined/src/privileged/csru.sv
View File

@ -46,17 +46,17 @@ module csru #(parameter
generate generate
if (`F_SUPPORTED | `D_SUPPORTED) begin if (`F_SUPPORTED | `D_SUPPORTED) begin
logic [4:0] FFLAGS_REGW; logic [4:0] FFLAGS_REGW;
logic WriteFFLAGSM, WriteFRMM, WriteFCSRM; logic WriteFFLAGSM, WriteFRMM; //, WriteFCSRM;
logic [2:0] NextFRMM; logic [2:0] NextFRMM;
logic [4:0] NextFFLAGSM; logic [4:0] NextFFLAGSM;
// Write enables // Write enables
assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR) && ~StallW; //assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR) && ~StallW;
assign WriteFFLAGSM = (CSRUWriteM && (CSRAdrM == FFLAGS) | WriteFCSRM) && ~StallW; assign WriteFRMM = (CSRUWriteM && (CSRAdrM == FRM | CSRAdrM == FCSR)) && ~StallW;
assign WriteFRMM = (CSRUWriteM && (CSRAdrM == FRM) | WriteFCSRM) && ~StallW; assign WriteFFLAGSM = (CSRUWriteM && (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) && ~StallW;
// Write Values // Write Values
assign NextFRMM = WriteFCSRM ? CSRWriteValM[7:5] : CSRWriteValM[2:0]; assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM; assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM;
// CSRs // CSRs

40
wally-pipelined/src/uncore/uncore.sv
View File

@ -79,17 +79,37 @@ module uncore (
// subword accesses: converts HWDATAIN to HWDATA // subword accesses: converts HWDATAIN to HWDATA
subwordwrite sww(.*); subwordwrite sww(.*);
// tightly integrated memory generate
dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*); // tightly integrated memory
dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
//if (`BOOTTIM_SUPPORTED) *** restore when naming is figured out
dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
// memory-mapped I/O peripherals // memory-mapped I/O peripherals
clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*); if (`CLINT_SUPPORTED == 1)
plic plic(.HADDR(HADDR[27:0]), .*); clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*);
gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts else begin
uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0;
.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), assign TimerIntM = 0; assign SwIntM = 0;
.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); end
if (`PLIC_SUPPORTED == 1)
plic plic(.HADDR(HADDR[27:0]), .*);
else begin
assign ExtIntM = 0;
end
if (`GPIO_SUPPORTED == 1)
gpio gpio(.HADDR(HADDR[7:0]), .*);
else begin
assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
end
if (`UART_SUPPORTED == 1)
uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1),
.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
else begin
assign UARTSout = 0; assign UARTIntr = 0;
end
endgenerate
// mux could also include external memory // mux could also include external memory
// AHB Read Multiplexer // AHB Read Multiplexer