diff --git a/wally-pipelined/config/shared/wally-constants.vh b/wally-pipelined/config/shared/wally-constants.vh
index 35f568e1e..706997b93 100644
--- a/wally-pipelined/config/shared/wally-constants.vh
+++ b/wally-pipelined/config/shared/wally-constants.vh
@@ -37,7 +37,6 @@
 // Virtual Memory Constants
 `define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9)
 `define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS))
-`define PPN_HIGH_SEGMENT_BITS (`XLEN==32 ? 12 : 17)
 `define PPN_BITS (`XLEN==32 ? 22 : 44)
 `define PA_BITS (`XLEN==32 ? 34 : 56)
 `define SVMODE_BITS (`XLEN == 32 ? 1 : 4)
diff --git a/wally-pipelined/src/privileged/csru.sv b/wally-pipelined/src/privileged/csru.sv
index aea1d398f..2e48731da 100644
--- a/wally-pipelined/src/privileged/csru.sv
+++ b/wally-pipelined/src/privileged/csru.sv
@@ -46,17 +46,17 @@ module csru #(parameter
   generate  
     if (`F_SUPPORTED | `D_SUPPORTED) begin
       logic [4:0] FFLAGS_REGW;
-      logic WriteFFLAGSM, WriteFRMM, WriteFCSRM;
+      logic WriteFFLAGSM, WriteFRMM; //, WriteFCSRM;
       logic [2:0] NextFRMM;
       logic [4:0] NextFFLAGSM;
         
       // Write enables
-      assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR)  && ~StallW;
-      assign WriteFFLAGSM = (CSRUWriteM && (CSRAdrM == FFLAGS) | WriteFCSRM)  && ~StallW;
-      assign WriteFRMM = (CSRUWriteM && (CSRAdrM == FRM) | WriteFCSRM)  && ~StallW;
+      //assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR)  && ~StallW;
+      assign WriteFRMM = (CSRUWriteM && (CSRAdrM == FRM | CSRAdrM == FCSR))  && ~StallW;
+      assign WriteFFLAGSM = (CSRUWriteM && (CSRAdrM == FFLAGS | CSRAdrM == FCSR))  && ~StallW;
     
       // Write Values
-      assign NextFRMM = WriteFCSRM ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
+      assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
       assign NextFFLAGSM = WriteFFLAGSM ? CSRWriteValM[4:0] : FFLAGS_REGW | SetFflagsM;
 
       // CSRs
diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index d49414a79..a100d76f9 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -79,17 +79,37 @@ module uncore (
   // subword accesses: converts HWDATAIN to HWDATA
   subwordwrite sww(.*);
 
-  // tightly integrated memory
-  dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
-  dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
+  generate
+    // tightly integrated memory
+    dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
+    //if (`BOOTTIM_SUPPORTED) *** restore when naming is figured out
+      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
 
-  // memory-mapped I/O peripherals
-  clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*);
-  plic plic(.HADDR(HADDR[27:0]), .*);
-  gpio gpio(.HADDR(HADDR[7:0]), .*); // *** may want to add GPIO interrupts
-  uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
-            .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), 
-            .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
+    // memory-mapped I/O peripherals
+    if (`CLINT_SUPPORTED == 1)
+      clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*);
+    else begin
+      assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0;
+      assign TimerIntM = 0; assign SwIntM = 0;
+    end
+    if (`PLIC_SUPPORTED == 1)
+      plic plic(.HADDR(HADDR[27:0]), .*);
+    else begin
+      assign ExtIntM = 0;
+    end
+    if (`GPIO_SUPPORTED == 1)
+      gpio gpio(.HADDR(HADDR[7:0]), .*); 
+    else begin
+      assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
+    end
+    if (`UART_SUPPORTED == 1)
+      uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
+                .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), 
+                .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
+    else begin
+      assign UARTSout = 0; assign UARTIntr = 0; 
+    end
+  endgenerate
 
   // mux could also include external memory  
   // AHB Read Multiplexer