Update dtim.sv

Program clean up

src/lsu/dtim.sv

@@ -28,17 +28,17 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module dtim import cvw::*;  #(parameter cvw_t P) (
-  input logic                clk, 
+  input logic                 clk, 
-  input logic                FlushW,        
+  input logic                 FlushW,        
-  input logic                ce,            // Chip Enable.  0: Holds ReadDataWordM
+  input logic                 ce,            // Chip Enable.  0: Holds ReadDataWordM
-  input logic [1:0]          MemRWM,        // Read/Write control
+  input logic [1:0]           MemRWM,        // Read/Write control
   input logic [P.PA_BITS-1:0] DTIMAdr,       // No stall: Execution stage memory address. Stall: Memory stage memory address
   input logic [P.LLEN-1:0]    WriteDataM,    // Write data from IEU
   input logic [P.LLEN/8-1:0]  ByteMaskM,     // Selects which bytes within a word to write
   output logic [P.LLEN-1:0]   ReadDataWordM  // Read data before subword selection
   );
 
-  logic                      we;
+  logic                       we;
  
   localparam LLENBYTES  = P.LLEN/8;
   // verilator  lint_off WIDTH 
@@ -52,4 +52,3 @@ module dtim import cvw::*;  #(parameter cvw_t P) (
   ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(P.LLEN)) 
     ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
-