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fix scanning when XLEN != FLEN

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Matthew 2024-06-12 22:41:48 -05:00
parent 61eba041e4
commit d21e5b1fca
3 changed files with 13 additions and 15 deletions
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5
bin/hw_debug_test.py
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@ -33,6 +33,7 @@ import time
from openocd_tcl_wrapper import OpenOCD from openocd_tcl_wrapper import OpenOCD
random_stimulus = True random_stimulus = True
random_order = False
def main(): def main():
with OpenOCD() as cvw: with OpenOCD() as cvw:
@ -67,7 +68,7 @@ def main():
# Write random data to all registers # Write random data to all registers
reg_addrs = list(registers.keys()) reg_addrs = list(registers.keys())
if random_stimulus: if random_order:
random.shuffle(reg_addrs) random.shuffle(reg_addrs)
test_reg_data = {} test_reg_data = {}
for r in reg_addrs: for r in reg_addrs:
@ -88,7 +89,7 @@ def main():
# Confirm data was written correctly # Confirm data was written correctly
reg_addrs = list(registers.keys()) reg_addrs = list(registers.keys())
if random_stimulus: if random_order:
random.shuffle(reg_addrs) random.shuffle(reg_addrs)
for r in reg_addrs: for r in reg_addrs:
try: try:

6
src/debug/dm.sv
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@ -123,6 +123,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
logic [9:0] Cycle; // DM's current position in the scan chain logic [9:0] Cycle; // DM's current position in the scan chain
logic InvalidRegNo; // Requested RegNo is invalid logic InvalidRegNo; // Requested RegNo is invalid
logic RegReadOnly; // Current RegNo points to a readonly register logic RegReadOnly; // Current RegNo points to a readonly register
logic MiscRegNo; // Requested RegNo is on the Misc scan chain
logic GPRegNo; // Requested RegNo is a GPR logic GPRegNo; // Requested RegNo is a GPR
logic FPRegNo; // Requested RegNo is a FPR logic FPRegNo; // Requested RegNo is a FPR
logic CSRegNo; // Requested RegNo is a CSR logic CSRegNo; // Requested RegNo is a CSR
@ -427,7 +428,8 @@ module dm import cvw::*; #(parameter cvw_t P) (
assign DebugCapture = (AcState == AC_CAPTURE); assign DebugCapture = (AcState == AC_CAPTURE);
assign DebugRegUpdate = (AcState == AC_UPDATE); assign DebugRegUpdate = (AcState == AC_UPDATE);
assign MiscSel = ~(CSRegNo | GPRegNo | FPRegNo) & (AcState != AC_IDLE); assign MiscRegNo = ~(CSRegNo | GPRegNo | FPRegNo);
assign MiscSel = MiscRegNo & (AcState != AC_IDLE);
assign CSRSel = CSRegNo & (AcState != AC_IDLE); assign CSRSel = CSRegNo & (AcState != AC_IDLE);
assign GPRSel = GPRegNo & (AcState != AC_IDLE); assign GPRSel = GPRegNo & (AcState != AC_IDLE);
assign FPRSel = FPRegNo & (AcState != AC_IDLE); assign FPRSel = FPRegNo & (AcState != AC_IDLE);
@ -451,7 +453,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
assign PackedDataReg = {Data3,Data2,Data1,Data0}; assign PackedDataReg = {Data3,Data2,Data1,Data0};
// Load data from message registers into scan chain // Load data from message registers into scan chain
assign WriteScanReg = AcWrite & (~(GPRegNo | FPRegNo) & (Cycle == ShiftCount) | (GPRegNo | FPRegNo) & (Cycle == 0)); assign WriteScanReg = AcWrite & (MiscRegNo & (Cycle == ShiftCount) | ~MiscRegNo & (Cycle == 0));
genvar i; genvar i;
for (i=0; i<P.LLEN; i=i+1) begin for (i=0; i<P.LLEN; i=i+1) begin
// ARMask is used as write enable for subword overwrites (basic mask would overwrite neighbors in the chain) // ARMask is used as write enable for subword overwrites (basic mask would overwrite neighbors in the chain)

17
src/debug/rad.sv
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@ -77,7 +77,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
FPRegNo = 0; FPRegNo = 0;
case (Regno) inside case (Regno) inside
[`FFLAGS_REGNO:`FCSR_REGNO], [`FFLAGS_REGNO:`FCSR_REGNO],
[`MSTATUS_REGNO:`MCOUNTEREN_REGNO], [`MSTATUS_REGNO:`MCOUNTEREN_REGNO], // InvalidRegNo = ~P.ZICSR_SUPPORTED;
`MENVCFG_REGNO, `MENVCFG_REGNO,
`MSTATUSH_REGNO, `MSTATUSH_REGNO,
`MENVCFGH_REGNO, `MENVCFGH_REGNO,
@ -104,7 +104,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
`SIP_REGNO, `SIP_REGNO,
`MIE_REGNO, `MIE_REGNO,
`MIP_REGNO : begin `MIP_REGNO : begin
ShiftCount = P.XLEN - 1; ShiftCount = P.LLEN - 1;
CSRegNo = 1; CSRegNo = 1;
RegReadOnly = 1; // TODO: eventually DCSR (any maybe others) will be RW RegReadOnly = 1; // TODO: eventually DCSR (any maybe others) will be RW
end end
@ -112,30 +112,25 @@ module rad import cvw::*; #(parameter cvw_t P) (
[`HPMCOUNTERBASE_REGNO:`TIME_REGNO], [`HPMCOUNTERBASE_REGNO:`TIME_REGNO],
[`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO], [`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO],
[`MVENDORID_REGNO:`MCONFIGPTR_REGNO] : begin [`MVENDORID_REGNO:`MCONFIGPTR_REGNO] : begin
ShiftCount = P.XLEN - 1; ShiftCount = P.LLEN - 1;
CSRegNo = 1; CSRegNo = 1;
RegReadOnly = 1; RegReadOnly = 1;
end end
[`X0_REGNO:`X15_REGNO] : begin [`X0_REGNO:`X15_REGNO] : begin
ShiftCount = P.XLEN - 1; ShiftCount = P.LLEN - 1;
GPRegNo = 1; GPRegNo = 1;
end end
[`X16_REGNO:`X31_REGNO] : begin [`X16_REGNO:`X31_REGNO] : begin
ShiftCount = P.XLEN - 1; ShiftCount = P.LLEN - 1;
InvalidRegNo = P.E_SUPPORTED; InvalidRegNo = P.E_SUPPORTED;
GPRegNo = 1; GPRegNo = 1;
end end
[`FP0_REGNO:`FP31_REGNO] : begin [`FP0_REGNO:`FP31_REGNO] : begin
ShiftCount = P.FLEN - 1; ShiftCount = P.LLEN - 1;
InvalidRegNo = ~(P.F_SUPPORTED | P.D_SUPPORTED | P.Q_SUPPORTED); InvalidRegNo = ~(P.F_SUPPORTED | P.D_SUPPORTED | P.Q_SUPPORTED);
FPRegNo = 1; FPRegNo = 1;
end end
//`MISA_REGNO : begin
// ShiftCount = SCANCHAINLEN - MISA_IDX;
// InvalidRegNo = ~P.ZICSR_SUPPORTED;
// RegReadOnly = 1;
//end
`TRAPM_REGNO : begin `TRAPM_REGNO : begin
ShiftCount = SCANCHAINLEN - TRAPM_IDX; ShiftCount = SCANCHAINLEN - TRAPM_IDX;
InvalidRegNo = ~P.ZICSR_SUPPORTED; InvalidRegNo = ~P.ZICSR_SUPPORTED;