From d21e5b1fcaac7ff7d9d62df06c800dd984434d1e Mon Sep 17 00:00:00 2001
From: Matthew <106996253+Matthew-Otto@users.noreply.github.com>
Date: Wed, 12 Jun 2024 22:41:48 -0500
Subject: [PATCH] fix scanning when XLEN != FLEN

---
 bin/hw_debug_test.py |  5 +++--
 src/debug/dm.sv      |  6 ++++--
 src/debug/rad.sv     | 17 ++++++-----------
 3 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/bin/hw_debug_test.py b/bin/hw_debug_test.py
index cc4021195..f7aad2938 100755
--- a/bin/hw_debug_test.py
+++ b/bin/hw_debug_test.py
@@ -33,6 +33,7 @@ import time
 from openocd_tcl_wrapper import OpenOCD
 
 random_stimulus = True
+random_order = False
 
 def main():
     with OpenOCD() as cvw:
@@ -67,7 +68,7 @@ def main():
 
         # Write random data to all registers
         reg_addrs = list(registers.keys())
-        if random_stimulus:
+        if random_order:
             random.shuffle(reg_addrs)
         test_reg_data = {}
         for r in reg_addrs:
@@ -88,7 +89,7 @@ def main():
 
         # Confirm data was written correctly
         reg_addrs = list(registers.keys())
-        if random_stimulus:
+        if random_order:
             random.shuffle(reg_addrs)
         for r in reg_addrs:
             try:
diff --git a/src/debug/dm.sv b/src/debug/dm.sv
index b6c339fc8..47d61a10c 100644
--- a/src/debug/dm.sv
+++ b/src/debug/dm.sv
@@ -123,6 +123,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
   logic [9:0]        Cycle;          // DM's current position in the scan chain
   logic              InvalidRegNo;   // Requested RegNo is invalid
   logic              RegReadOnly;    // Current RegNo points to a readonly register
+  logic              MiscRegNo;      // Requested RegNo is on the Misc scan chain
   logic              GPRegNo;        // Requested RegNo is a GPR
   logic              FPRegNo;        // Requested RegNo is a FPR
   logic              CSRegNo;        // Requested RegNo is a CSR
@@ -427,7 +428,8 @@ module dm import cvw::*; #(parameter cvw_t P) (
   assign DebugCapture = (AcState == AC_CAPTURE);
   assign DebugRegUpdate = (AcState == AC_UPDATE);
 
-  assign MiscSel = ~(CSRegNo | GPRegNo | FPRegNo) & (AcState != AC_IDLE);
+  assign MiscRegNo = ~(CSRegNo | GPRegNo | FPRegNo);
+  assign MiscSel = MiscRegNo & (AcState != AC_IDLE);
   assign CSRSel = CSRegNo & (AcState != AC_IDLE);
   assign GPRSel = GPRegNo & (AcState != AC_IDLE);
   assign FPRSel = FPRegNo & (AcState != AC_IDLE);
@@ -451,7 +453,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
     assign PackedDataReg = {Data3,Data2,Data1,Data0};
       
   // Load data from message registers into scan chain
-  assign WriteScanReg = AcWrite & (~(GPRegNo | FPRegNo) & (Cycle == ShiftCount) | (GPRegNo | FPRegNo) & (Cycle == 0));
+  assign WriteScanReg = AcWrite & (MiscRegNo & (Cycle == ShiftCount) | ~MiscRegNo & (Cycle == 0));
   genvar i;
   for (i=0; i<P.LLEN; i=i+1) begin
     // ARMask is used as write enable for subword overwrites (basic mask would overwrite neighbors in the chain)
diff --git a/src/debug/rad.sv b/src/debug/rad.sv
index 8463ae132..58175f68e 100644
--- a/src/debug/rad.sv
+++ b/src/debug/rad.sv
@@ -77,7 +77,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
     FPRegNo = 0;
     case (Regno) inside
       [`FFLAGS_REGNO:`FCSR_REGNO],
-      [`MSTATUS_REGNO:`MCOUNTEREN_REGNO],
+      [`MSTATUS_REGNO:`MCOUNTEREN_REGNO], //  InvalidRegNo = ~P.ZICSR_SUPPORTED;
       `MENVCFG_REGNO,
       `MSTATUSH_REGNO,
       `MENVCFGH_REGNO,
@@ -104,7 +104,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
       `SIP_REGNO,
       `MIE_REGNO,
       `MIP_REGNO : begin
-        ShiftCount = P.XLEN - 1;
+        ShiftCount = P.LLEN - 1;
         CSRegNo = 1;
         RegReadOnly = 1; // TODO: eventually DCSR (any maybe others) will be RW
       end
@@ -112,30 +112,25 @@ module rad import cvw::*; #(parameter cvw_t P) (
       [`HPMCOUNTERBASE_REGNO:`TIME_REGNO],
       [`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO],
       [`MVENDORID_REGNO:`MCONFIGPTR_REGNO] : begin
-        ShiftCount = P.XLEN - 1;
+        ShiftCount = P.LLEN - 1;
         CSRegNo = 1;
         RegReadOnly = 1;
       end
 
       [`X0_REGNO:`X15_REGNO] : begin
-        ShiftCount = P.XLEN - 1;
+        ShiftCount = P.LLEN - 1;
         GPRegNo = 1;
       end
       [`X16_REGNO:`X31_REGNO] : begin
-        ShiftCount = P.XLEN - 1;
+        ShiftCount = P.LLEN - 1;
         InvalidRegNo = P.E_SUPPORTED;
         GPRegNo = 1;
       end
       [`FP0_REGNO:`FP31_REGNO] : begin
-        ShiftCount = P.FLEN - 1;
+        ShiftCount = P.LLEN - 1;
         InvalidRegNo = ~(P.F_SUPPORTED | P.D_SUPPORTED | P.Q_SUPPORTED);
         FPRegNo = 1;
       end
-      //`MISA_REGNO : begin
-      //  ShiftCount = SCANCHAINLEN - MISA_IDX;
-      //  InvalidRegNo = ~P.ZICSR_SUPPORTED;
-      //  RegReadOnly = 1;
-      //end
       `TRAPM_REGNO : begin
         ShiftCount = SCANCHAINLEN - TRAPM_IDX;
         InvalidRegNo = ~P.ZICSR_SUPPORTED;