mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 09:45:18 +00:00
Merge pull request #760 from davidharrishmc/dev
Synthesis and VCS fixes
This commit is contained in:
Rose Thompson
GitHub
commit
d196f8f8af
1
.gitignore
vendored
1
.gitignore
vendored
@ -188,6 +188,7 @@ sim/cfi/*
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sim/branch/*
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sim/obj_dir
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examples/verilog/fulladder/obj_dir
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examples/verilog/fulladder/fulladder.vcd
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config/deriv
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docs/docker/buildroot-config-src
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docs/docker/testvector-generation
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@ -274,6 +274,7 @@ os.chdir(regressionDir)
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coveragesim = "questa" # Questa is required for code/functional coverage
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defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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#defaultsim = "verilator" # Default simulator for all other tests
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coverage = '--coverage' in sys.argv
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fp = '--fp' in sys.argv
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@ -299,9 +300,9 @@ configs = [
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TestCase(
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name="lints",
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variant="all",
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cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log",
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cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/verilator/logs/all_lints.log",
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grepstr="lints run with no errors or warnings",
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grepfile = WALLY + "/sim/questa/logs/all_lints.log")
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grepfile = WALLY + "/sim/verilator/logs/all_lints.log")
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]
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if (coverage): # only run RV64GC tests on Questa in coverage mode
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@ -19,6 +19,8 @@ module testbench();
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// at start of test, load vectors and pulse reset
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initial
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begin
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$dumpfile("fulladder.vcd");
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$dumpvars;
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$readmemb("fulladder.tv", testvectors);
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cycle = 0;
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vectornum = 0; errors = 0;
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@ -47,6 +49,7 @@ module testbench();
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$finish;
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end
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end
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endmodule
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module fulladder(input logic a, b, c,
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@ -1,5 +1,3 @@
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#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
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#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
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#verilator --binary --top-module testbench fulladder.sv
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verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv
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verilator --binary --top-module testbench --trace fulladder.sv
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obj_dir/Vtestbench
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@ -30,6 +30,10 @@ DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
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default: run
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run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
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mkdir -p $(VERILATOR_DIR)/logs
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wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
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profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
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$(VERILATOR_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST)
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mv gmon.out gmon_$(WALLYCONF).out
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@ -39,17 +43,13 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF)
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mv gmon_$(WALLYCONF)* $(VERILATOR_DIR)/logs_profiling
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echo "Please check $(VERILATOR_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files."
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run: wkdir/$(WALLYCONF)_$(TEST)/Vtestbench
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mkdir -p $(VERILATOR_DIR)/logs
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wkdir/$(WALLYCONF)_$(TEST)/Vtestbench +TEST=$(TEST)
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wkdir/$(WALLYCONF)_$(TEST)/Vtestbench: $(DEPENDENCIES)
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verilator \
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--Mdir wkdir/$(WALLYCONF)_$(TEST) -o Vtestbench \
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--binary --trace \
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$(OPT) $(PARAMS) $(NONPROF) \
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$(EXTRA_ARGS) \
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--timescale "1ns/1ns" --timing --top-module testbench --relative-includes \
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--top-module testbench --relative-includes \
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$(INCLUDE_PATH) \
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${WALLY}/sim/verilator/wrapper.c \
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$(SOURCES)
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@ -61,13 +61,10 @@ obj_dir_profiling/Vtestbench_$(WALLYCONF): $(DEPENDENCIES)
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--binary \
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--prof-cfuncs $(OPT) $(PARAMS) \
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$(EXTRA_ARGS) \
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--timescale "1ns/1ns" --timing --top-module testbench --relative-includes \
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--top-module testbench --relative-includes \
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$(INCLUDE_PATH) \
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${WALLY}/sim/verilator/wrapper.c \
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$(SOURCES)
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questa:
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vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)"
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clean:
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rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling
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@ -162,7 +162,9 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt
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logic [P.FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer
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logic mvsgn; // sign bit for extending move
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logic [P.FLEN-1:0] FliResE; // Floating-point load immediate value
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logic [P.FLEN-1:0] FliResE; // Zfa Floating-point load immediate value
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logic [P.FLEN-1:0] FRoundE; // Zfa fround output
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logic [4:0] FRoundFlagsE; // Zfa fround flags
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//////////////////////////////////////////////////////////////////////////////////////////
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// Decode Stage: fctrl decoder, read register file
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@ -267,15 +269,25 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
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.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
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// floating-point load immediate: fli
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// ZFA: fround and floating-point load immediate fli
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if (P.ZFA_SUPPORTED) begin
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logic [4:0] Rs1E;
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logic [1:0] Fmt2E; // Two-bit format field from instruction
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// fround
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fround #(P) fround(.Xs(XsE), .Xe(XeE), .Xm(XmE),
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.XNaN(XNaNE), .XSNaN(XSNaNE), .XZero(XZeroE), .Fmt(FmtE),
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.FRound(FRoundE), .FRoundFlags(FRoundFlagsE));
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// fli
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flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
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flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
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fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE));
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end else assign FliResE = '0;
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end else begin
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assign FRoundE = '0;
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assign FRoundFlagsE = '0;
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assign FliResE = '0;
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end
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// fmv.*.x: NaN Box SrcA to extend integer to requested FP size
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if(P.FPSIZES == 1)
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@ -34,10 +34,11 @@ module fround import cvw::*; #(parameter cvw_t P) (
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input logic XNaN, // X is NaN
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input logic XSNaN, // X is Signalling NaN
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input logic XZero, // X is Zero
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input logic [P.FMTBITS-1:0] Fmt // the input's precision (11=quad 01=double 00=single 10=half)
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input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
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output logic [P.FLEN-1:0] FRound, // Rounded result
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output logic [4:0] FRoundFlags // Rounder flags
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);
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logic [P.NE-2:0] Bias;
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logic [P.NE-1:0] E;
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logic [P.NF:0] Imask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd;
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@ -171,4 +172,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
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assign Inexact = FRoundNX & ~(XNaN | Exact) & (Rp | T');
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*/
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assign FRound = '0;
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assign FRoundFlags = '0;
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endmodule
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@ -286,16 +286,18 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign IFUHBURST = 3'b0;
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assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0;
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end
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// mux between the alignments of uncached reads.
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if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16],
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FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
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PCSpillF[2:1], ShiftUncachedInstr);
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else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
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end else begin : nobus // block: bus
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assign {BusStall, CacheCommittedF} = '0;
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assign {IFUHADDR, IFUHWRITE, IFUHSIZE, IFUHBURST, IFUHTRANS,
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BusStall, CacheCommittedF, BusCommittedF, FetchBuffer} = '0;
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assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
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assign InstrRawF = IROMInstrF;
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end
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// mux between the alignments of uncached reads.
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if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
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PCSpillF[2:1], ShiftUncachedInstr);
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else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
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@ -383,7 +383,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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end
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end else begin: nobus // block: bus, only DTIM
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assign LSUHWDATA = '0;
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assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0;
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assign DCacheReadDataWordM = '0;
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assign ReadDataWordMuxM = DTIMReadDataWordM;
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assign {BusStall, BusCommittedM} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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@ -52,6 +52,7 @@ module subwordread import cvw::*; #(parameter cvw_t P) (
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// Use indexed part select to imply muxes to select each size of subword
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if (P.LLEN == 128) mux2 #(64) dblmux(ReadDataWordMuxM[63:0], ReadDataWordMuxM[127:64], PAdrSwapM[3], DblWordM);
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else if (P.LLEN == 64) assign DblWordM = ReadDataWordMuxM;
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else assign DblWordM = '0; // unused for RV32F
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if (P.LLEN >= 64) mux2 #(32) wordmux(DblWordM[31:0], DblWordM[63:32], PAdrSwapM[2], WordM);
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else assign WordM = ReadDataWordMuxM;
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mux2 #(16) halfwordmux(WordM[15:0], WordM[31:16], PAdrSwapM[1], HalfwordM);
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@ -264,6 +264,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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end else begin
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assign {IFUHREADY, LSUHREADY, HCLK, HRESETn, HADDR, HWDATA,
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HWSTRB, HWRITE, HSIZE, HBURST, HPROT, HTRANS, HMASTLOCK} = '0;
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end
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// global stall and flush control
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@ -302,15 +305,12 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
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end else begin
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assign CSRReadValW = '0;
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assign EPCM = '0;
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assign TrapVectorM = '0;
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assign RetM = 1'b0;
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assign TrapM = 1'b0;
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assign wfiM = 1'b0;
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assign IntPendingM = 1'b0;
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assign sfencevmaM = 1'b0;
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assign BigEndianM = 1'b0;
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assign {CSRReadValW, PrivilegeModeW,
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SATP_REGW, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_MPP, STATUS_FS, FRM_REGW,
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// PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW,
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ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE,
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EPCM, TrapVectorM, RetM, TrapM,
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sfencevmaM, BigEndianM, wfiM, IntPendingM} = '0;
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end
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// multiply/divide unit
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@ -351,15 +351,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.SetFflagsM, // FPU flags (to privileged unit)
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.FIntDivResultW);
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end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
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assign FPUStallD = 1'b0;
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assign FWriteIntE = 1'b0;
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assign FCvtIntE = 1'b0;
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assign FIntResM = '0;
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assign FCvtIntW = 1'b0;
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assign FDivBusyE = 1'b0;
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assign IllegalFPUInstrD = 1'b1;
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assign SetFflagsM = '0;
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assign FpLoadStoreM = 1'b0;
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assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW,
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IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
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FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0;
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end
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endmodule
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@ -85,6 +85,9 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
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.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,
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.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin,
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.UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
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end else begin
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assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt,
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MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0;
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end
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endmodule
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@ -33,9 +33,9 @@ def synthsintocsv():
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for oneSynth in allSynths:
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descrip = specReg.findall(oneSynth)
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print("From " + oneSynth + " Find ")
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for d in descrip:
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print(d)
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# print("From " + oneSynth + " Find ")
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# for d in descrip:
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# print(d)
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if (descrip[3] == "sram"):
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base = 4
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else:
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@ -54,7 +54,7 @@ def synthsintocsv():
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for phrase in ['Path Slack', 'Design Area']:
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bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*'
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bashCommand = bashCommand.format(phrase)
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print(bashCommand)
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# print(bashCommand)
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try:
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output = subprocess.check_output(['bash','-c', bashCommand])
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nums = metricReg.findall(str(output))
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@ -1,14 +1,21 @@
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# Run all Wally synthesis experiments from chapter 8
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# However, trying to run the freqsweeps at the same time maxes out licenses and some runs fail
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#./wallySynth.py --freqsweep 330 --tech sky130
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#./wallySynth.py --freqsweep 870 --tech sky90
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#./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
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# Adding the sleep gives them time to finish.
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./wallySynth.py --freqsweep 330 --tech sky130
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sleep 300
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./wallySynth.py --freqsweep 870 --tech sky90
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sleep 300
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./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
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sleep 300
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# These jobs can run in parallel and take longer
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./wallySynth.py --configsweep --tech sky130 --targetfreq 330
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./wallySynth.py --configsweep --tech sky90 --targetfreq 870
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./wallySynth.py --configsweep --tech tsmc28psyn --targetfreq 2800 --usesram
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./wallySynth.py --featuresweep --tech sky130 --targetfreq 330
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./wallySynth.py --featuresweep --tech sky90 --targetfreq 870
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./wallySynth.py --featuresweep --tech tsmc28psyn --targetfreq 2800 --usesram
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# Extract summary data (run this by hand after all experiments finish)
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#./extractSummary.py --sky130freq 330 --sky90freq 870 --tsmcfreq 2800
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# Extract summary data (run this by hand after all experiments finish)
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./extractSummary.py --sky130freq 330 --sky90freq 870 --tsmcfreq 2800
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