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https://github.com/openhwgroup/cvw
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Remove conditional from inside decompress module
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@ -42,11 +42,7 @@ module decompress (
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logic [5:0] immSH;
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logic [1:0] op;
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// if the system handles compressed instructions, decode appropriately
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if (!(`C_SUPPORTED)) begin:decompress // no compressed mode
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assign InstrD = InstrRawD;
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assign IllegalCompInstrD = 0;
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end else begin : decompress // COMPRESSED mode supported
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// Extrac op and register source/destination fields
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assign instr16 = InstrRawD[15:0]; // instruction is already aligned
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assign op = instr16[1:0];
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assign rds1 = instr16[11:7];
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@ -176,6 +172,5 @@ module decompress (
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end
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endcase
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end
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end
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endmodule
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@ -87,7 +87,6 @@ module ifu (
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);
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF;
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logic BranchMisalignedFaultE;
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logic IllegalCompInstrD;
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logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
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logic [`XLEN-1:2] PCPlus4F;
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logic CompressedF;
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@ -340,8 +339,14 @@ module ifu (
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flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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// expand 16-bit compressed instructions to 32 bits
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decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); // *** move the config logic outside
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if (`C_SUPPORTED) begin
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logic IllegalCompInstrD;
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decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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end else begin
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assign InstrD = InstrRawD;
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assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD;
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end
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// Misaligned PC logic
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// Instruction address misalignement only from br/jal(r) instructions.
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