Remove conditional from inside decompress module

pipelined/src/ifu/decompress.sv

@@ -42,11 +42,7 @@ module decompress (
   logic [5:0]         immSH;
   logic [1:0]         op;
     
-  // if the system handles compressed instructions, decode appropriately
-  if (!(`C_SUPPORTED)) begin:decompress // no compressed mode
-    assign InstrD = InstrRawD;
-    assign IllegalCompInstrD = 0;
-  end else begin : decompress // COMPRESSED mode supported
+  // Extrac op and register source/destination fields
   assign instr16 = InstrRawD[15:0]; // instruction is already aligned
   assign op = instr16[1:0];
   assign rds1 = instr16[11:7];
@@ -176,6 +172,5 @@ module decompress (
                   end
       endcase
     end
-    end
 endmodule
     

pipelined/src/ifu/ifu.sv

@@ -87,7 +87,6 @@ module ifu (
 );
   (* mark_debug = "true" *)  logic [`XLEN-1:0]            PCNextF;
   logic                        BranchMisalignedFaultE;
-  logic                        IllegalCompInstrD;
   logic [`XLEN-1:0]            PCPlus2or4F, PCLinkD;
   logic [`XLEN-1:2]            PCPlus4F;
   logic                        CompressedF;
@@ -340,8 +339,14 @@ module ifu (
   flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); // *** move the config logic outside
+  if (`C_SUPPORTED) begin
+    logic IllegalCompInstrD;
+    decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
     assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
+  end else begin  
+    assign InstrD = InstrRawD;
+    assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD;
+  end
 
   // Misaligned PC logic
   // Instruction address misalignement only from br/jal(r) instructions.