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https://github.com/openhwgroup/cvw
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Remove conditional from inside decompress module
This commit is contained in:
David Harris
parent
0a011f4548
commit
d1839b6db2
@ -42,36 +42,32 @@ module decompress (
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logic [5:0] immSH;
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logic [5:0] immSH;
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logic [1:0] op;
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logic [1:0] op;
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// if the system handles compressed instructions, decode appropriately
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// Extrac op and register source/destination fields
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if (!(`C_SUPPORTED)) begin:decompress // no compressed mode
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assign instr16 = InstrRawD[15:0]; // instruction is already aligned
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assign InstrD = InstrRawD;
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assign op = instr16[1:0];
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assign IllegalCompInstrD = 0;
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assign rds1 = instr16[11:7];
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end else begin : decompress // COMPRESSED mode supported
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assign rs2 = instr16[6:2];
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assign instr16 = InstrRawD[15:0]; // instruction is already aligned
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assign rs1p = {2'b01, instr16[9:7]};
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assign op = instr16[1:0];
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assign rds1p = {2'b01, instr16[9:7]};
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assign rds1 = instr16[11:7];
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assign rs2p = {2'b01, instr16[4:2]};
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assign rs2 = instr16[6:2];
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assign rdp = {2'b01, instr16[4:2]};
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assign rs1p = {2'b01, instr16[9:7]};
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assign rds1p = {2'b01, instr16[9:7]};
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assign rs2p = {2'b01, instr16[4:2]};
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assign rdp = {2'b01, instr16[4:2]};
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// many compressed immediate formats
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// many compressed immediate formats
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assign immCILSP = {4'b0000, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
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assign immCILSP = {4'b0000, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
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assign immCILSPD = {3'b000, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
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assign immCILSPD = {3'b000, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
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assign immCSS = {4'b0000, instr16[8:7], instr16[12:9], 2'b00};
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assign immCSS = {4'b0000, instr16[8:7], instr16[12:9], 2'b00};
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assign immCSSD = {3'b000, instr16[9:7], instr16[12:10], 3'b000};
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assign immCSSD = {3'b000, instr16[9:7], instr16[12:10], 3'b000};
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assign immCL = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCL = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCLD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCLD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCS = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCS = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCSD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCSD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCJ = {instr16[12], instr16[8], instr16[10:9], instr16[6], instr16[7], instr16[2], instr16[11], instr16[5:3], {9{instr16[12]}}};
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assign immCJ = {instr16[12], instr16[8], instr16[10:9], instr16[6], instr16[7], instr16[2], instr16[11], instr16[5:3], {9{instr16[12]}}};
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assign immCB = {{4{instr16[12]}}, instr16[6:5], instr16[2], instr16[11:10], instr16[4:3], instr16[12]};
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assign immCB = {{4{instr16[12]}}, instr16[6:5], instr16[2], instr16[11:10], instr16[4:3], instr16[12]};
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assign immCI = {{7{instr16[12]}}, instr16[6:2]};
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assign immCI = {{7{instr16[12]}}, instr16[6:2]};
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assign immCILUI = {{15{instr16[12]}}, instr16[6:2]};
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assign immCILUI = {{15{instr16[12]}}, instr16[6:2]};
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assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000};
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assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000};
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assign immCIW = {2'b00, instr16[10:7], instr16[12:11], instr16[5], instr16[6], 2'b00};
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assign immCIW = {2'b00, instr16[10:7], instr16[12:11], instr16[5], instr16[6], 2'b00};
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assign immSH = {instr16[12], instr16[6:2]};
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assign immSH = {instr16[12], instr16[6:2]};
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// only for RV128
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// only for RV128
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// assign immCILSPQ = {2{instr16[5]}, instr16[5:2], instr16[12], instr16[6], 4'b0000};
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// assign immCILSPQ = {2{instr16[5]}, instr16[5:2], instr16[12], instr16[6], 4'b0000};
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@ -79,103 +75,102 @@ module decompress (
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// assign immCLQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
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// assign immCLQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
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// assign immCSQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
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// assign immCSQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
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always_comb
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always_comb
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if (op == 2'b11) begin // noncompressed instruction
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if (op == 2'b11) begin // noncompressed instruction
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InstrD = InstrRawD;
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InstrD = InstrRawD;
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IllegalCompInstrD = 0;
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IllegalCompInstrD = 0;
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end else begin // convert compressed instruction into uncompressed
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end else begin // convert compressed instruction into uncompressed
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IllegalCompInstrD = 0;
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IllegalCompInstrD = 0;
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case ({op, instr16[15:13]})
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case ({op, instr16[15:13]})
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5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn
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5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn
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else begin // illegal instruction
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else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
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5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
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5'b00011: if (`XLEN==32)
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InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
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else
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InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
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5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
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5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
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5'b00111: if (`XLEN==32)
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InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
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else
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InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
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5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
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5'b01001: if (`XLEN==32)
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InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
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else
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InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
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5'b01010: InstrD = {immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li
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5'b01011: if (rds1 != 5'b00010)
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InstrD = {immCILUI, rds1, 7'b0110111}; // c.lui
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else
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InstrD = {immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp
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5'b01100: if (instr16[11:10] == 2'b00)
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InstrD = {6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli
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else if (instr16[11:10] == 2'b01)
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InstrD = {6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai
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else if (instr16[11:10] == 2'b10)
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InstrD = {immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi
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else if (instr16[12:10] == 3'b011)
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if (instr16[6:5] == 2'b00)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub
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else if (instr16[6:5] == 2'b01)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor
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else if (instr16[6:5] == 2'b10)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
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else // if (instr16[6:5] == 2'b11)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
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else if (instr16[12:10] == 3'b111 & `XLEN > 32)
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if (instr16[6:5] == 2'b00)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
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else if (instr16[6:5] == 2'b01)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
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else begin // reserved
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IllegalCompInstrD = 1;
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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end
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5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
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else begin // illegal instruction
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5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
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IllegalCompInstrD = 1;
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5'b00011: if (`XLEN==32)
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
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end
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5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
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5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
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5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
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5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
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5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
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5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
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5'b10011: if (`XLEN == 32)
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InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
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else
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InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
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5'b10100: if (instr16[12] == 0)
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if (instr16[6:2] == 5'b00000)
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InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
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else
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else
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InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
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InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
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5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
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else
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5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
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if (rs2 == 5'b00000)
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5'b00111: if (`XLEN==32)
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if (rds1 == 5'b00000)
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InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
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InstrD = {12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak
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else
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InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
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5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
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5'b01001: if (`XLEN==32)
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InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
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else
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InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
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5'b01010: InstrD = {immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li
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5'b01011: if (rds1 != 5'b00010)
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InstrD = {immCILUI, rds1, 7'b0110111}; // c.lui
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else
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InstrD = {immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp
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5'b01100: if (instr16[11:10] == 2'b00)
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InstrD = {6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli
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else if (instr16[11:10] == 2'b01)
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InstrD = {6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai
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else if (instr16[11:10] == 2'b10)
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InstrD = {immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi
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else if (instr16[12:10] == 3'b011)
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if (instr16[6:5] == 2'b00)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub
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else if (instr16[6:5] == 2'b01)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor
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else if (instr16[6:5] == 2'b10)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
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else // if (instr16[6:5] == 2'b11)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
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else if (instr16[12:10] == 3'b111 & `XLEN > 32)
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if (instr16[6:5] == 2'b00)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
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else if (instr16[6:5] == 2'b01)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
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else begin // reserved
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
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5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
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5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
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5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
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5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
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5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
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5'b10011: if (`XLEN == 32)
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InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
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else
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InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
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5'b10100: if (instr16[12] == 0)
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if (instr16[6:2] == 5'b00000)
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InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
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else
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else
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InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
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InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
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else
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else
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if (rs2 == 5'b00000)
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InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
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if (rds1 == 5'b00000)
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5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
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InstrD = {12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak
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5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
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else
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5'b10111: if (`XLEN==32)
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InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
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InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
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else
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else
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InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
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InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
|
||||||
5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
|
default: begin // illegal instruction
|
||||||
5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
|
IllegalCompInstrD = 1;
|
||||||
5'b10111: if (`XLEN==32)
|
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
||||||
InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
|
end
|
||||||
else
|
endcase
|
||||||
InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
|
|
||||||
default: begin // illegal instruction
|
|
||||||
IllegalCompInstrD = 1;
|
|
||||||
InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
|
|
||||||
end
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|||||||
@ -87,7 +87,6 @@ module ifu (
|
|||||||
);
|
);
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF;
|
||||||
logic BranchMisalignedFaultE;
|
logic BranchMisalignedFaultE;
|
||||||
logic IllegalCompInstrD;
|
|
||||||
logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
|
logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
|
||||||
logic [`XLEN-1:2] PCPlus4F;
|
logic [`XLEN-1:2] PCPlus4F;
|
||||||
logic CompressedF;
|
logic CompressedF;
|
||||||
@ -340,8 +339,14 @@ module ifu (
|
|||||||
flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
|
||||||
|
|
||||||
// expand 16-bit compressed instructions to 32 bits
|
// expand 16-bit compressed instructions to 32 bits
|
||||||
decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); // *** move the config logic outside
|
if (`C_SUPPORTED) begin
|
||||||
assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
logic IllegalCompInstrD;
|
||||||
|
decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
|
||||||
|
assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
|
||||||
|
end else begin
|
||||||
|
assign InstrD = InstrRawD;
|
||||||
|
assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD;
|
||||||
|
end
|
||||||
|
|
||||||
// Misaligned PC logic
|
// Misaligned PC logic
|
||||||
// Instruction address misalignement only from br/jal(r) instructions.
|
// Instruction address misalignement only from br/jal(r) instructions.
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user