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Modified uncore to use AHB bridge to GPIO

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This commit is contained in:
David Harris 2022-07-05 05:02:21 +00:00
parent e7fe7ad0c8
commit d033659beb
1 changed files with 125 additions and 92 deletions
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49
pipelined/src/uncore/uncore.sv
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@ -81,6 +81,24 @@ module uncore (
logic UARTIntr,GPIOIntr; logic UARTIntr,GPIOIntr;
logic SDCIntM; logic SDCIntM;
logic PCLK, PRESETn, PWRITE, PENABLE;
// logic PSEL, PREADY;
logic [1:0] PSEL, PREADY;
logic [31:0] PADDR;
logic [`XLEN-1:0] PWDATA;
logic [`XLEN/8-1:0] PSTRB;
logic [1:0][`XLEN-1:0] PRDATA;
// logic [`XLEN-1:0][8:0] PRDATA;
logic [`XLEN-1:0] HREADBRIDGE;
logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
// *** to do:
// combinational loop related to HREADY, HREADYOUT through PENABLE
// hook up and test GPIO on AHB
// hook up HWSTRB and remove subword write decoders
// add other peripherals on AHB
// HTRANS encoding
// Determine which region of physical memory (if any) is being accessed // Determine which region of physical memory (if any) is being accessed
// Use a trimmed down portion of the PMA checker - only the address decoders // Use a trimmed down portion of the PMA checker - only the address decoders
// Set access types to all 1 as don't cares because the MMU has already done access checking // Set access types to all 1 as don't cares because the MMU has already done access checking
@ -89,7 +107,16 @@ module uncore (
// unswizzle HSEL signals // unswizzle HSEL signals
assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
// generate // AHB -> APB bridge
ahbapbbridge #(2) ahbapbbridge
(.HCLK, .HRESETn, .HSEL({1'b0, HSELGPIO}), .HADDR, .HWDATA, .HWRITE, .HTRANS, .HREADY, .HWSTRB('1),
.HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
.PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
assign PREADY[1] = 0; // *** replace these with connections to other peripherals
assign PRDATA[1] = 0;
assign HSELBRIDGE = HSELGPIO; // if any of the bridge signals are selected
// This system is showing a combinatonal loop related to HREADY and HREADYBRIDGE and HREADYGPIO
// on-chip RAM // on-chip RAM
if (`RAM_SUPPORTED) begin : ram if (`RAM_SUPPORTED) begin : ram
ram #( ram #(
@ -139,7 +166,7 @@ module uncore (
assign SExtInt = 0; assign SExtInt = 0;
end end
if (`GPIO_SUPPORTED == 1) begin : gpio if (`GPIO_SUPPORTED == 1) begin : gpio
gpio gpio( /* gpio gpio(
.HCLK, .HRESETn, .HSELGPIO, .HCLK, .HRESETn, .HSELGPIO,
.HADDR(HADDR[7:0]), .HADDR(HADDR[7:0]),
.HWDATA, .HWDATA,
@ -149,8 +176,11 @@ module uncore (
.HRESPGPIO, .HREADYGPIO, .HRESPGPIO, .HREADYGPIO,
.GPIOPinsIn, .GPIOPinsIn,
.GPIOPinsOut, .GPIOPinsEn, .GPIOPinsOut, .GPIOPinsEn,
.GPIOIntr); .GPIOIntr); */
gpio_apb gpio(
.PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
.PRDATA(PRDATA[0]), .PREADY(PREADY[0]),
.iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr);
end else begin : gpio end else begin : gpio
assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
end end
@ -180,7 +210,6 @@ module uncore (
assign SDCCmdOut = 0; assign SDCCmdOut = 0;
assign SDCCmdOE = 0; assign SDCCmdOE = 0;
end end
// endgenerate
// mux could also include external memory // mux could also include external memory
// AHB Read Multiplexer // AHB Read Multiplexer
@ -188,7 +217,8 @@ module uncore (
({`XLEN{HSELEXTD}} & HRDATAEXT) | ({`XLEN{HSELEXTD}} & HRDATAEXT) |
({`XLEN{HSELCLINTD}} & HREADCLINT) | ({`XLEN{HSELCLINTD}} & HREADCLINT) |
({`XLEN{HSELPLICD}} & HREADPLIC) | ({`XLEN{HSELPLICD}} & HREADPLIC) |
({`XLEN{HSELGPIOD}} & HREADGPIO) | // ({`XLEN{HSELGPIOD}} & HREADGPIO) |
({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
({`XLEN{HSELBootRomD}} & HREADBootRom) | ({`XLEN{HSELBootRomD}} & HREADBootRom) |
({`XLEN{HSELUARTD}} & HREADUART) | ({`XLEN{HSELUARTD}} & HREADUART) |
({`XLEN{HSELSDCD}} & HREADSDC); ({`XLEN{HSELSDCD}} & HREADSDC);
@ -197,7 +227,8 @@ module uncore (
HSELEXTD & HRESPEXT | HSELEXTD & HRESPEXT |
HSELCLINTD & HRESPCLINT | HSELCLINTD & HRESPCLINT |
HSELPLICD & HRESPPLIC | HSELPLICD & HRESPPLIC |
HSELGPIOD & HRESPGPIO | // HSELGPIOD & HRESPGPIO |
HSELBRIDGE & HRESPBRIDGE |
HSELBootRomD & HRESPBootRom | HSELBootRomD & HRESPBootRom |
HSELUARTD & HRESPUART | HSELUARTD & HRESPUART |
HSELSDC & HRESPSDC; HSELSDC & HRESPSDC;
@ -206,7 +237,8 @@ module uncore (
HSELEXTD & HREADYEXT | HSELEXTD & HREADYEXT |
HSELCLINTD & HREADYCLINT | HSELCLINTD & HREADYCLINT |
HSELPLICD & HREADYPLIC | HSELPLICD & HREADYPLIC |
HSELGPIOD & HREADYGPIO | // HSELGPIOD & HREADYGPIO |
HSELBRIDGED & HREADYBRIDGE |
HSELBootRomD & HREADYBootRom | HSELBootRomD & HREADYBootRom |
HSELUARTD & HREADYUART | HSELUARTD & HREADYUART |
HSELSDCD & HREADYSDC | HSELSDCD & HREADYSDC |
@ -214,5 +246,6 @@ module uncore (
// Address Decoder Delay (figure 4-2 in spec) // Address Decoder Delay (figure 4-2 in spec)
flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
endmodule endmodule