From d033659beb584b9f01f179d0268dc7ea03beab27 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 5 Jul 2022 05:02:21 +0000 Subject: [PATCH] Modified uncore to use AHB bridge to GPIO --- pipelined/src/uncore/uncore.sv | 217 +++++++++++++++++++-------------- 1 file changed, 125 insertions(+), 92 deletions(-) diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index a69b7cd0c..66219ffe7 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -81,6 +81,24 @@ module uncore ( logic UARTIntr,GPIOIntr; logic SDCIntM; + logic PCLK, PRESETn, PWRITE, PENABLE; +// logic PSEL, PREADY; + logic [1:0] PSEL, PREADY; + logic [31:0] PADDR; + logic [`XLEN-1:0] PWDATA; + logic [`XLEN/8-1:0] PSTRB; + logic [1:0][`XLEN-1:0] PRDATA; +// logic [`XLEN-1:0][8:0] PRDATA; + logic [`XLEN-1:0] HREADBRIDGE; + logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; + + // *** to do: + // combinational loop related to HREADY, HREADYOUT through PENABLE + // hook up and test GPIO on AHB + // hook up HWSTRB and remove subword write decoders + // add other peripherals on AHB + // HTRANS encoding + // Determine which region of physical memory (if any) is being accessed // Use a trimmed down portion of the PMA checker - only the address decoders // Set access types to all 1 as don't cares because the MMU has already done access checking @@ -89,98 +107,109 @@ module uncore ( // unswizzle HSEL signals assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; -// generate - // on-chip RAM - if (`RAM_SUPPORTED) begin : ram - ram #( - .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( - .HCLK, .HRESETn, - .HSELRam, .HADDR, - .HWRITE, .HREADY, .HSIZED, - .HTRANS, .HWDATA, .HREADRam, - .HRESPRam, .HREADYRam); - end + // AHB -> APB bridge + ahbapbbridge #(2) ahbapbbridge + (.HCLK, .HRESETn, .HSEL({1'b0, HSELGPIO}), .HADDR, .HWDATA, .HWRITE, .HTRANS, .HREADY, .HWSTRB('1), + .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE), + .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA); + assign PREADY[1] = 0; // *** replace these with connections to other peripherals + assign PRDATA[1] = 0; + assign HSELBRIDGE = HSELGPIO; // if any of the bridge signals are selected + // This system is showing a combinatonal loop related to HREADY and HREADYBRIDGE and HREADYGPIO + + // on-chip RAM + if (`RAM_SUPPORTED) begin : ram + ram #( + .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( + .HCLK, .HRESETn, + .HSELRam, .HADDR, + .HWRITE, .HREADY, .HSIZED, + .HTRANS, .HWDATA, .HREADRam, + .HRESPRam, .HREADYRam); + end - if (`BOOTROM_SUPPORTED) begin : bootrom - ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) - bootrom( - .HCLK, .HRESETn, - .HSELRam(HSELBootRom), .HADDR, - .HWRITE, .HREADY, .HTRANS, .HSIZED, - .HWDATA, - .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom)); - end + if (`BOOTROM_SUPPORTED) begin : bootrom + ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) + bootrom( + .HCLK, .HRESETn, + .HSELRam(HSELBootRom), .HADDR, + .HWRITE, .HREADY, .HTRANS, .HSIZED, + .HWDATA, + .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom)); + end - // memory-mapped I/O peripherals - if (`CLINT_SUPPORTED == 1) begin : clint - clint clint( - .HCLK, .HRESETn, .TIMECLK, - .HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE, - .HWDATA, .HREADY, .HTRANS, .HSIZED, - .HREADCLINT, - .HRESPCLINT, .HREADYCLINT, - .MTIME(MTIME_CLINT), - .MTimerInt, .MSwInt); + // memory-mapped I/O peripherals + if (`CLINT_SUPPORTED == 1) begin : clint + clint clint( + .HCLK, .HRESETn, .TIMECLK, + .HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE, + .HWDATA, .HREADY, .HTRANS, .HSIZED, + .HREADCLINT, + .HRESPCLINT, .HREADYCLINT, + .MTIME(MTIME_CLINT), + .MTimerInt, .MSwInt); - end else begin : clint - assign MTIME_CLINT = 0; - assign MTimerInt = 0; assign MSwInt = 0; - end - if (`PLIC_SUPPORTED == 1) begin : plic - plic plic( - .HCLK, .HRESETn, - .HSELPLIC, .HADDR(HADDR[27:0]), - .HWRITE, .HREADY, .HTRANS, .HWDATA, - .UARTIntr, .GPIOIntr, - .HREADPLIC, .HRESPPLIC, .HREADYPLIC, - .MExtInt, .SExtInt); - end else begin : plic - assign MExtInt = 0; - assign SExtInt = 0; - end - if (`GPIO_SUPPORTED == 1) begin : gpio - gpio gpio( - .HCLK, .HRESETn, .HSELGPIO, - .HADDR(HADDR[7:0]), - .HWDATA, - .HWRITE, .HREADY, - .HTRANS, - .HREADGPIO, - .HRESPGPIO, .HREADYGPIO, - .GPIOPinsIn, - .GPIOPinsOut, .GPIOPinsEn, - .GPIOIntr); - - end else begin : gpio - assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; - end - if (`UART_SUPPORTED == 1) begin : uart - uart uart( - .HCLK, .HRESETn, - .HSELUART, - .HADDR(HADDR[2:0]), - .HWRITE, .HWDATA, - .HREADUART, .HRESPUART, .HREADYUART, - .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface - .SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface - .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU - end else begin : uart - assign UARTSout = 0; assign UARTIntr = 0; - end - if (`SDC_SUPPORTED == 1) begin : sdc - SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, - .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, - // sdc interface - .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK, - // interrupt to PLIC - .SDCIntM - ); - end else begin : sdc - assign SDCCLK = 0; - assign SDCCmdOut = 0; - assign SDCCmdOE = 0; - end -// endgenerate + end else begin : clint + assign MTIME_CLINT = 0; + assign MTimerInt = 0; assign MSwInt = 0; + end + if (`PLIC_SUPPORTED == 1) begin : plic + plic plic( + .HCLK, .HRESETn, + .HSELPLIC, .HADDR(HADDR[27:0]), + .HWRITE, .HREADY, .HTRANS, .HWDATA, + .UARTIntr, .GPIOIntr, + .HREADPLIC, .HRESPPLIC, .HREADYPLIC, + .MExtInt, .SExtInt); + end else begin : plic + assign MExtInt = 0; + assign SExtInt = 0; + end + if (`GPIO_SUPPORTED == 1) begin : gpio +/* gpio gpio( + .HCLK, .HRESETn, .HSELGPIO, + .HADDR(HADDR[7:0]), + .HWDATA, + .HWRITE, .HREADY, + .HTRANS, + .HREADGPIO, + .HRESPGPIO, .HREADYGPIO, + .GPIOPinsIn, + .GPIOPinsOut, .GPIOPinsEn, + .GPIOIntr); */ + gpio_apb gpio( + .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, + .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), + .iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr); + end else begin : gpio + assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; + end + if (`UART_SUPPORTED == 1) begin : uart + uart uart( + .HCLK, .HRESETn, + .HSELUART, + .HADDR(HADDR[2:0]), + .HWRITE, .HWDATA, + .HREADUART, .HRESPUART, .HREADYUART, + .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface + .SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface + .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU + end else begin : uart + assign UARTSout = 0; assign UARTIntr = 0; + end + if (`SDC_SUPPORTED == 1) begin : sdc + SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, + .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, + // sdc interface + .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK, + // interrupt to PLIC + .SDCIntM + ); + end else begin : sdc + assign SDCCLK = 0; + assign SDCCmdOut = 0; + assign SDCCmdOE = 0; + end // mux could also include external memory // AHB Read Multiplexer @@ -188,7 +217,8 @@ module uncore ( ({`XLEN{HSELEXTD}} & HRDATAEXT) | ({`XLEN{HSELCLINTD}} & HREADCLINT) | ({`XLEN{HSELPLICD}} & HREADPLIC) | - ({`XLEN{HSELGPIOD}} & HREADGPIO) | +// ({`XLEN{HSELGPIOD}} & HREADGPIO) | + ({`XLEN{HSELBRIDGED}} & HREADBRIDGE) | ({`XLEN{HSELBootRomD}} & HREADBootRom) | ({`XLEN{HSELUARTD}} & HREADUART) | ({`XLEN{HSELSDCD}} & HREADSDC); @@ -197,7 +227,8 @@ module uncore ( HSELEXTD & HRESPEXT | HSELCLINTD & HRESPCLINT | HSELPLICD & HRESPPLIC | - HSELGPIOD & HRESPGPIO | +// HSELGPIOD & HRESPGPIO | + HSELBRIDGE & HRESPBRIDGE | HSELBootRomD & HRESPBootRom | HSELUARTD & HRESPUART | HSELSDC & HRESPSDC; @@ -206,7 +237,8 @@ module uncore ( HSELEXTD & HREADYEXT | HSELCLINTD & HREADYCLINT | HSELPLICD & HREADYPLIC | - HSELGPIOD & HREADYGPIO | +// HSELGPIOD & HREADYGPIO | + HSELBRIDGED & HREADYBRIDGE | HSELBootRomD & HREADYBootRom | HSELUARTD & HREADYUART | HSELSDCD & HREADYSDC | @@ -214,5 +246,6 @@ module uncore ( // Address Decoder Delay (figure 4-2 in spec) flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); + flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED); endmodule