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Updated verilog-ethernet to be compatible with wally.

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This commit is contained in:
Rose Thompson 2024-07-19 13:36:26 -05:00
parent a324e79b6f
commit ce2cc48642
2 changed files with 17 additions and 17 deletions
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32
addins/sparse-checkout
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@ -1,16 +1,16 @@
rtl/eth_mac_mii_fifo.v rtl/eth_mac_mii_fifo.sv
rtl/eth_mac_mii.v rtl/eth_mac_mii.sv
rtl/mii_phy_if.v rtl/mii_phy_if.sv
rtl/ssio_ddr_in.v rtl/ssio_ddr_in.sv
rtl/eth_mac_1g.v rtl/eth_mac_1g.sv
rtl/axis_gmii_rx.v rtl/axis_gmii_rx.sv
rtl/lfsr.v rtl/lfsr.sv
rtl/eth_axis_tx.v rtl/eth_axis_tx.sv
rtl/mac_ctrl_tx.v rtl/mac_ctrl_tx.sv
rtl/axis_gmii_tx.v rtl/axis_gmii_tx.sv
rtl/mac_ctrl_rx.v rtl/mac_ctrl_rx.sv
rtl/mac_pause_ctrl_tx.v rtl/mac_pause_ctrl_tx.sv
rtl/mac_pause_ctrl_rx.v rtl/mac_pause_ctrl_rx.sv
lib/axis/rtl/axis_async_fifo_adapter.v lib/axis/rtl/axis_async_fifo_adapter.sv
lib/axis/rtl/axis_adapter.v lib/axis/rtl/axis_adapter.sv
lib/axis/rtl/axis_async_fifo.v lib/axis/rtl/axis_async_fifo.sv

2
addins/verilog-ethernet

@ -1 +1 @@
Subproject commit baac5f8d811d43853d59d69957975ead8bbed088 Subproject commit 13c33ff1a82348691a40d78cf2bab10cbf4f76b2