diff --git a/addins/sparse-checkout b/addins/sparse-checkout
index 76eadb284..f1743725c 100644
--- a/addins/sparse-checkout
+++ b/addins/sparse-checkout
@@ -1,16 +1,16 @@
-rtl/eth_mac_mii_fifo.v
-rtl/eth_mac_mii.v
-rtl/mii_phy_if.v
-rtl/ssio_ddr_in.v
-rtl/eth_mac_1g.v
-rtl/axis_gmii_rx.v
-rtl/lfsr.v
-rtl/eth_axis_tx.v
-rtl/mac_ctrl_tx.v
-rtl/axis_gmii_tx.v
-rtl/mac_ctrl_rx.v
-rtl/mac_pause_ctrl_tx.v
-rtl/mac_pause_ctrl_rx.v
-lib/axis/rtl/axis_async_fifo_adapter.v
-lib/axis/rtl/axis_adapter.v
-lib/axis/rtl/axis_async_fifo.v
+rtl/eth_mac_mii_fifo.sv
+rtl/eth_mac_mii.sv
+rtl/mii_phy_if.sv
+rtl/ssio_ddr_in.sv
+rtl/eth_mac_1g.sv
+rtl/axis_gmii_rx.sv
+rtl/lfsr.sv
+rtl/eth_axis_tx.sv
+rtl/mac_ctrl_tx.sv
+rtl/axis_gmii_tx.sv
+rtl/mac_ctrl_rx.sv
+rtl/mac_pause_ctrl_tx.sv
+rtl/mac_pause_ctrl_rx.sv
+lib/axis/rtl/axis_async_fifo_adapter.sv
+lib/axis/rtl/axis_adapter.sv
+lib/axis/rtl/axis_async_fifo.sv
diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet
index baac5f8d8..13c33ff1a 160000
--- a/addins/verilog-ethernet
+++ b/addins/verilog-ethernet
@@ -1 +1 @@
-Subproject commit baac5f8d811d43853d59d69957975ead8bbed088
+Subproject commit 13c33ff1a82348691a40d78cf2bab10cbf4f76b2