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More unused signal cleanup

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This commit is contained in:
David Harris 2022-05-12 15:26:08 +00:00
parent 5670f77de2
commit ce24c080d5
2 changed files with 5 additions and 8 deletions
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4
pipelined/src/ifu/ifu.sv
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@ -33,8 +33,8 @@
module ifu ( module ifu (
input logic clk, reset, input logic clk, reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM,
input logic FlushF, FlushD, FlushE, FlushM, FlushW, input logic FlushF, FlushD, FlushE, FlushM,
// Bus interface // Bus interface
(* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA,
(* mark_debug = "true" *) input logic IFUBusAck, (* mark_debug = "true" *) input logic IFUBusAck,

9
pipelined/src/wally/wallypipelinedcore.sv
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@ -63,13 +63,11 @@ module wallypipelinedcore (
// new signals that must connect through DP // new signals that must connect through DP
logic MDUE, W64E; logic MDUE, W64E;
logic CSRReadM, CSRWriteM, PrivilegedM; logic CSRReadM, CSRWriteM, PrivilegedM;
logic [1:0] AtomicE;
logic [1:0] AtomicM; logic [1:0] AtomicM;
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
(* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM; (* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM;
logic [2:0] Funct3E; logic [2:0] Funct3E;
// logic [31:0] InstrF; logic [31:0] InstrD;
logic [31:0] InstrD, InstrW;
(* mark_debug = "true" *) logic [31:0] InstrM; (* mark_debug = "true" *) logic [31:0] InstrM;
logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE;
(* mark_debug = "true" *) logic [`XLEN-1:0] PCM; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
@ -166,8 +164,8 @@ module wallypipelinedcore (
ifu ifu( ifu ifu(
.clk, .reset, .clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW, .FlushF, .FlushD, .FlushE, .FlushM,
// Fetch // Fetch
.IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
.IFUBusRead, .IFUStallF, .IFUBusRead, .IFUStallF,
@ -217,7 +215,6 @@ module wallypipelinedcore (
// Memory stage interface // Memory stage interface
.SquashSCW, // from LSU .SquashSCW, // from LSU
.MemRWM, // read/write control goes to LSU .MemRWM, // read/write control goes to LSU
.AtomicE, // atomic control goes to LSU
.AtomicM, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU
.WriteDataE, // Write data to LSU .WriteDataE, // Write data to LSU
.Funct3M, // size and signedness to LSU .Funct3M, // size and signedness to LSU