diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index d10bb95f6..be340b2e6 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -33,8 +33,8 @@
 
 module ifu (
 	input logic 				clk, reset,
-	input logic 				StallF, StallD, StallE, StallM, StallW,
-	input logic 				FlushF, FlushD, FlushE, FlushM, FlushW,
+	input logic 				StallF, StallD, StallE, StallM, 
+	input logic 				FlushF, FlushD, FlushE, FlushM, 
 	// Bus interface
 (* mark_debug = "true" *)	input logic [`XLEN-1:0] 	IFUBusHRDATA,
 (* mark_debug = "true" *)	input logic 				IFUBusAck,
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 0ca52dc55..ccbc25df3 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -63,13 +63,11 @@ module wallypipelinedcore (
   // new signals that must connect through DP
   logic             MDUE, W64E;
   logic             CSRReadM, CSRWriteM, PrivilegedM;
-  logic [1:0]             AtomicE;
   logic [1:0]             AtomicM;
   logic [`XLEN-1:0]     ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
 (* mark_debug = "true" *)  logic [`XLEN-1:0]         SrcAM;
   logic [2:0]             Funct3E;
-  //  logic [31:0] InstrF;
-  logic [31:0]             InstrD, InstrW;
+  logic [31:0]             InstrD;
   (* mark_debug = "true" *) logic [31:0]             InstrM;
   logic [`XLEN-1:0]         PCF, PCD, PCE, PCLinkE;
   (* mark_debug = "true" *) logic [`XLEN-1:0]         PCM;
@@ -166,8 +164,8 @@ module wallypipelinedcore (
   
   ifu ifu(
     .clk, .reset,
-    .StallF, .StallD, .StallE, .StallM, .StallW,
-    .FlushF, .FlushD, .FlushE, .FlushM, .FlushW,
+    .StallF, .StallD, .StallE, .StallM, 
+    .FlushF, .FlushD, .FlushE, .FlushM, 
     // Fetch
     .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
     .IFUBusRead, .IFUStallF,
@@ -217,7 +215,6 @@ module wallypipelinedcore (
      // Memory stage interface
      .SquashSCW, // from LSU
      .MemRWM, // read/write control goes to LSU
-     .AtomicE, // atomic control goes to LSU        
      .AtomicM, // atomic control goes to LSU
      .WriteDataE, // Write data to LSU
      .Funct3M, // size and signedness to LSU