From 4062038848b754c7742da776e92ab6b4cf269613 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 18:06:20 -0500 Subject: [PATCH 1/3] Added some additional details about the buildroot install. --- docs/README-linux.md | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/README-linux.md b/docs/README-linux.md index cf9c146dc..63a3f5e2b 100644 --- a/docs/README-linux.md +++ b/docs/README-linux.md @@ -16,6 +16,7 @@ To configure and build Buildroot: $ make --jobs To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. +Depending on your system configuration this makefile may need a bit of tweaking. It places the output buildroot images in $RISCV/linux-testvectors and the buildroot object dumps in $RISCV/buildroot/output/images/disassembly. If these directories are owned by root then the makefile will likely fail. You can either change the makefile's target directories or change temporarily change the owner of the two directories. $ source ~/riscv-wally/setup.sh $ cd $WALLY/linux/buildroot-scripts From 059c73a4d207cdcc73e04c037ff9037e4e5e480b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 18:36:02 -0500 Subject: [PATCH 2/3] First stab at the i cache logger. --- testbench/testbench.sv | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index bb70a6360..575b9b6c5 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,6 +30,7 @@ `define PrintHPMCounters 1 `define BPRED_LOGGER 1 +`define INSTR_FETCH_ADDR_LOGGER 0 module testbench; parameter DEBUG=0; @@ -546,7 +547,29 @@ logic [3:0] dummy; end end end +end + + + if (`INSTR_FETCH_ADDR_LOGGER == 1) begin + int file; + string LogFile; + logic resetD, resetEdge; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + initial begin + LogFile = $psprintf("ICache.log"); + file = $fopen(LogFile, "w"); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(dut.core.StallD & ~dut.core.FlushD) begin + $fwrite(file, "%h R\n", dut.core.ifu.PCF); + end + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end end + if (`BPRED_SUPPORTED == 1) begin From 514738ad965430e9a92cd161fb96b646a8d4f28a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Mar 2023 23:44:50 -0500 Subject: [PATCH 3/3] Now reports i cache and d cache memory accesses. --- testbench/testbench.sv | 39 +++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 575b9b6c5..f07cfef12 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -30,7 +30,8 @@ `define PrintHPMCounters 1 `define BPRED_LOGGER 1 -`define INSTR_FETCH_ADDR_LOGGER 0 +`define I_CACHE_ADDR_LOGGER 1 +`define D_CACHE_ADDR_LOGGER 1 module testbench; parameter DEBUG=0; @@ -550,7 +551,7 @@ logic [3:0] dummy; end - if (`INSTR_FETCH_ADDR_LOGGER == 1) begin + if (`I_CACHE_ADDR_LOGGER == 1) begin int file; string LogFile; logic resetD, resetEdge; @@ -563,15 +564,41 @@ end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); - if(dut.core.StallD & ~dut.core.FlushD) begin - $fwrite(file, "%h R\n", dut.core.ifu.PCF); + if(~dut.core.StallD & ~dut.core.FlushD) begin + $fwrite(file, "%h R\n", dut.core.ifu.PCPF); + end + if(EndSample) $fwrite(file, "END %s\n", memfilename); + end + end + + if (`D_CACHE_ADDR_LOGGER == 1) begin + int file; + string LogFile; + logic resetD, resetEdge; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; + initial begin + LogFile = $psprintf("DCache.log"); + file = $fopen(LogFile, "w"); + end + always @(posedge clk) begin + if(resetEdge) $fwrite(file, "TRAIN\n"); + if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename); + if(~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + if(dut.core.lsu.bus.dcache.CacheRWM == 2'b10) begin + $fwrite(file, "%h R\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.CacheRWM == 2'b01) begin + $fwrite(file, "%h W\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.CacheAtomicM[1] == 1'b1) begin // *** This may change + $fwrite(file, "%h A\n", dut.core.lsu.PAdrM); + end else if (dut.core.lsu.bus.dcache.FlushDCache) begin + $fwrite(file, "%h F\n", dut.core.lsu.PAdrM); + end end if(EndSample) $fwrite(file, "END %s\n", memfilename); end end - - if (`BPRED_SUPPORTED == 1) begin if (`BPRED_LOGGER) begin string direction;