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Cleaned bram interface

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This commit is contained in:
David Harris 2022-06-08 01:39:44 +00:00
parent f81719337e
commit cc06fa1c55
5 changed files with 36 additions and 16 deletions
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8
pipelined/src/generic/flop/bram1p1rw.sv
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@ -44,8 +44,8 @@ module bram1p1rw
//---------------------------------------------------------------------- //----------------------------------------------------------------------
) ( ) (
input logic clk, input logic clk,
input logic en, input logic we,
input logic [NUM_COL-1:0] we, input logic [NUM_COL-1:0] bwe,
input logic [ADDR_WIDTH-1:0] addr, input logic [ADDR_WIDTH-1:0] addr,
output logic [DATA_WIDTH-1:0] dout, output logic [DATA_WIDTH-1:0] dout,
input logic [DATA_WIDTH-1:0] din input logic [DATA_WIDTH-1:0] din
@ -60,9 +60,9 @@ module bram1p1rw
always @ (posedge clk) begin always @ (posedge clk) begin
dout <= RAM[addr]; dout <= RAM[addr];
if(en) begin if(we) begin
for(i=0;i<NUM_COL;i=i+1) begin for(i=0;i<NUM_COL;i=i+1) begin
if(we[i]) begin if(bwe[i]) begin
RAM[addr][i*COL_WIDTH +: COL_WIDTH] <= din[i*COL_WIDTH +:COL_WIDTH]; RAM[addr][i*COL_WIDTH +: COL_WIDTH] <= din[i*COL_WIDTH +:COL_WIDTH];
end end
end end

12
pipelined/src/generic/flop/bram2p1r1w.sv
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@ -46,11 +46,11 @@ module bram2p1r1w
//---------------------------------------------------------------------- //----------------------------------------------------------------------
) ( ) (
input logic clk, input logic clk,
input logic enaA, input logic reA,
input logic [ADDR_WIDTH-1:0] addrA, input logic [ADDR_WIDTH-1:0] addrA,
output logic [DATA_WIDTH-1:0] doutA, output logic [DATA_WIDTH-1:0] doutA,
input logic enaB, input logic weB,
input logic [NUM_COL-1:0] weB, input logic [NUM_COL-1:0] bweB,
input logic [ADDR_WIDTH-1:0] addrB, input logic [ADDR_WIDTH-1:0] addrB,
input logic [DATA_WIDTH-1:0] dinB input logic [DATA_WIDTH-1:0] dinB
); );
@ -128,15 +128,15 @@ module bram2p1r1w
// Port-A Operation // Port-A Operation
always @ (posedge clk) begin always @ (posedge clk) begin
if(enaA) begin if(reA) begin
doutA <= RAM[addrA]; doutA <= RAM[addrA];
end end
end end
// Port-B Operation: // Port-B Operation:
always @ (posedge clk) begin always @ (posedge clk) begin
if(enaB) begin if(weB) begin
for(i=0;i<NUM_COL;i=i+1) begin for(i=0;i<NUM_COL;i=i+1) begin
if(weB[i]) begin if(bweB[i]) begin
RAM[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +:COL_WIDTH]; RAM[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +:COL_WIDTH];
end end
end end

2
pipelined/src/generic/flop/simpleram.sv
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@ -43,6 +43,6 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
localparam OFFSET = $clog2(`XLEN/8); localparam OFFSET = $clog2(`XLEN/8);
bram1p1rw #(`XLEN/8, 8, ADDR_WDITH) bram1p1rw #(`XLEN/8, 8, ADDR_WDITH)
memory(.clk, .en(we), .we(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd)); memory(.clk, .we, .bwe(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd));
endmodule endmodule

24
pipelined/src/uncore/ram.sv
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@ -97,10 +97,30 @@ module ram #(parameter BASE=0, RANGE = 65535) (
HWADDR <= #1 A; HWADDR <= #1 A;
bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA) bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA)
memory(.clk(HCLK), .enaA(1'b1), memory(.clk(HCLK), .reA(1'b1),
.addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam), .addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam),
.enaB(memwrite & risingHREADYRam), .weB(ByteMaskM), .weB(memwrite & risingHREADYRam), .bweB(ByteMaskM),
.addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA)); .addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA));
/*
bram1p1r1w #(`XLEN/8, 8, ADDR_WDITH)
memory(.clk(HCLK), .we(memwrite), .bwe(ByteMaskM), . addr(A***), .dout(HREADRam), .din(HWDATA));
#(
//--------------------------------------------------------------------------
parameter NUM_COL = 8,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input logic clk,
input logic ena,
input logic [NUM_COL-1:0] we,
input logic [ADDR_WIDTH-1:0] addr,
output logic [DATA_WIDTH-1:0] dout,
input logic [DATA_WIDTH-1:0] din
);*/
endmodule endmodule

4
pipelined/src/uncore/ram_orig.sv
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@ -97,9 +97,9 @@ module ram_orig #(parameter BASE=0, RANGE = 65535) (
HWADDR <= #1 A; HWADDR <= #1 A;
bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA) bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA)
memory(.clk(HCLK), .enaA(1'b1), memory(.clk(HCLK), .reA(1'b1),
.addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam), .addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam),
.enaB(memwrite & risingHREADYRam), .weB(ByteMaskM), .weB(memwrite & risingHREADYRam), .bweB(ByteMaskM),
.addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA)); .addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA));