Merge branch 'main' of https://github.com/openhwgroup/cvw into main

.gitignore

@@ -119,3 +119,55 @@ tests/coverage/*.elf
 sim/*Cache.log
 sim/branch
 tests/fp/combined_IF_vectors/IF_vectors/*.tv
+/sim/branch-march14.tar.gz
+/sim/gshareforward-no-class
+/sim/lint-wally_32
+/sim/lint-wally_32e
+/sim/local16.txt
+/sim/localhistory_m6k10_results_april24.txt
+/sim/log.log
+/sim/obj_dir/Vtestbench.cpp
+/sim/obj_dir/Vtestbench.h
+/sim/obj_dir/Vtestbench.mk
+/sim/obj_dir/Vtestbench__ConstPool_0.cpp
+/sim/obj_dir/Vtestbench__Syms.cpp
+/sim/obj_dir/Vtestbench__Syms.h
+/sim/obj_dir/Vtestbench___024root.h
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
+/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
+/sim/obj_dir/Vtestbench___024root__Slow.cpp
+/sim/obj_dir/Vtestbench___024unit.h
+/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
+/sim/obj_dir/Vtestbench___024unit__Slow.cpp
+/sim/obj_dir/Vtestbench__verFiles.dat
+/sim/obj_dir/Vtestbench_classes.mk
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
+/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
+/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp

.gitmodules

@@ -24,3 +24,6 @@
 [submodule "addins/branch-predictor-simulator"]
 	path = addins/branch-predictor-simulator
 	url = https://github.com/synxlin/branch-predictor-simulator.git
+[submodule "addins/FreeRTOS-Kernel"]
+	path = addins/FreeRTOS-Kernel
+	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git

addins/FreeRTOS-Kernel

@@ -0,0 +1 @@
+Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31

benchmarks/embench/Makefile

@@ -16,10 +16,18 @@ buildsize: build_speedopt_size build_sizeopt_size
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
 build_speedopt_speed:
 	$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" 
+	# remove files not used in embench1.0  When changing to 2.0, restore these files		
+	#rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum
+	#rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind
+	#rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount	
 	find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 build_sizeopt_speed:
 	$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" 
+	# remove files not used in embench1.0  When changing to 2.0, restore these files		
+	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum
+	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind
+	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount	
 	find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size

config/buildroot/config.vh

@@ -49,7 +49,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
-
+localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/fpga/config.vh

@@ -0,0 +1,175 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// include shared configuration
+`include "BranchPredictorType.vh"
+
+localparam FPGA = 1;
+localparam QEMU = 0;
+
+// RV32 or RV64: XLEN = 32 or 64
+localparam XLEN = 32'd64;
+
+// IEEE 754 compliance
+localparam IEEE754 = 0;
+
+// MISA RISC-V configuration per specification
+localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
+localparam ZICSR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam ZFH_SUPPORTED = 0;
+localparam SSTC_SUPPORTED = 0;
+localparam ZICBOM_SUPPORTED = 0;
+localparam ZICBOZ_SUPPORTED = 0;
+localparam ZICBOP_SUPPORTED = 0;
+localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
+
+// LSU microarchitectural Features
+localparam BUS_SUPPORTED = 1;
+localparam DCACHE_SUPPORTED = 1;
+localparam ICACHE_SUPPORTED = 1;
+localparam VIRTMEM_SUPPORTED = 1;
+localparam VECTORED_INTERRUPTS_SUPPORTED = 1;
+localparam BIGENDIAN_SUPPORTED = 1;
+
+// TLB configuration.  Entries should be a power of 2
+localparam ITLB_ENTRIES = 32'd32;
+localparam DTLB_ENTRIES = 32'd32;
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+localparam DCACHE_NUMWAYS = 32'd4;
+localparam DCACHE_WAYSIZEINBYTES = 32'd4096;
+localparam DCACHE_LINELENINBITS = 32'd512;
+localparam ICACHE_NUMWAYS = 32'd4;
+localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
+localparam ICACHE_LINELENINBITS = 32'd512;
+
+// Integer Divider Configuration
+// IDIV_BITSPERCYCLE must be 1, 2, or 4
+localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_ON_FPU = 1;
+
+// Legal number of PMP entries are 0, 16, or 64
+localparam PMP_ENTRIES = 32'd16;
+
+// Address space
+localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000;
+
+// Bus Interface width
+localparam AHBW = 32'd64;
+
+// WFI Timeout Wait
+localparam WFI_TIMEOUT_BIT = 32'd16;
+
+// Peripheral Physical Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+localparam DTIM_SUPPORTED = 1'b0;
+localparam logic [63:0] DTIM_BASE =       64'h80000000;
+localparam logic [63:0] DTIM_RANGE =      64'h00001FFF;
+
+localparam IROM_SUPPORTED = 1'b0;
+localparam logic [63:0] IROM_BASE =       64'h80000000;
+localparam logic [63:0] IROM_RANGE =      64'h00001FFF;
+
+localparam BOOTROM_SUPPORTED = 1'b1;
+localparam logic [63:0] BOOTROM_BASE =   64'h00001000;
+localparam logic [63:0] BOOTROM_RANGE =  64'h00000FFF;
+
+localparam UNCORE_RAM_SUPPORTED = 1'b0;
+localparam logic [63:0] UNCORE_RAM_BASE =       64'h80000000;
+localparam logic [63:0] UNCORE_RAM_RANGE =      64'h7FFFFFFF;
+
+localparam EXT_MEM_SUPPORTED = 1'b1;
+localparam logic [63:0] EXT_MEM_BASE =       64'h80000000;
+localparam logic [63:0] EXT_MEM_RANGE =      64'h07FFFFFF;
+
+localparam CLINT_SUPPORTED = 1'b1;
+localparam logic [63:0] CLINT_BASE =  64'h02000000;
+localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF;
+
+localparam GPIO_SUPPORTED = 1'b1;
+localparam logic [63:0] GPIO_BASE =   64'h10060000;
+localparam logic [63:0] GPIO_RANGE =  64'h000000FF;
+
+localparam UART_SUPPORTED = 1'b1;
+localparam logic [63:0] UART_BASE =   64'h10000000;
+localparam logic [63:0] UART_RANGE =  64'h00000007;
+
+localparam PLIC_SUPPORTED = 1'b1;
+localparam logic [63:0] PLIC_BASE =   64'h0C000000;
+localparam logic [63:0] PLIC_RANGE =  64'h03FFFFFF;
+
+localparam SDC_SUPPORTED = 1'b1;
+localparam logic [63:0] SDC_BASE =   64'h00012100;
+localparam logic [63:0] SDC_RANGE =  64'h0000001F;
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+localparam GPIO_LOOPBACK_TEST = 0;
+
+// Hardware configuration
+localparam UART_PRESCALE = 32'd0;
+
+// Interrupt configuration
+localparam PLIC_NUM_SRC = 32'd53;
+// comment out the following if >=32 sources
+localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
+localparam PLIC_GPIO_ID = 32'd3;
+localparam PLIC_UART_ID = 32'd10;
+
+localparam BPRED_SUPPORTED = 1;
+localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+localparam BPRED_NUM_LHR = 32'd6;
+localparam BPRED_SIZE = 32'd12;
+localparam BTB_SIZE = 32'd10;
+
+localparam SVADU_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED = 0;
+
+// FPU division architecture
+localparam RADIX = 32'h4;
+localparam DIVCOPIES = 32'h4;
+
+// bit manipulation
+localparam ZBA_SUPPORTED = 1;
+localparam ZBB_SUPPORTED = 1;
+localparam ZBC_SUPPORTED = 1;
+localparam ZBS_SUPPORTED = 1;
+
+// Memory synthesis configuration
+localparam USE_SRAM = 0;
+
+`include "test-shared.vh"

config/rv32e/config.vh

@@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv32gc/config.vh

@@ -50,6 +50,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv32i/config.vh

@@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;

config/rv32imc/config.vh

@@ -48,6 +48,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv64fpquad/config.vh

@@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv64gc/config.vh

@@ -52,6 +52,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 1;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;

config/rv64i/config.vh

@@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
 localparam SVPBMT_SUPPORTED = 0;
+localparam SVINVAL_SUPPORTED = 0;
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;

config/shared/parameter-defs.vh

@@ -24,6 +24,7 @@ parameter cvw_t P = '{
   ZICBOZ_SUPPORTED :     ZICBOZ_SUPPORTED,
   ZICBOP_SUPPORTED :     ZICBOP_SUPPORTED,
   SVPBMT_SUPPORTED :     SVPBMT_SUPPORTED,
+  SVINVAL_SUPPORTED :    SVINVAL_SUPPORTED,
   BUS_SUPPORTED :        BUS_SUPPORTED,
   DCACHE_SUPPORTED :     DCACHE_SUPPORTED,
   ICACHE_SUPPORTED :     ICACHE_SUPPORTED,

config/shared/test-shared.vh

@@ -93,7 +93,7 @@ localparam FMT2  = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0    : 2'd2);
 localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
 
 // division constants
-localparam DIVN        = (((NF<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2); // standard length of input
+localparam DIVN        = (((NF+2<XLEN) & IDIV_ON_FPU) ? XLEN : NF+2); // standard length of input
 localparam LOGR        = ($clog2(RADIX));           // r = log(R)
 localparam RK          = (LOGR*DIVCOPIES);         // r*k used for intdiv preproc
 localparam LOGRK       = ($clog2(RK));               // log2(r*k)

fpga/constraints/small-debug.xdc

@@ -21,32 +21,32 @@ connect_debug_port u_ila_0/clk [get_nets CPUCLK]
 
 set_property port_width 64 [get_debug_ports u_ila_0/probe0]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe1]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]]
+connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe2]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]]
+connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe3]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe4]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe5]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]]
+connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 28 [get_debug_ports u_ila_0/probe6]
@@ -131,7 +131,7 @@ connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe22]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
 
 # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
 #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]

fpga/constraints/vcu-small-debug.xdc

@@ -0,0 +1,52 @@
+create_debug_core u_ila_0 ila
+
+set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+startgroup 
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
+endgroup
+connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
+
+set_property port_width 64 [get_debug_ports u_ila_0/probe0]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe1]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe2]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe4]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe6]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
+

fpga/generator/wally.tcl

@@ -12,6 +12,17 @@ if {$boardName!="ArtyA7"} {
     set_property board_part $boardName [current_project]
 }
 
+# read package first
+read_verilog -sv  ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
+read_verilog -sv  ../src/wallypipelinedsocwrapper.sv
+# then read top level
+if {$board=="ArtyA7"} {
+    read_verilog  {../src/fpgaTopArtyA7.v}
+} else {
+    read_verilog  {../src/fpgaTop.v}
+}
+
+# read in ip
 read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
 read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
 read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
@@ -23,17 +34,13 @@ if {$board=="ArtyA7"} {
     read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
 }
 
+# read in all other rtl
 read_verilog -sv [glob -type f  ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
-if {$board=="ArtyA7"} {
+
-    read_verilog  {../src/fpgaTopArtyA7.v}
-} else {
-    read_verilog  {../src/fpgaTop.v}
-}
 read_verilog -sv  [glob -type f ../src/sdc/*.sv]
 
 set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
 
-
 if {$board=="ArtyA7"} {
     add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
     set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints-$board.xdc]
@@ -45,7 +52,6 @@ if {$board=="ArtyA7"} {
 # define top level
 set_property top fpgaTop [current_fileset]
 
-
 update_compile_order -fileset sources_1
 # This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on.
 exec mkdir -p reports/
@@ -77,7 +83,7 @@ if {$board=="ArtyA7"} {
     source ../constraints/small-debug.xdc
 
 } else {
-    source ../constraints/debug4.xdc
+    source ../constraints/vcu-small-debug.xdc
 }
 
 

fpga/src/fpgaTop.v

@@ -24,8 +24,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module fpgaTop 
   (input           default_250mhz_clk1_0_n,
    input 		   default_250mhz_clk1_0_p, 
@@ -72,12 +70,12 @@ module fpgaTop
   
   wire 			   HCLKOpen;
   wire 			   HRESETnOpen;
-  wire [`AHBW-1:0] HRDATAEXT;
+  wire [64-1:0] HRDATAEXT;
   wire 			   HREADYEXT;
   wire 			   HRESPEXT;
   wire 			   HSELEXT;
   wire [31:0] 	   HADDR;
-  wire [`AHBW-1:0] HWDATA;
+  wire [64-1:0] HWDATA;
   wire 			   HWRITE;
   wire [2:0] 	   HSIZE;
   wire [2:0] 	   HBURST;
@@ -211,7 +209,7 @@ module fpgaTop
   
 
   // wally
-  wallypipelinedsoc wallypipelinedsoc
+  wallypipelinedsocwrapper wallypipelinedsocwrapper
     (.clk(CPUCLK),
      .reset_ext(bus_struct_reset),
      // bus interface

fpga/src/wallypipelinedsocwrapper.sv

@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// wallypipelinedsocwrapper.sv
+//
+// Written: Ross Thompson ross1728@gmail.com 16 June 2023
+// Modified: 
+//
+// Purpose: A wrapper to set parameters.  Vivado cannot set the top level parameters because it only supports verilog,
+//          not system verilog.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "config.vh"
+
+import cvw::*;
+
+module wallypipelinedsocwrapper (
+  input  logic                clk, 
+  input  logic                reset_ext,        // external asynchronous reset pin
+  output logic                reset,            // reset synchronized to clk to prevent races on release
+  // AHB Interface
+  input  logic [64-1:0]     HRDATAEXT,
+  input  logic                HREADYEXT, HRESPEXT,
+  output logic                HSELEXT,
+  // outputs to external memory, shared with uncore memory
+  output logic                HCLK, HRESETn,
+  output logic [64-1:0]  HADDR,
+  output logic [64-1:0]     HWDATA,
+  output logic [64/8-1:0]   HWSTRB,
+  output logic                HWRITE,
+  output logic [2:0]          HSIZE,
+  output logic [2:0]          HBURST,
+  output logic [3:0]          HPROT,
+  output logic [1:0]          HTRANS,
+  output logic                HMASTLOCK,
+  output logic                HREADY,
+  // I/O Interface
+  input  logic                TIMECLK,          // optional for CLINT MTIME counter
+  input  logic [31:0]         GPIOIN,           // inputs from GPIO
+  output logic [31:0]         GPIOOUT,          // output values for GPIO
+  output logic [31:0]         GPIOEN,           // output enables for GPIO
+  input  logic                UARTSin,          // UART serial data input
+  output logic                UARTSout,         // UART serial data output
+  input  logic                SDCCmdIn,         // SDC Command input
+  output logic                SDCCmdOut,        // SDC Command output
+  output logic                SDCCmdOE,         // SDC Command output enable
+  input  logic [3:0]          SDCDatIn,         // SDC data input
+  output logic                SDCCLK            // SDC clock
+);
+  `include "parameter-defs.vh"
+
+  wallypipelinedsoc  #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+endmodule

sim/FPbuild.txt

@@ -34,18 +34,14 @@ other FP tests given by the great SoftFloat/TestFloat output.
 
 4a.) Each test will test all its vectors - if you want to test a
 subset of the vectors (e.g., only binary16), you should modify the
-cvw/testbench/tests-fp.h and comment out the tests  you do not want to
+testfloat.do in the sim directory.  Change the TEST_SIZE="all" to the
-test.  The best way to do this is to comment out each item out with
+specific test you want to run.  For example, if you want to run only
-the // comment option in SV.  For example,
+binary16, you should set this variable to TEST_SIZE="HP".
-
-string f128div[] = '{
-//	"f128_div_rne.tv",
-//	"f128_div_rz.tv",
-//	"f128_div_ru.tv",
-//	"f128_div_rd.tv",
-//	"f128_div_rnm.tv"
-};
 
+4b.) If you want to turn off the generation of wlf files while running
+sim-testfloat-batch, you can modify testfloat.do in the sim
+directory.  Inside this DO file, modify the WAV file to 0 --> i.e.,
+set "quietly set WAV 0;"
 
 
 

sim/sim-testfloat-batch

@@ -10,6 +10,4 @@
 # sqrt   - test square root
 # all    - test everything
 
-# nowave for 2nd argument supresses wlf files
+vsim -c -do "do testfloat.do rv64fpquad $1"
-
-vsim -c -do "do testfloat.do rv64fpquad $1 $2"

sim/testfloat.do

@@ -25,14 +25,18 @@ vlib work
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 # $num = the added words after the call
-vlog +incdir+../config/$1 +incdir+../config/shared ../src/wally/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
+vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv  ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 
 
-vsim -voptargs=+acc work.testbenchfp -G TEST=$2
+# Change TEST_SIZE to only test certain FP width
+# values are QP, DP, SP, HP
+vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" 
 
-# Determine if nowave argument is provided
+# Set WAV variable to avoid having any output to wave (to limit disk space)
-#   this removes any output to a wlf or wave window to reduce
+quietly set WAV 1;
-#   disk space.
+
-if {($argc > 2) && ($3 eq "nowave")} {
+# Determine if nowave argument is provided this removes any output to
+# a wlf or wave window to reduce disk space.
+if {$WAV eq 0} {
     puts "No wave output is selected"
 } else {
     puts "wave output is selected"

sim/wally.xrun

@@ -0,0 +1,2 @@
+xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv
+xrun -elaborate -top testbench ../testbench/testbench.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench

sim/wave-fpu.do

@@ -7,8 +7,15 @@ add wave -noupdate /testbenchfp/Y
 add wave -noupdate /testbenchfp/Z
 add wave -noupdate /testbenchfp/Res
 add wave -noupdate /testbenchfp/Ans
+add wave -noupdate /testbenchfp/reset
 add wave -noupdate /testbenchfp/DivStart
 add wave -noupdate /testbenchfp/FDivBusyE
+add wave -noupdate /testbenchfp/CheckNow
+add wave -noupdate /testbenchfp/DivDone
+add wave -noupdate /testbenchfp/ResMatch
+add wave -noupdate /testbenchfp/FlagMatch
+add wave -noupdate /testbenchfp/CheckNow
+add wave -noupdate /testbenchfp/NaNGood
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
 add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*

sim/wave.do

@@ -11,37 +11,37 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
 add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
-add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
-add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
-add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
-add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
-add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
@@ -74,26 +74,27 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
 add wave -noupdate -group {WriteBack stage} /testbench/PCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
+add wave -noupdate -expand -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
-add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
 add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
 add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
@@ -520,8 +521,8 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
 add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
-add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -group {Performance Counters} -label MCYCLE -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
-add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
 add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
 add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
 add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
@@ -594,26 +595,19 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY
 add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA
 add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB
 add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE
-add wave -noupdate /testbench/LoadMem
+add wave -noupdate /testbench/dut/core/priv/priv/privmode/PrivilegeModeW
-add wave -noupdate /testbench/CurrState
+add wave -noupdate /testbench/dut/core/priv/priv/STATUS_MIE
-add wave -noupdate /testbench/DCacheFlushStart
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/InstrMName
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/c/InstrValidM
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/clk
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrValidW
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/PCW
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrRawW
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -expand -group rvvi /testbench/wallyTracer/valid
-add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/ecf
-add wave -noupdate /testbench/ecf
-add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/ce
-add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/we
-add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/addr
-add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/dout
-add wave -noupdate /testbench/reset
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {320072 ns} 0} {{Cursor 4} {19809168 ns} 1}
+WaveRestoreCursors {{Cursor 4} {6170 ns} 0} {{Cursor 4} {19809168 ns} 1}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -629,4 +623,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {319935 ns} {320329 ns}
+WaveRestoreZoom {6124 ns} {6284 ns}

src/cache/cacheway.sv

@@ -124,7 +124,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
 
   genvar               words;
 
-  localparam           SRAMLEN = 128;
+  localparam           SRAMLEN = 128;             // *** make this a global parameter
   localparam           NUMSRAM = LINELEN/SRAMLEN;
   localparam           SRAMLENINBYTES = SRAMLEN/8;
   localparam           LOGNUMSRAM = $clog2(NUMSRAM);

src/cvw.sv

@@ -61,6 +61,7 @@ typedef struct packed {
   logic         ZICBOZ_SUPPORTED;
   logic         ZICBOP_SUPPORTED;
   logic         SVPBMT_SUPPORTED;
+  logic         SVINVAL_SUPPORTED;
 
   // Microarchitectural Features
   logic         BUS_SUPPORTED;

src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -38,7 +38,6 @@ module fdivsqrtfgen2 import cvw::*;  #(parameter cvw_t P) (
   assign FN = (UM << 1) | (C & ~(C << 2));
   assign FZ = '0;
 
-
   always_comb     // Choose which adder input will be used
     if (up)       F = FP;
     else if (uz)  F = FZ;

src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -55,7 +55,7 @@ module fdivsqrtfsm import cvw::*;  #(parameter cvw_t P) (
   assign FDivBusyE = (state == BUSY) | IFDivStartE; 
  
   // terminate immediately on special cases
-  assign FSpecialCaseE = XZeroE | | XInfE  | XNaNE |  (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
+  assign FSpecialCaseE = XZeroE | XInfE  | XNaNE |  (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE;
   if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
   else              assign SpecialCaseE = FSpecialCaseE;
   flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc

src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -63,7 +63,7 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   // Otherwise, the divisor is retained and the residual and result
   // are fed back for the next iteration.
  
-  // Residual WS/SC registers/initializaiton mux
+  // Residual WS/SC registers/initialization mux
   mux2   #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN);
   mux2   #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN);
   flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);

src/ieu/controller.sv

@@ -32,6 +32,8 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // Decode stage control signals
   input  logic        StallD, FlushD,          // Stall, flush Decode stage
   input  logic [31:0] InstrD,                  // Instruction in Decode stage
+  input  logic [1:0]  STATUS_FS,               // is FPU enabled?
+  input  logic [3:0]  ENVCFG_CBE,              // Cache block operation enables
   output logic [2:0]  ImmSrcD,                 // Type of immediate extension
   input  logic        IllegalIEUFPUInstrD,     // Illegal IEU and FPU instruction
   output logic        IllegalBaseInstrD,       // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
@@ -60,6 +62,9 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
   output logic        BMUActiveE,              // Bit manipulation instruction being executed
   output logic        MDUActiveE,              // Mul/Div instruction being executed
+  output logic [3:0]  CMOpM,                   // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  output logic        IFUPrefetchE,            // instruction prefetch
+  output logic        LSUPrefetchM,            // data prefetch
 
   // Memory stage control signals
   input  logic        StallM, FlushM,          // Stall, flush Memory stage
@@ -80,16 +85,18 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        StoreStallD              // Store (memory write) causes stall
 );
 
+
   logic [6:0] OpD;                             // Opcode in Decode stage
   logic [2:0] Funct3D;                         // Funct3 field in Decode stage
   logic [6:0] Funct7D;                         // Funct7 field in Decode stage
-  logic [4:0] Rs1D;                            // Rs1 source register in Decode stage
+  logic [4:0] Rs1D, Rs2D, RdD;                 // Rs1/2 source register / dest reg in Decode stage
 
-  `define CTRLW 23
+  `define CTRLW 24
 
   // pipelined control signals
   logic        RegWriteD, RegWriteE;           // RegWrite (register will be written)
   logic [2:0]  ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
+  logic [2:0]  PreImmSrcD;                     // Immediate source format (before amending for prefetches)
   logic [1:0]  MemRWD, MemRWE;                 // Store (write to memory)
   logic        ALUOpD;                         // 0 for address generation, 1 for all other operations (must use Funct3)
   logic        BaseW64D;                       // W64 for Base instructions specifically
@@ -103,6 +110,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic        CSRReadD;                       // CSR read instruction
   logic [1:0]  AtomicD;                        // Atomic (AMO) instruction
   logic        FenceXD;                        // Fence instruction
+  logic        CMOD;                           // Cache management instruction
   logic        InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
   logic        CSRWriteD, CSRWriteE;           // CSR write
   logic        PrivilegedD, PrivilegedE;       // Privileged instruction
@@ -126,16 +134,27 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic [2:0]  ZBBSelectD;                     // ZBB Mux Select Signal
   logic        IFunctD, RFunctD, MFunctD;      // Detect I, R, and M-type RV32IM/Rv64IM instructions
   logic        LFunctD, SFunctD, BFunctD;      // Detect load, store, branch instructions
-  logic        JFunctD;                        // detect jalr instruction
+  logic        FLSFunctD;                      // Detect floating-point loads and stores
+  logic        JRFunctD;                       // detect jalr instruction
+  logic        FenceFunctD;                    // Detect fence instruction
+  logic        CMOFunctD;                      // Detect CMO instruction
+  logic        AFunctD, AMOFunctD;             // Detect atomic instructions
+  logic        RWFunctD, MWFunctD;             // detect RW/MW instructions
+  logic        PFunctD, CSRFunctD;             // detect privileged / CSR instruction
   logic        FenceM;                         // Fence.I or sfence.VMA instruction in memory stage
   logic [2:0]  ALUSelectD;                     // ALU Output selection mux control
   logic        IWValidFunct3D;                 // Detects if Funct3 is valid for IW instructions
+  logic [3:0]  CMOpD, CMOpE;                   // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  logic        IFUPrefetchD;                   // instruction prefetch
+  logic        LSUPrefetchD, LSUPrefetchE;     // data prefetch
 
   // Extract fields
   assign OpD     = InstrD[6:0];
   assign Funct3D = InstrD[14:12];
   assign Funct7D = InstrD[31:25];
   assign Rs1D    = InstrD[19:15];
+  assign Rs2D    = InstrD[24:20];
+  assign RdD     = InstrD[11:7];
 
   // Funct 7 checking
   // Be rigorous about detecting illegal instructions if CSRs or bit manipulation is supported
@@ -156,70 +175,108 @@ module controller import cvw::*;  #(parameter cvw_t P) (
     assign MFunctD          = (Funct7D == 7'b0000001) & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
     assign LFunctD          = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | 
                               ((P.XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110));
+    assign FLSFunctD        = (STATUS_FS != 2'b00) & ((Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) |
+                              (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED));
+    assign FenceFunctD      = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001);
+    assign CMOFunctD        = (Funct3D == 3'b010 & RdD == 5'b0) & 
+                              ((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4 & ENVCFG_CBE[3]) |
+                               (P.ZICBOM_SUPPORTED & ((InstrD[31:20] == 12'd0 & (ENVCFG_CBE[1:0] != 2'b00))) | 
+                                                      (InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2) & ENVCFG_CBE[2]));
+                               // *** need to get with enable bits such as MENVCFG_CBZE
+    assign AFunctD          = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011);
+    assign AMOFunctD        = (InstrD[31:27] == 5'b00001) |
+                              (InstrD[31:27] == 5'b00000) |
+                              (InstrD[31:27] == 5'b00100) |
+                              (InstrD[31:27] == 5'b01100) |
+                              (InstrD[31:27] == 5'b01000) |
+                              (InstrD[31:27] == 5'b10000) |
+                              (InstrD[31:27] == 5'b10100) |
+                              (InstrD[31:27] == 5'b11000) |
+                              (InstrD[31:27] == 5'b11100);
+    assign RWFunctD         = ((Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101) & Funct7ZeroD |
+                              (Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) & (P.XLEN == 64);
+    assign MWFunctD         = MFunctD & (P.XLEN == 64) & ~(Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b011);
     assign SFunctD          = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | 
                               ((P.XLEN == 64) & (Funct3D == 3'b011));
-    assign BFunctD          = (Funct3D[2:1] != 2'b01); // legal branches
+    assign BFunctD          = Funct3D[2:1] != 2'b01; // legal branches
-    assign JFunctD          = (Funct3D == 3'b000);
+    assign JRFunctD         = Funct3D == 3'b000;
+    assign PFunctD          = Funct3D == 3'b000 & RdD == 5'b0;
+    assign CSRFunctD        = Funct3D[1:0] != 2'b00; 
     assign IWValidFunct3D   = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101;
   end else begin:legalcheck2
     assign IFunctD = 1; // Don't bother to separate out shift decoding
     assign RFunctD = ~Funct7D[0]; // Not a multiply
     assign MFunctD = Funct7D[0] & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv
     assign LFunctD = 1; // don't bother to check Funct3 for loads
+    assign FLSFunctD = 1; // don't bother to check Func3 for floating-point loads/stores
+    assign FenceFunctD = 1; // don't bother to check fields for fences
+    assign CMOFunctD = 1; // don't bother to check fields for CMO instructions
+    assign AFunctD = 1; // don't bother to check fields for atomics
+    assign AMOFunctD = 1; // don't bother to check Funct7 for AMO operations
+    assign RWFunctD = 1; // don't bother to check fields for RW instructions
+    assign MWFunctD = 1; // don't bother to check fields for MW instructions
     assign SFunctD = 1; // don't bother to check Funct3 for stores
     assign BFunctD = 1; // don't bother to check Funct3 for branches
-    assign JFunctD = 1; // don't bother to check Funct3 for jumps
+    assign JRFunctD = 1; // don't bother to check Funct3 for jalrs
+    assign PFunctD = 1; // don't bother to check fields for privileged instructions
+    assign CSRFunctD = 1; // don't bother to check Funct3 for CSR operations
     assign IWValidFunct3D = 1;
   end
 
   // Main Instruction Decoder
   /* verilator lint_off CASEINCOMPLETE */
   always_comb begin
-    ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // default: Illegal instruction
+    ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_1; // default: Illegal instruction
     case(OpD)
-    // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
+    // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_CMO_Illegal
       7'b0000011: if (LFunctD) 
-                      ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // loads
+                      ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_0; // loads
-      7'b0000111:     ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported
+      7'b0000111: if (FLSFunctD)  
-      7'b0001111: if (P.ZIFENCEI_SUPPORTED)
+                      ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_1; // flw - only legal if FP supported
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
+      7'b0001111: if (FenceFunctD) begin
+                    if (P.ZIFENCEI_SUPPORTED)
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0_0; // fence
                     else
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // fence treated as nop
+                  end else if (CMOFunctD) begin
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1_0; // CMO Instruction
+                  end
       7'b0010011: if (IFunctD)    
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // I-type ALU
-      7'b0010111:     ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
+      7'b0010111:     ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // auipc
       7'b0011011: if (IFunctD & IWValidFunct3D & P.XLEN == 64)
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // IW-type ALU for RV64i
       7'b0100011: if (SFunctD) 
-                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores
+                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores
-      7'b0100111:     ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported
+      7'b0100111: if (FLSFunctD)
-      7'b0101111: if (P.A_SUPPORTED) begin
+                      ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported
-                    if (InstrD[31:27] == 5'b00010)
+      7'b0101111: if (P.A_SUPPORTED & AFunctD) begin
-                      ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
+                    if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0)
+                      ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr
                     else if (InstrD[31:27] == 5'b00011)
-                      ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc
+                      ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc
-                    else 
+                    else if (AMOFunctD) 
-                      ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo
+                      ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo
                  end
       7'b0110011: if (RFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type 
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // R-type 
                   else if (MFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0_0; // Multiply/divide
-      7'b0110111:     ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
+      7'b0110111:     ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0_0; // lui
-      7'b0111011: if (RFunctD & (P.XLEN == 64))
+      7'b0111011: if (RWFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // R-type W instructions for RV64i
-                  else if (MFunctD & (P.XLEN == 64))
+                  else if (MWFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0_0; // W-type Multiply/Divide
       7'b1100011: if (BFunctD)   
-                      ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
+                      ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0_0; // branches
-      7'b1100111: if (JFunctD)
+      7'b1100111: if (JRFunctD)
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jalr
-      7'b1101111:     ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
+      7'b1101111:     ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jal
       7'b1110011: if (P.ZICSR_SUPPORTED) begin
-                   if (Funct3D == 3'b000)
+                   if (PFunctD)
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0_0; // privileged; decoded further in privdec modules
-                   else
+                   else if (CSRFunctD)
-                      ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
+                      ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0_0; // csrs
                   end
     endcase
   end
@@ -230,9 +287,9 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // On RV32E, can't write to upper 16 registers.  Checking reads to upper 16 is more costly so disregard them.
   assign IllegalERegAdrD = P.E_SUPPORTED & P.ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; 
   //assign IllegalBaseInstrD = 1'b0;
-  assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD,
+  assign {BaseRegWriteD, PreImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD,
           ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, 
-          PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
+          PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
   
   assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
   assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]);            // Don't write if setting or clearing zeros
@@ -300,13 +357,41 @@ module controller import cvw::*;  #(parameter cvw_t P) (
     assign FlushDCacheD = 0;
   end
 
+  // Cache Management instructions
+  always_comb begin
+    CMOpD = 4'b0000; // default: not a cbo instruction
+    if ((P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) & CMOD) begin
+      CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero
+      CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean
+      CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush 
+      CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval
+    end 
+  end
+
+  // Prefetch Hints
+  always_comb begin
+    // default: not a prefetch hint
+    IFUPrefetchD = 1'b0;
+    LSUPrefetchD = 1'b0;
+    ImmSrcD = PreImmSrcD;
+    if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destiation x0 is hint for Prefetch
+      case (Rs2D) // which type of prefectch?  Note: prefetch.r and .w are handled the same in Wally
+        5'b00000: IFUPrefetchD = 1'b1; // prefetch.i
+        5'b00001: LSUPrefetchD = 1'b1; // prefetch.r
+        5'b00011: LSUPrefetchD = 1'b1; // prefetch.w
+        // default: not a prefetch hint
+      endcase
+      if (IFUPrefetchD | LSUPrefetchD) ImmSrcD = 3'b001; // use S-type immediate format for prefetches
+    end
+  end
+
   // Decode stage pipeline control register
   flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
 
   // Execute stage pipeline control register and logic
-  flopenrc #(29) controlregE(clk, reset, FlushE, ~StallE,
+  flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE,
-                           {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD},
+                           {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, InstrValidD},
-                           {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE});
+                           {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, InstrValidE});
 
   // Branch Logic
   //  The comparator handles both signed and unsigned branches using BranchSignedE
@@ -325,9 +410,9 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
   
   // Memory stage pipeline control register
-  flopenrc #(20) controlregM(clk, reset, FlushM, ~StallM,
+  flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
-                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE},
+                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
-                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM});
+                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
   
   // Writeback stage pipeline control register
   flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
@@ -339,5 +424,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
 
   // the synchronous DTIM cannot read immediately after write
   // a cache cannot read or write immediately after a write
-  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)) | (|AtomicD));
+  // atomic operations are also detected as MemRWD[1]
+  assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
 endmodule

src/ieu/datapath.sv

@@ -98,7 +98,7 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   assign Rs2D      = InstrD[24:20];
   assign RdD       = InstrD[11:7];
   regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
-  extend  #(P.XLEN, P.A_SUPPORTED) ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
+  extend #(P)        ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
  
   // Execute stage pipeline register and logic
   flopenrc #(P.XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);

src/ieu/extend.sv

@@ -27,28 +27,29 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-module extend #(parameter XLEN, A_SUPPORTED) (
+module extend import cvw::*;  #(parameter cvw_t P) (
   input  logic [31:7]       InstrD,       // All instruction bits except opcode (lower 7 bits)
   input  logic [2:0]        ImmSrcD,      // Select what kind of extension to perform
-  output logic [XLEN-1:0]   ImmExtD);    // Extended immediate
+  output logic [P.XLEN-1:0] ImmExtD);     // Extended immediate
 
-  localparam [XLEN-1:0] undefined = {(XLEN){1'bx}}; // could change to 0 after debug
+  localparam [P.XLEN-1:0] undefined = {(P.XLEN){1'bx}}; // could change to 0 after debug
  
   always_comb
-    case(ImmSrcD) 
+    case (ImmSrcD) 
       // I-type 
-      3'b000:   ImmExtD = {{(XLEN-12){InstrD[31]}}, InstrD[31:20]};  
+      3'b000:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:20]};  
       // S-type (stores)
-      3'b001:   ImmExtD = {{(XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]}; 
+      3'b001:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]};
       // B-type (branches)
-      3'b010:   ImmExtD = {{(XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; 
+      3'b010:   ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; 
       // J-type (jal)
-      3'b011:   ImmExtD = {{(XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; 
+      3'b011:   ImmExtD = {{(P.XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; 
       // U-type (lui, auipc)
-      3'b100:   ImmExtD = {{(XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 
+      3'b100:   ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 
       // Store Conditional: zero offset
-      3'b101:  if (A_SUPPORTED) ImmExtD = 0;
+      3'b101:  if (P.A_SUPPORTED) ImmExtD = 0;
                else             ImmExtD = undefined;
       default: ImmExtD = undefined; // undefined
     endcase  
+
 endmodule

src/ieu/ieu.sv

@@ -30,6 +30,8 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   input  logic              clk, reset,
   // Decode stage signals
   input  logic [31:0]       InstrD,                          // Instruction
+  input  logic [1:0]        STATUS_FS,                       // is FPU enabled?
+  input  logic [3:0]        ENVCFG_CBE,                      // Cache block operation enables
   input  logic              IllegalIEUFPUInstrD,             // Illegal instruction
   output logic              IllegalBaseInstrD,               // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
   // Execute stage signals
@@ -43,6 +45,9 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
   output logic [4:0]        RdE,                             // Destination register
   output logic              MDUActiveE,                      // Mul/Div instruction being executed
+  output logic [3:0]        CMOpM,                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  output logic              IFUPrefetchE,                    // instruction prefetch
+  output logic              LSUPrefetchM,                    // datata prefetch
   // Memory stage signals
   input  logic              SquashSCW,                       // Squash store conditional, from LSU
   output logic [1:0]        MemRWM,                          // Read/write control goes to LSU
@@ -97,11 +102,11 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   logic       BMUActiveE;                                    // Bit manipulation instruction being executed
            
   controller #(P) c(
-    .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
+    .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
     .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, 
     .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, 
-    .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE,
+    .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
     .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
     .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD);

src/lsu/lsu.sv

@@ -39,6 +39,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   input  logic [6:0]              Funct7M,                              // Atomic memory operation function
   input  logic [1:0]              AtomicM,                              // Atomic memory operation
   input  logic                    FlushDCacheM,                         // Flush D cache to next level of memory
+  input  logic [3:0]              CMOpM,                                // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  input  logic                    LSUPrefetchM,                         // Prefetch
   output logic                    CommittedM,                           // Delay interrupts while memory operation in flight
   output logic                    SquashSCW,                            // Store conditional failed disable write to GPR
   output logic                    DCacheMiss,                           // D cache miss for performance counters
@@ -260,6 +262,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0;
       assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW);
       
+      // *** need RT to add support for CMOpM and LSUPrefetchM (DH 7/2/23)
+      // *** prefetch can just act as a read operation
       cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
         .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),

src/mmu/pmpchecker.sv

@@ -67,7 +67,7 @@ module pmpchecker import cvw::*;  #(parameter cvw_t P) (
   priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 
   // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region
-  assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode
+  assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode
 
   assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
   assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;

src/privileged/csr.sv

@@ -84,6 +84,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   output var logic [7:0]           PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],
   output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0],
   output logic [2:0]               FRM_REGW, 
+  output logic [3:0]               ENVCFG_CBE,
   //
   output logic [P.XLEN-1:0]        CSRReadValW,               // value read from CSR
   output logic [P.XLEN-1:0]        UnalignedPCNextF,          // Next PC, accounting for traps and returns
@@ -123,7 +124,11 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]       TVecAlignedM;
   logic                    InstrValidNotFlushedM;
   logic                    STimerInt;
-  logic                    MENVCFG_STCE;
+  logic [63:0]             MENVCFG_REGW;
+  logic [P.XLEN-1:0]       SENVCFG_REGW;
+  logic                    ENVCFG_STCE; // supervisor timer counter enable
+  logic                    ENVCFG_PBMTE; // page-based memory types enable
+  logic                    ENVCFG_FIOM; // fence implies io (presently not used)
 
   // only valid unflushed instructions can access CSRs
   assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
@@ -214,7 +219,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   csri #(P) csri(.clk, .reset,  
     .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
     .MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
-    .MIDELEG_REGW, .MENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
+    .MIDELEG_REGW, .ENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
 
   csrsr #(P) csrsr(.clk, .reset, .StallW, 
     .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, 
@@ -233,10 +238,12 @@ module csr import cvw::*;  #(parameter cvw_t P) (
     .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
     .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
-    .MENVCFG_STCE);
+    .MENVCFG_REGW);
 
 
   if (P.S_SUPPORTED) begin:csrs
+    logic STCE; 
+    assign STCE = P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_REGW[1] & ENVCFG_STCE));
     csrs #(P) csrs(.clk, .reset,
       .CSRSWriteM, .STrapM, .CSRAdrM,
       .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, 
@@ -244,8 +251,8 @@ module csr import cvw::*;  #(parameter cvw_t P) (
       .CSRWriteValM, .PrivilegeModeW,
       .CSRSReadValM, .STVEC_REGW, .SEPC_REGW,      
       .SCOUNTEREN_REGW,
-      .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .MENVCFG_STCE,
+      .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .STCE,
-      .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt);
+      .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt, .SENVCFG_REGW);
   end else begin
     assign WriteSSTATUSM = 0;
     assign CSRSReadValM = 0;
@@ -282,6 +289,17 @@ module csr import cvw::*;  #(parameter cvw_t P) (
     assign IllegalCSRCAccessM = 1; // counters aren't enabled
   end
 
+   // Broadcast appropriate environment configuration based on privilege mode
+  assign ENVCFG_STCE =  MENVCFG_REGW[63]; // supervisor timer counter enable
+  assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable
+  assign ENVCFG_CBE =   (PrivilegeModeW == P.M_MODE) ? 4'b1111 : 
+                        (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : 
+                                                                       (MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]);
+  // FIOM presently doesn't do anything because Wally fences don't do anything
+  assign ENVCFG_FIOM =  (PrivilegeModeW == P.M_MODE) ? 1'b1 : 
+                        (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[0] : 
+                                                                       (MENVCFG_REGW[0] & SENVCFG_REGW[0]);
+
   // merge CSR Reads
   assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; 
   flopenrc #(P.XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);

src/privileged/csri.sv

@@ -34,7 +34,7 @@ module csri import cvw::*;  #(parameter cvw_t P) (
   input  logic [11:0]       CSRAdrM,
   input  logic              MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
   input  logic [11:0]       MIDELEG_REGW,
-  input  logic              MENVCFG_STCE,
+  input  logic              ENVCFG_STCE,
   output logic [11:0]       MIP_REGW, MIE_REGW,
   output logic [11:0]       MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
 );
@@ -61,7 +61,7 @@ module csri import cvw::*;  #(parameter cvw_t P) (
   if (P.S_SUPPORTED) begin:mask
     if (P.SSTC_SUPPORTED) begin
       assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec)
-      assign STIP = MENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5];
+      assign STIP = ENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5];
     end else begin
       assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
       assign STIP = MIP_REGW_writeable[5];

src/privileged/csrm.sv

@@ -48,18 +48,15 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],
   output logic                     WriteMSTATUSM, WriteMSTATUSHM,
   output logic                     IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM,
-  output logic                     MENVCFG_STCE
+  output logic [63:0]              MENVCFG_REGW
 );
 
   logic [P.XLEN-1:0]               MISA_REGW, MHARTID_REGW;
   logic [P.XLEN-1:0]               MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
-  logic [63:0]                     MENVCFG_REGW;
   logic [P.XLEN-1:0]               MENVCFGH_REGW;
-  logic [63:0]                     MENVCFG_PreWriteValM, MENVCFG_WriteValM;
   logic                            WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
   logic                            WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
   logic                            WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
-  logic                            WriteMENVCFGM;
 
   // Machine CSRs
   localparam MVENDORID     = 12'hF11;
@@ -83,7 +80,6 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   localparam MCAUSE        = 12'h342;
   localparam MTVAL         = 12'h343;
   localparam MIP           = 12'h344;
-  localparam MTINST        = 12'h34A;
   localparam PMPCFG0       = 12'h3A0;
   // .. up to 15 more at consecutive addresses
   localparam PMPADDR0      = 12'h3B0;
@@ -147,7 +143,6 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   assign WriteMCAUSEM        = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
   assign WriteMTVALM         = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
   assign WriteMCOUNTERENM    = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
-  assign WriteMENVCFGM       = CSRMWriteM & (CSRAdrM == MENVCFG);
   assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
 
   assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
@@ -169,6 +164,11 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
     flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
   end else assign MCOUNTEREN_REGW = '0;
 
+  // MENVCFG register
+  if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control
+    logic WriteMENVCFGM;
+    logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM;
+    assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG);
     // MENVCFG is always 64 bits even for RV32
     assign MENVCFG_WriteValM = {
       MENVCFG_PreWriteValM[63]  & P.SSTC_SUPPORTED,
@@ -179,12 +179,11 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
       3'b0,
       MENVCFG_PreWriteValM[0]   & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
     };
-
     if (P.XLEN == 64) begin
       assign MENVCFG_PreWriteValM = CSRWriteValM;
       flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW);
       assign MENVCFGH_REGW = 0;
-  end else begin
+    end else begin // RV32 has high and low halves
       logic WriteMENVCFGHM;
       assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM};
       assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32);
@@ -192,21 +191,14 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
       flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]);
       assign MENVCFGH_REGW = MENVCFG_REGW[63:32];
     end
-
+  end
-  // Extract bit fields
-  assign MENVCFG_STCE =  MENVCFG_REGW[63];
-  // Uncomment these other fields when they are defined
-  // assign MENVCFG_PBMTE = MENVCFG_REGW[62];
-  // assign MENVCFG_CBZE  =  MENVCFG_REGW[7];
-  // assign MENVCFG_CBCFE = MENVCFG_REGW[6];
-  // assign MENVCFG_CBIE  =  MENVCFG_REGW[5:4];
-  // assign MENVCFG_FIOM  =  MENVCFG_REGW[0];
 
   // Read machine mode CSRs
   // verilator lint_off WIDTH
   logic [5:0] entry;
   always_comb begin
     entry = '0;
+    CSRMReadValM = 0;
     IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
     if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry
       CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]};
@@ -229,7 +221,8 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
       MHARTID:       CSRMReadValM = MHARTID_REGW; // hardwired to 0 
       MCONFIGPTR:    CSRMReadValM = 0; // hardwired to 0
       MSTATUS:       CSRMReadValM = MSTATUS_REGW;
-      MSTATUSH:      CSRMReadValM = MSTATUSH_REGW; 
+      MSTATUSH:      if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW; 
+                     else IllegalCSRMAccessM = 1;
       MTVEC:         CSRMReadValM = MTVEC_REGW;
       MEDELEG:       CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW};
       MIDELEG:       CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW};
@@ -239,16 +232,13 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
       MEPC:          CSRMReadValM = MEPC_REGW;
       MCAUSE:        CSRMReadValM = MCAUSE_REGW;
       MTVAL:         CSRMReadValM = MTVAL_REGW;
-      MTINST:        CSRMReadValM = 0; // implemented as trivial zero
       MCOUNTEREN:    CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW};
-      MENVCFG:       CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
+      MENVCFG:       if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0];
-      MENVCFGH:      CSRMReadValM = MENVCFGH_REGW;
+                     else IllegalCSRMAccessM = 1;
+      MENVCFGH:      if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW;
+                     else IllegalCSRMAccessM = 1;
       MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
-
+      default:       IllegalCSRMAccessM = 1;
-      default: begin
-                 CSRMReadValM = 0;
-                 IllegalCSRMAccessM = 1;
-      end
     endcase
   end
   // verilator lint_on WIDTH

src/privileged/csrs.sv

@@ -44,10 +44,12 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   output logic [P.XLEN-1:0] SATP_REGW,
   input  logic [11:0]       MIP_REGW, MIE_REGW, MIDELEG_REGW,
   input  logic [63:0]       MTIME_CLINT,
-  input  logic              MENVCFG_STCE,
+  input  logic              STCE,
   output logic              WriteSSTATUSM,
   output logic              IllegalCSRSAccessM,
-  output logic              STimerInt
+  output logic              STimerInt,
+  output logic [P.XLEN-1:0] SENVCFG_REGW
+
 );
 
   // Supervisor CSRs
@@ -75,7 +77,6 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   logic                    WriteSENVCFGM;
 
   logic [P.XLEN-1:0]       SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
-  logic [P.XLEN-1:0]       SENVCFG_REGW;
   logic [P.XLEN-1:0]       SENVCFG_WriteValM;
 
   logic [63:0]             STIMECMP_REGW;
@@ -90,8 +91,8 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   assign WriteSATPM       = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM);
   assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN);
   assign WriteSENVCFGM    = CSRSWriteM & (CSRAdrM == SENVCFG);
-  assign WriteSTIMECMPM   = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE));
+  assign WriteSTIMECMPM   = CSRSWriteM & (CSRAdrM == STIMECMP) & STCE;
-  assign WriteSTIMECMPHM  = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE)) & (P.XLEN == 32);
+  assign WriteSTIMECMPHM  = CSRSWriteM & (CSRAdrM == STIMECMPH) & STCE & (P.XLEN == 32);
 
   // CSRs
   flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); 
@@ -125,19 +126,11 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
     CSRWriteValM[7]   & P.ZICBOZ_SUPPORTED,
     CSRWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}},
     3'b0,
-    CSRWriteValM[0]   & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED
+    CSRWriteValM[0]   & P.VIRTMEM_SUPPORTED
   };
 
   flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW);
     
-  // Extract bit fields
-  // Uncomment these other fields when they are defined
-  // assign SENVCFG_PBMTE = SENVCFG_REGW[62];
-  // assign SENVCFG_CBZE  =  SENVCFG_REGW[7];
-  // assign SENVCFG_CBCFE = SENVCFG_REGW[6];
-  // assign SENVCFG_CBIE  =  SENVCFG_REGW[5:4];
-  // assign SENVCFG_FIOM  =  SENVCFG_REGW[0];
-    
   // CSR Reads
   always_comb begin:csrr
     IllegalCSRSAccessM = 0;
@@ -157,13 +150,13 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
                  end
       SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW};
       SENVCFG:   CSRSReadValM = SENVCFG_REGW;
-      STIMECMP:  if (P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE))) 
+      STIMECMP:  if (STCE) 
                    CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0]; 
                  else begin 
                    CSRSReadValM = 0;
                    IllegalCSRSAccessM = 1;
                  end
-      STIMECMPH: if (P.SSTC_SUPPORTED & (P.XLEN == 32) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE))) 
+      STIMECMPH: if (STCE) 
                    CSRSReadValM[31:0] = STIMECMP_REGW[63:32];
                  else begin // not supported for RV64
                    CSRSReadValM = 0;

src/privileged/csrsr.sv

@@ -54,7 +54,6 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
   // STATUS REGISTER FIELD
   // See Privileged Spec Section 3.1.6
   // Lower privilege status registers are a subset of the full status register
-  // *** consider adding MBE, SBE, UBE fields, parameterized to be fixed or adjustable
   if (P.XLEN==64) begin: csrsr64 // RV64
     assign MSTATUS_REGW  = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0,
                            STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,

src/privileged/privdec.sv

@@ -30,7 +30,7 @@
 module privdec import cvw::*;  #(parameter cvw_t P) (
   input  logic         clk, reset,
   input  logic         StallM,
-  input  logic [31:20] InstrM,                              // privileged instruction function field
+  input  logic [31:15] InstrM,                              // privileged instruction function field
   input  logic         PrivilegedM,                         // is this a privileged instruction (from IEU controller)
   input  logic         IllegalIEUFPUInstrM,                 // Not a legal IEU instruction
   input  logic         IllegalCSRAccessM,                   // Not a legal CSR access
@@ -39,24 +39,37 @@ module privdec import cvw::*;  #(parameter cvw_t P) (
   output logic         IllegalInstrFaultM,                  // Illegal instruction
   output logic         EcallFaultM, BreakpointFaultM,       // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
   output logic         sretM, mretM,                        // return instructions
-  output logic         wfiM, sfencevmaM                     // wfi / sfence.fma instructions
+  output logic         wfiM, sfencevmaM                     // wfi / sfence.vma / sinval.vma instructions
 );
 
+  logic                rs1zeroM;                            // rs1 field = 0
   logic                IllegalPrivilegedInstrM;             // privileged instruction isn't a legal one or in legal mode
   logic                WFITimeoutM;                         // WFI reaches timeout threshold
   logic                ebreakM, ecallM;                     // ebreak / ecall instructions
+  logic                sinvalvmaM;                          // sinval.vma
+  logic                sfencewinvalM, sfenceinvalirM;       // sfence.w.inval, sfence.inval.ir
+  logic                invalM;                              // any of the svinval instructions
 
   ///////////////////////////////////////////
   // Decode privileged instructions
   ///////////////////////////////////////////
 
-  assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & P.S_SUPPORTED & 
+  assign rs1zeroM =    InstrM[19:15] == 5'b0;
+  
+  // svinval instructions
+  // any svinval instruction is treated as sfence.vma on Wally
+  assign sinvalvmaM =     (InstrM[31:25] == 7'b0001001);
+  assign sfencewinvalM  = (InstrM[31:20] == 12'b000110000000) & rs1zeroM;
+  assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM;
+  assign invalM =         P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM); 
+
+  assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED & 
                       (PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR); 
-  assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == P.M_MODE);
+  assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & rs1zeroM & (PrivilegeModeW == P.M_MODE);
-  assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000);
+  assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM;
-  assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001);
+  assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM;
-  assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101);
+  assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM;
-  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001) & 
+  assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001 | invalM) & 
                       (PrivilegeModeW == P.M_MODE | (PrivilegeModeW == P.S_MODE & ~STATUS_TVM)); 
 
   ///////////////////////////////////////////

src/privileged/privileged.sv

@@ -82,6 +82,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   output var logic [7:0]    PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0],           // PMP configuration entries to MMU
   output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0],  // PMP address entries to MMU
   output logic [2:0]        FRM_REGW,                                       // FPU rounding mode
+  output logic [3:0]        ENVCFG_CBE,                                     // Cache block operation enables
   // PC logic output in privileged unit                                    
   output logic [P.XLEN-1:0] UnalignedPCNextF,                               // Next PC from trap/return PC logic
   // control outputs                                                       
@@ -117,7 +118,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
 
   // decode privileged instructions
-  privdec #(P) pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), 
+  privdec #(P) pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:15]), 
     .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, 
     .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
     .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
@@ -136,7 +137,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
     .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
     .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-    .SetFflagsM, .FRM_REGW, 
+    .SetFflagsM, .FRM_REGW, .ENVCFG_CBE,
     .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
 
   // pipeline early-arriving trap sources

src/uncore/plic_apb.sv

@@ -31,7 +31,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`define N P.PLIC_NUM_SRC
 // number of interrupt sources
 // does not include source 0, which does not connect to anything according to spec
 // up to 63 sources supported; in the future, allow up to 1023 sources
@@ -59,19 +58,20 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   logic [31:0]                Din, Dout;
 
   // context-independent signals
-  logic [`N:1]               requests;
+  logic [P.PLIC_NUM_SRC:1]               requests;
-  logic [`N:1][2:0]          intPriority;
+  logic [P.PLIC_NUM_SRC:1][2:0]          intPriority;
-  logic [`N:1]               intInProgress, intPending, nextIntPending;
+  logic [P.PLIC_NUM_SRC:1]               intInProgress, intPending, nextIntPending;
   
   // context-dependent signals
   logic [`C-1:0][2:0]        intThreshold;
-  logic [`C-1:0][`N:1]       intEn;
+  logic [`C-1:0][P.PLIC_NUM_SRC:1]       intEn;
   logic [`C-1:0][5:0]        intClaim; // ID's are 6 bits if we stay within 63 sources
-  logic [`C-1:0][7:1][`N:1]  irqMatrix;
+  logic [`C-1:0][7:1][P.PLIC_NUM_SRC:1]  irqMatrix;
   logic [`C-1:0][7:1]        priorities_with_irqs;
   logic [`C-1:0][7:1]        max_priority_with_irqs;
-  logic [`C-1:0][`N:1]       irqs_at_max_priority;
+  logic [`C-1:0][P.PLIC_NUM_SRC:1]       irqs_at_max_priority;
   logic [`C-1:0][7:1]        threshMask;
+  logic [P.PLIC_NUM_SRC-1:0] One;
 
   // =======
   // AHB I/O
@@ -81,6 +81,7 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   assign memread  = ~PWRITE & PSEL;           // read at start of access phase.  PENABLE hasn't set up before this
   assign PREADY   = 1'b1;                     // PLIC never takes >1 cycle to respond
   assign entry    = {PADDR[23:2],2'b0};
+  assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment.
 
   // account for subword read/write circuitry
   // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
@@ -92,66 +93,67 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
     assign Din    = PWDATA[31:0];
   end
 
-  if (P.PLIC_NUM_SRC_LT_32) `define PLIC_NUM_SRC_LT_32
-
   // ==================
   // Register Interface
   // ==================
+  localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31;
     
   always @(posedge PCLK) begin
     // resetting
     if (~PRESETn) begin
-      intPriority   <= #1 {`N{3'b0}};
+      intPriority   <= #1 '0;
-      intEn         <= #1 {2*`N{1'b0}};
+      intEn         <= #1 '0;
-      intThreshold  <= #1 {2{3'b0}};
+      intThreshold  <= #1 '0;
-      intInProgress <= #1 {`N{1'b0}};
+      intInProgress <= #1 '0;
     // writing
     end else begin
       if (memwrite)
         casez(entry)
           24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0];
-          `ifdef PLIC_NUM_SRC_LT_32 // eventually switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources
+          24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1];
-          24'h002000: intEn[0][`N:1]          <= #1 Din[`N:1];
+          24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1];
-          24'h002080: intEn[1][`N:1]          <= #1 Din[`N:1];
+
-          `endif
+          // verilator lint_off SELRANGE  
-          `ifndef PLIC_NUM_SRC_LT_32
+          // *** RT: Long term we want to factor out these variable number of registers as a generate loop
-          24'h002000: intEn[0][31:1]          <= #1 Din[31:1];
+          // I think this won't work as a case statement.
-          24'h002004: intEn[0][`N:32]         <= #1 Din[31:0];
+          24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32]         <= #1 Din[P.PLIC_NUM_SRC-32:0];
-          24'h002080: intEn[1][31:1]          <= #1 Din[31:1];
+          24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32]         <= #1 Din[P.PLIC_NUM_SRC-32:0];
-          24'h002084: intEn[1][`N:32]         <= #1 Din[31:0];
+          // verilator lint_on SELRANGE
-          `endif
           24'h200000: intThreshold[0]         <= #1 Din[2:0];
-          24'h200004: intInProgress           <= #1 intInProgress & ~({{`N-1{1'b0}}, 1'b1} << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+          24'h200004: intInProgress           <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
           24'h201000: intThreshold[1]         <= #1 Din[2:0];
-          24'h201004: intInProgress           <= #1 intInProgress & ~({{`N-1{1'b0}}, 1'b1} << (Din[5:0]-1)); // lower "InProgress" to signify completion 
+          24'h201004: intInProgress           <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 
         endcase
       // Read synchronously because a read can have side effect of changing intInProgress
       if (memread) begin
         casez(entry)
           24'h000000: Dout <= #1 32'b0;  // there is no intPriority[0]
           24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};      
-          `ifdef PLIC_NUM_SRC_LT_32
+          24'h001000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0};
-          24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0};
+          24'h002000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0};
-          24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0};
+
-          24'h002080: Dout <= #1 {{(31-`N){1'b0}},intEn[1],1'b0};
+          // verilator lint_off SELRANGE
-          `endif
+          // verilator lint_off WIDTHTRUNC 
-          `ifndef PLIC_NUM_SRC_LT_32
+          24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]};
-          24'h001000: Dout <= #1 {intPending[31:1],1'b0};
+          24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]};
-          24'h001004: Dout <= #1 {{(63-`N){1'b0}},intPending[`N:32]};
+          // verilator lint_on SELRANGE 
-          24'h002000: Dout <= #1 {intEn[0][31:1],1'b0};
+          // verilator lint_on WIDTHTRUNC 
-          24'h002004: Dout <= #1 {{(63-`N){1'b0}},intEn[0][`N:32]};
+
-          24'h002080: Dout <= #1 {intEn[0][31:1],1'b0};
+          24'h002080: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0};
-          24'h002084: Dout <= #1 {{(63-`N){1'b0}},intEn[1][`N:32]};
+          // verilator lint_off SELRANGE
-          `endif
+          // verilator lint_off WIDTHTRUNC 
+          24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]};
+          // verilator lint_on SELRANGE
+          // verilator lint_on WIDTHTRUNC 
           24'h200000: Dout <= #1 {29'b0,intThreshold[0]};
           24'h200004: begin
             Dout <= #1 {26'b0,intClaim[0]};
-            intInProgress <= #1 intInProgress | ({{`N-1{1'b0}}, 1'b1} << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
+            intInProgress <= #1 intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed
           end
           24'h201000: Dout <= #1 {29'b0,intThreshold[1]};
           24'h201004: begin
             Dout <= #1 {26'b0,intClaim[1]};
-            intInProgress <= #1 intInProgress | ({{`N-1{1'b0}}, 1'b1} << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
+            intInProgress <= #1 intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed
           end
           default: Dout <= #1 32'h0; // invalid access
         endcase
@@ -161,14 +163,14 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
 
   // connect sources to requests
   always_comb begin
-    requests = {`N{1'b0}};
+    requests = {P.PLIC_NUM_SRC{1'b0}};
     if(P.PLIC_GPIO_ID != 0) requests[P.PLIC_GPIO_ID] = GPIOIntr;
     if(P.PLIC_UART_ID != 0) requests[P.PLIC_UART_ID] = UARTIntr;
   end
 
   // pending interrupt request
   assign nextIntPending = (intPending | requests) & ~intInProgress; 
-  flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
+  flopr #(P.PLIC_NUM_SRC) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending);
 
   // context-dependent signals
   genvar ctx;
@@ -181,7 +183,7 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
     //   ("active" meaning it is enabled in context <ctx> and is pending)
     genvar src, pri;
     for (pri=1; pri<=7; pri++) begin
-      for (src=1; src<=`N; src++) begin
+      for (src=1; src<=P.PLIC_NUM_SRC; src++) begin
         assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src];
       end
     end
@@ -210,14 +212,14 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
 
     // of the sources at the highest priority level that has active requests,
     // which sources have active requests?
-    assign irqs_at_max_priority[ctx][`N:1] =
+    assign irqs_at_max_priority[ctx][P.PLIC_NUM_SRC:1] =
-      ({`N{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) |
-      ({`N{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) |
-      ({`N{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) |
-      ({`N{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) |
-      ({`N{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) |
-      ({`N{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) |
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) |
-      ({`N{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]);
+      ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]);
 
     // of the sources at the highest priority level that has active requests,
     // choose the source with the lowest source ID to be the most urgent
@@ -225,7 +227,7 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
     integer k;
     always_comb begin
       intClaim[ctx] = 6'b0;
-      for (k=`N; k>0; k--) begin
+      for (k=P.PLIC_NUM_SRC; k>0; k--) begin
         if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0];
       end
     end

src/uncore/uncore.sv

@@ -146,7 +146,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
     assign UARTSout = 0; assign UARTIntr = 0; 
   end
   if (P.SDC_SUPPORTED == 1) begin : sdc
-    SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
+    SDC #(P) SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS,
       .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC,
       // sdc interface
       .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK,

src/wally/wallypipelinedcore.sv

@@ -78,6 +78,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
   logic                          SquashSCW;
   logic                          MDUActiveE;                      // Mul/Div instruction being executed
+  logic [3:0]                    ENVCFG_CBE;                      // Cache Block operation enables
+  logic [3:0]                    CMOpM;                           // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
+  logic                          IFUPrefetchE, LSUPrefetchM;      // instruction / data prefetch hints
 
   // floating point unit signals
   logic [2:0]                    FRM_REGW;
@@ -188,10 +191,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   // integer execution unit: integer register file, datapath and controller
   ieu #(P) ieu(.clk, .reset,
      // Decode Stage interface
-     .InstrD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
+     .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
      // Execute Stage interface
      .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
-     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE,
+     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
      // Memory stage interface
      .SquashSCW,  // from LSU
      .MemRWM,     // read/write control goes to LSU
@@ -215,7 +218,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
     .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,            
     .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
-    .ReadDataW, .FlushDCacheM,
+    .ReadDataW, .FlushDCacheM, .CMOpM, .LSUPrefetchM,
     // connected to ahb (all stay the same)
     .LSUHADDR,  .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, 
     .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
@@ -291,7 +294,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
+      .FRM_REGW, .ENVCFG_CBE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
   end else begin
     assign CSRReadValW      = 0;
     assign UnalignedPCNextF = PC2NextF;

testbench/common/functionName.sv

@@ -119,8 +119,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
 //  initial begin
   always @ (negedge reset) begin
 	// clear out the old mapping between programs.
-	foreach(ProgramAddrMapMemory[i]) ProgramAddrMapMemory.delete(i);	
+    ProgramAddrMapMemory.delete();
-	foreach(ProgramLabelMapMemory[i]) ProgramLabelMapMemory.delete(i);
+    ProgramLabelMapMemory.delete();
 
     $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory);
     // we need to count the number of lines in the file so we can set FunctionRadixLineCount.
@@ -169,7 +169,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) (
   assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0;
   initial ProgramAddrIndex = '0;
 
-  assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
+  always @(*) FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex];
 
 endmodule // function_radix
 

testbench/common/instrNameDecTB.sv

@@ -30,13 +30,14 @@ module instrNameDecTB(
   logic [2:0] funct3;
   logic [6:0] funct7;
   logic [11:0] imm;
-  logic [4:0] rs2;
+  logic [4:0] rs2, rd;
 
   assign op = instr[6:0];
   assign funct3 = instr[14:12];
   assign funct7 = instr[31:25];
   assign imm = instr[31:20];
   assign rs2 = instr[24:20];
+  assign rd = instr[11:7];
 
   // it would be nice to add the operands to the name 
   // create another variable called decoded
@@ -77,7 +78,10 @@ module instrNameDecTB(
                        else if (funct7[6:1] == 6'b010010) name = "BEXTI";
                        else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
                        else                           name = "ILLEGAL"; 
-      10'b0010011_110: name = "ORI";
+      10'b0010011_110: if      (rd == 0 & rs2 == 0) name = "PREFETCH.I";
+                       else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
+                       else if (rd == 0 & rs2 == 3) name = "PREFETCH.W";
+                       else                         name = "ORI";
       10'b0010011_111: name = "ANDI";
       10'b0010111_???: name = "AUIPC";
       10'b0100011_000: name = "SB";
@@ -215,7 +219,13 @@ module instrNameDecTB(
                        else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
                        else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
                        else                              name = "ILLEGAL";
-      10'b0001111_???: name = "FENCE";
+      10'b0001111_000: name = "FENCE";
+      10'b0001111_001: name = "FENCE.I";
+      10'b0001111_010: if      (instr[31:20] == 12'd0) name = "CBO.INVAL";
+                       else if (instr[31:20] == 12'd1) name = "CBO.CLEAN";
+                       else if (instr[31:20] == 12'd2) name = "CBO.FLUSH";
+                       else if (instr[31:20] == 12'd4) name = "CBO.ZERO";    
+                       else                            name = "ILLEGAL";                   
       10'b1000011_???: name = "FMADD";
       10'b1000111_???: name = "FMSUB";
       10'b1001011_???: name = "FNMSUB";

testbench/common/loggers.sv

@@ -151,8 +151,10 @@ module loggers import cvw::*; #(parameter cvw_t P,
       $fwrite(file, "BEGIN %s\n", memfilename);
     end
     string AccessTypeString, HitMissString;
-    assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
+    always @(*) begin
+      HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
                       dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
+    end
     always @(posedge clk) begin
     if(resetEdge) $fwrite(file, "TRAIN\n");
     if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
@@ -174,14 +176,16 @@ module loggers import cvw::*; #(parameter cvw_t P,
 
     flop #(1) ResetDReg(clk, reset, resetD);
     assign resetEdge = ~reset & resetD;
-    assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
+    always @(*) begin
+      HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
                       (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
                       dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
-    assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
+      AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
                          dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" :
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
                          "NULL";
+    end
 
     assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
                      ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &

testbench/common/ramxdetector.sv

@@ -0,0 +1,45 @@
+///////////////////////////////////////////
+// ramxdetector.sv
+//
+// Written: David_Harris@hmc.edu
+// Modified: 2 July 2023
+//
+// Purpose: Detects if the processor is attempting to read unitialized RAM
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ramxdetector #(parameter XLEN, LLEN) (
+  input  logic            clk,
+  input  logic            MemReadM,
+  input  logic            LSULoadAccessFaultM,
+  input  logic [LLEN-1:0] ReadDataM,
+  input  logic [XLEN-1:0] PCM,
+  input  logic [31:0]     InstrM,
+  input  logic [XLEN-1:0] IEUAdrM,
+  input  string           InstrMName
+);
+
+  always_ff @(posedge clk)
+    if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
+      $display("WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests.");
+      $display("  PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
+      //$stop;
+    end
+  
+endmodule

testbench/common/riscvassertions.sv

@@ -56,6 +56,11 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
     assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
     assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
+    assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
+    assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
+    assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM required DCACHE_SUPPORTED");
+    assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ required DCACHE_SUPPORTED");
+    assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP required DCACHE_SUPPORTED");
   end
 
 endmodule

testbench/common/shadowmem.sv

@@ -39,10 +39,10 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
   logic         startD;
   
   if(P.DCACHE_SUPPORTED) begin
-    localparam numlines       = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+    localparam numlines       = P.DCACHE_WAYSIZEINBYTES*8/P.DCACHE_LINELENINBITS;
-    localparam numways        = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+    localparam numways        = P.DCACHE_NUMWAYS;
-    localparam linebytelen    = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+    localparam linelen        = P.DCACHE_LINELENINBITS;
-    localparam linelen        = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
+    localparam linebytelen    = linelen/8;
     localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
     localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
     localparam numwords       = sramlen/P.XLEN;

testbench/common/wallyTracer.sv

@@ -163,7 +163,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 	  CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
 	  CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
 	  CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
-	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
+	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
 	  CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW;
 	  // user CSRs
 	  CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;

testbench/testbench-xcelium.sv

@@ -0,0 +1,606 @@
+///////////////////////////////////////////
+// testbench.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: Wally Testbench and helper modules
+//          Applies test programs from the riscv-arch-test and Imperas suites
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "config.vh"
+`include "tests.vh"
+
+import cvw::*;
+
+module testbench;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
+  parameter DEBUG=0;
+  parameter TEST="none";
+  parameter PrintHPMCounters=1;
+  parameter BPRED_LOGGER=0;
+  parameter I_CACHE_ADDR_LOGGER=0;
+  parameter D_CACHE_ADDR_LOGGER=0;
+ 
+`include "parameter-defs.vh"
+
+  logic        clk;
+  logic        reset_ext, reset;
+  logic        ResetMem;
+
+  // DUT signals
+  logic [P.AHBW-1:0]    HRDATAEXT;
+  logic                 HREADYEXT, HRESPEXT;
+  logic [P.PA_BITS-1:0] HADDR;
+  logic [P.AHBW-1:0]    HWDATA;
+  logic [P.XLEN/8-1:0]  HWSTRB;
+  logic                 HWRITE;
+  logic [2:0]           HSIZE;
+  logic [2:0]           HBURST;
+  logic [3:0]           HPROT;
+  logic [1:0]           HTRANS;
+  logic                 HMASTLOCK;
+  logic                 HCLK, HRESETn;
+
+  logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
+  logic        UARTSin, UARTSout;
+
+  logic        SDCCLK;
+  logic        SDCCmdIn;
+  logic        SDCCmdOut;
+  logic        SDCCmdOE;
+  logic [3:0]  SDCDatIn;
+  tri1  [3:0]  SDCDat;
+  tri1         SDCCmd;
+
+  logic        HREADY;
+  logic        HSELEXT;
+
+  
+  string  ProgramAddrMapFile, ProgramLabelMapFile;
+  integer ProgramAddrLabelArray [string];
+
+  int test, i, errors, totalerrors;
+
+  string outputfile;
+  integer outputFilePointer;
+
+  string tests[];
+  logic DCacheFlushDone, DCacheFlushStart;
+  logic riscofTest; 
+  logic Validate;
+  logic SelectTest;
+
+  
+
+  // pick tests based on modes supported
+  initial begin
+    $display("TEST is %s", TEST);
+    //tests = '{};
+    if (P.XLEN == 64) begin // RV64
+      case (TEST)
+        "arch64i":                               tests = arch64i;
+        "arch64priv":                            tests = arch64priv;
+        "arch64c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
+                          else                   tests = {arch64c};
+        "arch64m":      if (P.M_SUPPORTED)        tests = arch64m;
+        "arch64f":      if (P.F_SUPPORTED)        tests = arch64f;
+        "arch64d":      if (P.D_SUPPORTED)        tests = arch64d;  
+        "arch64f_fma":      if (P.F_SUPPORTED)        tests = arch64f_fma;
+        "arch64d_fma":      if (P.D_SUPPORTED)        tests = arch64d_fma;  
+        "arch64zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
+        "imperas64i":                            tests = imperas64i;
+        "imperas64f":   if (P.F_SUPPORTED)        tests = imperas64f;
+        "imperas64d":   if (P.D_SUPPORTED)        tests = imperas64d;
+        "imperas64m":   if (P.M_SUPPORTED)        tests = imperas64m;
+        "wally64a":     if (P.A_SUPPORTED)        tests = wally64a;
+        "imperas64c":   if (P.C_SUPPORTED)        tests = imperas64c;
+                        else                     tests = imperas64iNOc;
+        "custom":                                tests = custom;
+        "wally64i":                              tests = wally64i; 
+        "wally64priv":                           tests = wally64priv;
+        "wally64periph":                         tests = wally64periph;
+        "coremark":                              tests = coremark;
+        "fpga":                                  tests = fpga;
+        "ahb" :                                  tests = ahb;
+        "coverage64gc" :                         tests = coverage64gc;
+        "arch64zba":     if (P.ZBA_SUPPORTED)     tests = arch64zba;
+        "arch64zbb":     if (P.ZBB_SUPPORTED)     tests = arch64zbb;
+        "arch64zbc":     if (P.ZBC_SUPPORTED)     tests = arch64zbc;
+        "arch64zbs":     if (P.ZBS_SUPPORTED)     tests = arch64zbs;
+      endcase 
+    end else begin // RV32
+      case (TEST)
+        "arch32i":                               tests = arch32i;
+        "arch32priv":                            tests = arch32priv;
+        "arch32c":      if (P.C_SUPPORTED) 
+                          if (P.ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
+                          else                   tests = {arch32c};
+        "arch32m":      if (P.M_SUPPORTED)        tests = arch32m;
+        "arch32f":      if (P.F_SUPPORTED)        tests = arch32f;
+        "arch32d":      if (P.D_SUPPORTED)        tests = arch32d;
+        "arch32f_fma":      if (P.F_SUPPORTED)        tests = arch32f_fma;
+        "arch32d_fma":      if (P.D_SUPPORTED)        tests = arch32d_fma;
+        "arch32zi":     if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
+        "imperas32i":                            tests = imperas32i;
+        "imperas32f":   if (P.F_SUPPORTED)        tests = imperas32f;
+        "imperas32m":   if (P.M_SUPPORTED)        tests = imperas32m;
+        "wally32a":     if (P.A_SUPPORTED)        tests = wally32a;
+        "imperas32c":   if (P.C_SUPPORTED)        tests = imperas32c;
+                        else                     tests = imperas32iNOc;
+        "wally32i":                              tests = wally32i; 
+        "wally32e":                              tests = wally32e; 
+        "wally32priv":                           tests = wally32priv;
+        "wally32periph":                         tests = wally32periph;
+        "embench":                               tests = embench;
+        "coremark":                              tests = coremark;
+        "arch32zba":     if (P.ZBA_SUPPORTED)     tests = arch32zba;
+        "arch32zbb":     if (P.ZBB_SUPPORTED)     tests = arch32zbb;
+        "arch32zbc":     if (P.ZBC_SUPPORTED)     tests = arch32zbc;
+        "arch32zbs":     if (P.ZBS_SUPPORTED)     tests = arch32zbs;
+      endcase
+    end
+    if (tests.size() == 0) begin
+      $display("TEST %s not supported in this configuration", TEST);
+      $stop;
+    end
+  end // initial begin
+
+  // Model the testbench as an fsm.
+  // Do this in parts so it easier to verify
+  // part 1: build a version which echos the same behavior as the below code, but does not drive anything
+  // part 2: drive some of the controls
+  // part 3: drive all logic and remove old inital and always @ negedge clk block
+
+  typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
+                           STATE_INIT_TEST,
+                           STATE_RESET_MEMORIES,
+                           STATE_RESET_MEMORIES2,
+                           STATE_LOAD_MEMORIES,
+                           STATE_RESET_TEST,
+                           STATE_RUN_TEST,
+                           STATE_CHECK_TEST,
+                           STATE_CHECK_TEST_WAIT,
+                           STATE_VALIDATE,
+                           STATE_INCR_TEST} statetype;
+  statetype CurrState, NextState;
+  logic        TestBenchReset;
+  logic [2:0]  ResetCount, ResetThreshold;
+  logic        LoadMem;
+  logic        ResetCntEn;
+  logic        ResetCntRst;
+  
+
+  string  signame, memfilename, pathname;
+  integer begin_signature_addr;
+
+  assign ResetThreshold = 3'd5;
+
+  initial begin
+    TestBenchReset = 1;
+    # 100;
+    TestBenchReset = 0;
+  end
+
+  always_ff @(posedge clk)
+    if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
+    else CurrState <= #1 NextState;  
+
+  // fsm next state logic
+  always_comb begin
+    // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
+    // and tests[0] == "2" refers to WallyRiscvArchTests 
+    riscofTest = tests[0] == "1" | tests[0] == "2"; 
+    pathname = tvpaths[tests[0].atoi()];
+
+    case(CurrState)
+      STATE_TESTBENCH_RESET:                      NextState = STATE_INIT_TEST;
+      STATE_INIT_TEST:                            NextState = STATE_RESET_MEMORIES;
+      STATE_RESET_MEMORIES:                       NextState = STATE_RESET_MEMORIES2;
+      STATE_RESET_MEMORIES2:                      NextState = STATE_LOAD_MEMORIES;  // Give the reset enough time to ensure the bus is reset before loading the memories.
+      STATE_LOAD_MEMORIES:                        NextState = STATE_RESET_TEST;
+      STATE_RESET_TEST:      if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_RUN_TEST:        if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
+                             else                 NextState = STATE_RUN_TEST;
+      STATE_CHECK_TEST:      if (DCacheFlushDone) NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_CHECK_TEST_WAIT: if(DCacheFlushDone)  NextState = STATE_VALIDATE;
+                             else                 NextState = STATE_CHECK_TEST_WAIT;
+      STATE_VALIDATE:                             NextState = STATE_INIT_TEST;
+      STATE_INCR_TEST:                            NextState = STATE_INIT_TEST;
+      default:                                    NextState = STATE_TESTBENCH_RESET;
+    endcase
+  end // always_comb
+  // fsm output control logic 
+  assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | 
+                     CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | 
+                     CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
+  // this initialization is very expensive, only do it for coremark.  
+  assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
+  assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
+  assign ResetCntRst = CurrState == STATE_INIT_TEST;
+  assign ResetCntEn = CurrState == STATE_RESET_TEST;
+  assign Validate = CurrState == STATE_VALIDATE;
+  assign SelectTest = CurrState == STATE_INIT_TEST;
+
+  // fsm reset counter
+  counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Find the test vector files and populate the PC to function label converter
+  ////////////////////////////////////////////////////////////////////////////////
+  logic [P.XLEN-1:0] testadr;
+  assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
+  always @(posedge clk) begin
+    if(SelectTest) begin
+      if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+      else            memfilename = {pathname, tests[test], ".elf.memfile"};
+      if (riscofTest) begin
+        ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
+      end else begin
+        ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+        ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
+      end
+      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
+      // the addr of each label and fill the array. To expand, add more elements to this array 
+      // and initialize them to zero (also initilaize them to zero at the start of the next test)
+      if(!P.FPGA) begin
+        updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
+      end
+    end
+    
+  ////////////////////////////////////////////////////////////////////////////////
+  // Verify the test ran correctly by checking the memory against a known signature.
+  ////////////////////////////////////////////////////////////////////////////////
+    if(TestBenchReset) test = 1;
+    if (TEST == "coremark")
+      if (dut.core.EcallFaultM) begin
+        $display("Benchmark: coremark is done.");
+        $stop;
+      end
+    if(Validate) begin
+      if (TEST == "embench") begin
+        // Writes contents of begin_signature to .sim.output file
+        // this contains instret and cycles for start and end of test run, used by embench 
+        // python speed script to calculate embench speed score. 
+        // also, begin_signature contains the results of the self checking mechanism, 
+        // which will be read by the python script for error checking
+        $display("Embench Benchmark: %s is done.", tests[test]);
+        if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
+        else outputfile = {pathname, tests[test], ".sim.output"};
+        outputFilePointer = $fopen(outputfile, "w");
+        i = 0;
+        testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
+        while ($unsigned(i) < $unsigned(5'd5)) begin
+          $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
+          i = i + 1;
+        end
+        $fclose(outputFilePointer);
+        $display("Embench Benchmark: created output file: %s", outputfile);
+      end else if (TEST == "coverage64gc") begin
+        $display("Coverage tests don't get checked");
+      end else begin 
+        // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+        // clear signature to prevent contamination from previous tests
+      end
+
+      if (!begin_signature_addr)
+        $display("begin_signature addr not found in %s", ProgramLabelMapFile);
+      else if (TEST != "embench") begin   // *** quick hack for embench.  need a better long term solution
+        CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
+      end
+      if(errors > 0) totalerrors = totalerrors + 1;
+      test = test + 1; // *** this probably needs to be moved.
+      if (test == tests.size()) begin
+        if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
+        else $display("FAIL: %d test programs had errors", totalerrors);
+        $stop;
+      end
+    end
+  end
+
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Some memories are not reset, but should be zeros or set to some initial value for simulation
+  ////////////////////////////////////////////////////////////////////////////////
+  integer adrindex;
+
+  if (P.UNCORE_RAM_SUPPORTED) `define TB_UNCORE_RAM_SUPPORTED;
+  if (P.BPRED_SUPPORTED) `define TB_BPRED_SUPPORTED;
+  if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) `define TB_BHT;
+
+  always @(posedge clk) begin
+    if (ResetMem)  // program memory is sometimes reset
+      if (P.UNCORE_RAM_SUPPORTED) begin
+      `ifdef TB_UNCORE_RAM_SUPPORTED
+        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
+      `endif
+      end
+    if(reset) begin  // branch predictor must always be reset
+      if (P.BPRED_SUPPORTED) begin
+      `ifdef TB_BPRED_SUPPORTED
+        // local history only
+        if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin
+        `ifdef TB_BHT
+          for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
+            dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
+        `endif
+        end
+        // these are both always included if there is a bpred
+        for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+        for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
+          dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+      `endif
+      end
+    end
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // load memories with program image
+  ////////////////////////////////////////////////////////////////////////////////
+  if (P.FPGA) `define TB_FPGA  // this is a gross hack for xcelium and verilator
+  if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
+  if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
+  if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
+  always @(posedge clk) begin
+    if (LoadMem) begin
+      if (P.FPGA) begin
+      `ifdef TB_FPGA
+        string romfilename, sdcfilename;
+        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
+        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
+        $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
+        // shorten sdc timers for simulation
+        dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
+      `endif
+      end
+      else if (P.IROM_SUPPORTED) begin
+      `ifdef TB_IROM_SUPPORTED
+        $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+      `endif
+      end
+      else if (P.BUS_SUPPORTED) begin
+      `ifdef TB_BUS_SUPPORTED
+        $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      `endif
+      end
+      if (P.DTIM_SUPPORTED) begin
+      `ifdef TB_DTIM_SUPPORTED
+        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+      `endif
+      end
+      $display("Read memfile %s", memfilename);
+    end
+  end  
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Actual hardware
+  ////////////////////////////////////////////////////////////////////////////////
+
+  // instantiate device to be tested
+  assign GPIOIN = 0;
+  assign UARTSin = 1;
+
+  if(P.EXT_MEM_SUPPORTED) begin
+    ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) 
+    ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
+      .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
+  end else begin 
+    assign HREADYEXT = 1;
+    assign {HRESPEXT, HRDATAEXT} = '0;
+  end
+
+  if(P.FPGA) begin : sdcard
+    sdModel sdcard
+      (.sdClk(SDCCLK),
+       .cmd(SDCCmd), 
+       .dat(SDCDat));
+
+    assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
+    assign SDCCmdIn = SDCCmd;
+    assign SDCDatIn = SDCDat;
+  end else begin
+    assign SDCCmd = '0;
+    assign SDCDat = '0;
+  end
+
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+  // generate clock to sequence tests
+  always begin
+    clk = 1; # 5; clk = 0; # 5;
+  end
+
+  ////////////////////////////////////////////////////////////////////////////////
+  // Support logic
+  ////////////////////////////////////////////////////////////////////////////////
+
+  // Track names of instructions
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.InstrRawF[31:0],
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+  // watch for problems such as lockup, reading unitialized memory, bad configs
+  watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);  // check if PCW is stuck
+  ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, 
+                                      dut.core.ifu.PCM, dut.core.ifu.InstrM, dut.core.lsu.IEUAdrM, InstrMName);
+  riscvassertions #(P) riscvassertions();  // check assertions for a legal configuration
+  loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
+  loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
+
+  // track the current function or global label
+  if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName
+    FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
+			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
+  end
+
+
+  // Termination condition
+  // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
+  // or sw	gp,-56(t0) for new Imperas tests
+  // or sd gp, -56(t0) 
+  // or on a jump to self infinite loop (6f) for RISC-V Arch tests
+  logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
+  if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  else                  assign ecf = 0;
+  assign DCacheFlushStart = ecf & 
+			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.core.ieu.dp.regf.we3 & 
+			      dut.core.ieu.dp.regf.a3 == 3 & 
+			      dut.core.ieu.dp.regf.wd3 == 1)) |
+           ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
+           ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
+
+  DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
+
+  task automatic CheckSignature;
+    // This task must be declared inside this module as it needs access to parameter P.  There is
+    // no way to pass P to the task unless we convert it to a module.
+    
+    input string  pathname;
+    input string  TestName;
+    input logic   riscofTest;
+    input integer begin_signature_addr;
+    output integer errors;
+
+    localparam SIGNATURESIZE = 5000000;
+    integer        i;
+    logic [31:0]   sig32[0:SIGNATURESIZE];
+    logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
+    string            signame;
+    logic [P.XLEN-1:0] testadr, testadrNoBase;
+
+    if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED2
+    
+    // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+    // clear signature to prevent contamination from previous tests
+    for(i=0; i<SIGNATURESIZE; i=i+1) begin
+      sig32[i] = 'bx;
+    end
+    if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
+    else signame = {pathname, TestName, ".signature.output"};
+    // read signature, reformat in 64 bits if necessary
+    $readmemh(signame, sig32);
+    i = 0;
+    while (i < SIGNATURESIZE) begin
+      if (P.XLEN == 32) begin
+        signature[i] = sig32[i];
+        i = i+1;
+      end else begin
+        signature[i/2] = {sig32[i+1], sig32[i]};
+        i = i + 2;
+      end
+      if (i >= 4 & sig32[i-4] === 'bx) begin
+        if (i == 4) begin
+          i = SIGNATURESIZE+1; // flag empty file
+          $display("  Error: empty test file");
+        end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
+      end
+    end
+
+    // Check errors
+    errors = (i == SIGNATURESIZE+1); // error if file is empty
+    i = 0;
+    testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
+    testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
+    /* verilator lint_off INFINITELOOP */
+    while (signature[i] !== 'bx) begin
+      logic [P.XLEN-1:0] sig;
+      if (P.DTIM_SUPPORTED) begin
+      `ifdef TB_DTIM_SUPPORTED2
+        //sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
+      `endif
+      end
+      else if (P.UNCORE_RAM_SUPPORTED) begin
+      `ifdef TB_UNCORE_RAM_SUPPORTED
+        sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+      //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
+      `endif
+      end
+      if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
+        errors = errors+1;
+        $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
+			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+        $stop; //***debug
+      end
+      i = i + 1;
+    end
+    /* verilator lint_on INFINITELOOP */
+    if (errors == 0) begin
+      $display("%s succeeded.  Brilliant!!!", TestName);
+    end else begin
+      $display("%s failed with %d errors. :(", TestName, errors);
+      //totalerrors = totalerrors+1;
+    end
+
+  endtask //
+  
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
+
+endmodule
+
+/* verilator lint_on STMTDLY */
+/* verilator lint_on WIDTH */
+
+task automatic updateProgramAddrLabelArray;
+  /* verilator lint_off WIDTHTRUNC */
+  /* verilator lint_off WIDTHEXPAND */
+  input string ProgramAddrMapFile, ProgramLabelMapFile;
+  inout  integer ProgramAddrLabelArray [string];
+  // Gets the memory location of begin_signature
+  integer ProgramLabelMapFP, ProgramAddrMapFP;
+  ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
+  ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
+
+
+  if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
+    // *** RT: I'm a bit confused by the required initialization here.
+    ProgramAddrLabelArray["begin_signature"] = 0;
+    ProgramAddrLabelArray["tohost"] = 0;
+    while (!$feof(ProgramLabelMapFP)) begin
+      string label, adrstr;
+      integer returncode;
+      returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
+      returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
+      if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
+    end
+  end
+  $fclose(ProgramLabelMapFP);
+  $fclose(ProgramAddrMapFP);
+  /* verilator lint_on WIDTHTRUNC */
+  /* verilator lint_on WIDTHEXPAND */
+endtask
+

testbench/testbench.sv

@@ -35,7 +35,7 @@ module testbench;
   /* verilator lint_off WIDTHEXPAND */
   parameter DEBUG=0;
   parameter TEST="none";
-  parameter PrintHPMCounters=0;
+  parameter PrintHPMCounters=1;
   parameter BPRED_LOGGER=0;
   parameter I_CACHE_ADDR_LOGGER=0;
   parameter D_CACHE_ADDR_LOGGER=0;
@@ -409,7 +409,20 @@ module testbench;
   // Support logic
   ////////////////////////////////////////////////////////////////////////////////
 
+  // Track names of instructions
+  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
+  logic [31:0] InstrW;
+  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.InstrRawF[31:0],
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
+                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+  // watch for problems such as lockup, reading unitialized memory, bad configs
   watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset);  // check if PCW is stuck
+  ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, 
+                                      dut.core.ifu.PCM, dut.core.ifu.InstrM, dut.core.lsu.IEUAdrM, InstrMName);
   riscvassertions #(P) riscvassertions();  // check assertions for a legal configuration
   loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
   loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
@@ -420,15 +433,6 @@ module testbench;
 			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
   end
 
-  // Track names of instructions
-  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  logic [31:0] InstrW;
-  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
-  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
-                dut.core.ifu.InstrRawF[31:0],
-                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
-                dut.core.ifu.InstrM,  InstrW,
-                InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // Termination condition
   // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
@@ -462,7 +466,7 @@ module testbench;
     integer        i;
     logic [31:0]   sig32[0:SIGNATURESIZE];
     logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
-    string            signame, pathname;
+    string            signame;
     logic [P.XLEN-1:0] testadr, testadrNoBase;
     
     // for tests with no self checking mechanism, read .signature.output file and compare to check for errors

testbench/tests.vh

@@ -75,26 +75,26 @@ string tvpaths[] = '{
 
   string embench[] = '{
     `EMBENCH,
-    "bd_speedopt_speed/src/nsichneu/nsichneu",
-    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/aha-mont64/aha-mont64",
     "bd_speedopt_speed/src/crc32/crc32",
+    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/edn/edn",
     "bd_speedopt_speed/src/huffbench/huffbench",
     "bd_speedopt_speed/src/matmult-int/matmult-int",
-    // "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
+     "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
     "bd_speedopt_speed/src/minver/minver",
     "bd_speedopt_speed/src/nettle-aes/nettle-aes",
     "bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
+    "bd_speedopt_speed/src/nsichneu/nsichneu",
     "bd_speedopt_speed/src/nbody/nbody",
     "bd_speedopt_speed/src/picojpeg/picojpeg",
-    // "bd_speedopt_speed/src/primecount/primecount",
+     "bd_speedopt_speed/src/primecount/primecount",
     "bd_speedopt_speed/src/qrduino/qrduino",
     "bd_speedopt_speed/src/sglib-combined/sglib-combined",
     "bd_speedopt_speed/src/slre/slre",
     "bd_speedopt_speed/src/st/st",
     "bd_speedopt_speed/src/statemate/statemate",
-    // "bd_speedopt_speed/src/tarfind/tarfind",
+     "bd_speedopt_speed/src/tarfind/tarfind",
     "bd_speedopt_speed/src/ud/ud",
     "bd_speedopt_speed/src/wikisort/wikisort",
     "bd_sizeopt_speed/src/aha-mont64/aha-mont64",
@@ -103,20 +103,20 @@ string tvpaths[] = '{
     "bd_sizeopt_speed/src/edn/edn",
     "bd_sizeopt_speed/src/huffbench/huffbench",
     "bd_sizeopt_speed/src/matmult-int/matmult-int",
-    // "bd_sizeopt_speed/src/md5sum/md5sum",
+     "bd_sizeopt_speed/src/md5sum/md5sum",
     "bd_sizeopt_speed/src/minver/minver",
     "bd_sizeopt_speed/src/nbody/nbody",
     "bd_sizeopt_speed/src/nettle-aes/nettle-aes",
     "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256",
     "bd_sizeopt_speed/src/nsichneu/nsichneu",
     "bd_sizeopt_speed/src/picojpeg/picojpeg",
-    // "bd_sizeopt_speed/src/primecount/primecount",
+     "bd_sizeopt_speed/src/primecount/primecount",
     "bd_sizeopt_speed/src/qrduino/qrduino",
     "bd_sizeopt_speed/src/sglib-combined/sglib-combined",
     "bd_sizeopt_speed/src/slre/slre",
     "bd_sizeopt_speed/src/st/st",
     "bd_sizeopt_speed/src/statemate/statemate",
-    // "bd_sizeopt_speed/src/tarfind/tarfind",
+     "bd_sizeopt_speed/src/tarfind/tarfind",
     "bd_sizeopt_speed/src/ud/ud",
     "bd_sizeopt_speed/src/wikisort/wikisort"
   };
@@ -1466,7 +1466,7 @@ string arch64zbb[] = '{
     "rv64i_m/B/src/andn-01.S",
     "rv64i_m/B/src/orn-01.S",
     "rv64i_m/B/src/xnor-01.S",
-    "rv64i_m/B/src/zext.h-01.S",
+    "rv64i_m/B/src/zext.h_64-01.S",
     "rv64i_m/B/src/sext.b-01.S",
     "rv64i_m/B/src/sext.h-01.S",
     "rv64i_m/B/src/clz-01.S",
@@ -2031,8 +2031,8 @@ string arch64zbs[] = '{
     "rv32i_m/privilege/src/WALLY-mie-01.S",
     "rv32i_m/privilege/src/WALLY-minfo-01.S",
     "rv32i_m/privilege/src/WALLY-misa-01.S",
-//    "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",
+    // "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",    // run this if SVADU_SUPPORTED = 0
-    "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S",
+    "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S", // run this if SVADU_SUPPORTED = 1
     "rv32i_m/privilege/src/WALLY-mtvec-01.S",
     "rv32i_m/privilege/src/WALLY-pma-01.S",
     "rv32i_m/privilege/src/WALLY-pmp-01.S",

testbench/wallywrapper.sv

@@ -26,36 +26,16 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "config.vh"
-`include "tests.vh"
-
-`define PrintHPMCounters 0
-`define BPRED_LOGGER 0
-`define I_CACHE_ADDR_LOGGER 0
-`define D_CACHE_ADDR_LOGGER 0
 
 import cvw::*;
 
 module wallywrapper;
-  parameter DEBUG=0;
-  parameter TEST="none";
  
 `include "parameter-defs.vh"
 
   logic        clk;
   logic        reset_ext, reset;
 
-  parameter SIGNATURESIZE = 5000000;
-
-  int test, i, errors, totalerrors;
-  logic [31:0] sig32[0:SIGNATURESIZE];
-  logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
-  logic [P.XLEN-1:0] testadr, testadrNoBase;
-  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  logic [31:0] InstrW;
-
-  string tests[];
-  logic [3:0] dummy;
-
   logic [P.AHBW-1:0]    HRDATAEXT;
   logic                HREADYEXT, HRESPEXT;
   logic [P.PA_BITS-1:0] HADDR;

tests/fp/combined_IF_vectors/extract_arch_vectors.py

@@ -1,7 +1,7 @@
 #! /usr/bin/python3
 
-# author: Alessandro Maiuolo
+# author: Alessandro Maiuolo, Kevin Kim
-# contact: amaiuolo@g.hmc.edu
+# contact: amaiuolo@g.hmc.edu, kekim@hmc.edu
 # date created: 3-29-2023
 
 # extract all arch test vectors
@@ -77,7 +77,7 @@ def create_vectors(my_config):
         rounding_mode = "X"
         flags = "XX"
         # use name to create our new tv
-        dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a')
+        dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'w')
         # open vectors
         src_file1 = open(source_dir1 + vector1,'r')
         src_file2 = open(source_dir2 + vector2,'r')
@@ -144,7 +144,7 @@ def create_vectors(my_config):
                 answer2 = src_file2.readline().strip()
                 answer1 = src_file2.readline().strip()
                 answer = answer1 + answer2
-                # print(answer1,answer2)
+                #print(answer1,answer2)
                 if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
                     # parse through .S file
                     detected = False
@@ -179,13 +179,56 @@ def create_vectors(my_config):
                 else:
                     # print("read false")
                     reading = False
+        elif my_config.letter == "M" and my_config.bits == 32:
+            reading = True
+            while reading:
+                # print("trigger 64M")
+                # get answer from Ref...signature
+                # answers span two lines and are reversed
+                answer = src_file2.readline().strip()
+                print(f"Answer: {answer}")
+                #print(answer1,answer2)
+                if not (answer == "6f5ca309"): # if there is still stuff to read
+                    # parse through .S file
+                    detected = False
+                    done = False
+                    op1val = "0"
+                    op2val = "0"
+                    while not (detected or done):
+                        # print("det1")
+                        line = src_file1.readline()
+                        # print(line)
+                        if "op1val" in line:
+                            # print("det2")
+                            # parse line
+                            op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
+                            if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
+                                op1val = twos_comp(my_config.bits, op1val)
+                            if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
+                                op2val = line.split("op2val")[1].split("x")[1].strip()
+                                if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
+                                if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
+                                    op2val = twos_comp(my_config.bits, op2val)
+                            # go to next test in vector
+                            detected = True
+                        elif "RVTEST_CODE_END" in line:
+                            done = True
+                    # ints don't have flags
+                    flags = "XX"
+                    # put it all together
+                    if not done:
+                        translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode)
+                        dest_file.write(translation + "\n")
+                else:
+                    # print("read false")
+                    reading = False 
         else:
             while reading:
                 # get answer and flags from Ref...signature
                 answer = src_file2.readline()
-                # print(answer)
+                print(answer)
                 packed = src_file2.readline()[6:]
-                # print(packed)
+                print("Packed: ", packed)
                 if len(packed.strip())>0: # if there is still stuff to read
                     # print("packed")
                     # parse through .S file
@@ -229,7 +272,7 @@ def create_vectors(my_config):
         src_file2.close()
 
 config_list = [
-Config(32, "M", "div", "div_", 0),
+Config(32, "M", "div", "div-", 0),
 Config(32, "F", "fdiv", "fdiv", 1),
 Config(32, "F", "fsqrt", "fsqrt", 2),
 Config(32, "M", "rem", "rem-", 3),