From e3856708d08a146adfdfd638720114bcbd6a916b Mon Sep 17 00:00:00 2001 From: Victor Clements Date: Tue, 13 Jun 2023 10:41:18 -0700 Subject: [PATCH 01/54] pulling in FreeRTOS/kernel Submodule --- .gitmodules | 3 +++ addins/FreeRTOS-Kernel | 1 + 2 files changed, 4 insertions(+) create mode 160000 addins/FreeRTOS-Kernel diff --git a/.gitmodules b/.gitmodules index 78243a1de..6c46deabf 100644 --- a/.gitmodules +++ b/.gitmodules @@ -24,3 +24,6 @@ [submodule "addins/branch-predictor-simulator"] path = addins/branch-predictor-simulator url = https://github.com/synxlin/branch-predictor-simulator.git +[submodule "addins/FreeRTOS-Kernel"] + path = addins/FreeRTOS-Kernel + url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git diff --git a/addins/FreeRTOS-Kernel b/addins/FreeRTOS-Kernel new file mode 160000 index 000000000..17a46c252 --- /dev/null +++ b/addins/FreeRTOS-Kernel @@ -0,0 +1 @@ +Subproject commit 17a46c252f2f237e03a6768c5d15731215322f31 From 3c98ed9e292f74c57366b0975f84c201f0023181 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jun 2023 09:26:02 -0700 Subject: [PATCH 02/54] Added assertions for ZICNTR and ZIHPM --- testbench/common/riscvassertions.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 24a7e223c..50577c37d 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -56,6 +56,8 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED"); assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); + assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); + assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); end endmodule From 2f35bec970a1e824a04711a93734fdd4f944fee5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jun 2023 15:40:13 -0500 Subject: [PATCH 03/54] FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization. --- fpga/generator/wally.tcl | 2 +- fpga/src/fpgaTop.v | 11 +++++++---- src/uncore/uncore.sv | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index d5a2fca43..c7ae69d48 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -23,7 +23,7 @@ if {$board=="ArtyA7"} { read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci } -read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] +read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] if {$board=="ArtyA7"} { read_verilog {../src/fpgaTopArtyA7.v} } else { diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 990495f44..0076e0279 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -24,7 +24,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" +`include "config.vh" module fpgaTop (input default_250mhz_clk1_0_n, @@ -62,6 +62,9 @@ module fpgaTop output [0 : 0] c0_ddr4_ck_t ); +`include "parameter-defs.vh" + + wire CPUCLK; wire c0_ddr4_ui_clk_sync_rst; wire bus_struct_reset; @@ -72,12 +75,12 @@ module fpgaTop wire HCLKOpen; wire HRESETnOpen; - wire [`AHBW-1:0] HRDATAEXT; + wire [P.AHBW-1:0] HRDATAEXT; wire HREADYEXT; wire HRESPEXT; wire HSELEXT; wire [31:0] HADDR; - wire [`AHBW-1:0] HWDATA; + wire [P.AHBW-1:0] HWDATA; wire HWRITE; wire [2:0] HSIZE; wire [2:0] HBURST; @@ -211,7 +214,7 @@ module fpgaTop // wally - wallypipelinedsoc wallypipelinedsoc + wallypipelinedsoc #(P) wallypipelinedsoc (.clk(CPUCLK), .reset_ext(bus_struct_reset), // bus interface diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index d1cd99002..b703d72fe 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -146,7 +146,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( assign UARTSout = 0; assign UARTIntr = 0; end if (P.SDC_SUPPORTED == 1) begin : sdc - SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, + SDC #(P) SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, // sdc interface .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK, From 4bee446cad28072af535d166bb74b3c4604f53a1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jun 2023 16:30:14 -0500 Subject: [PATCH 04/54] Vivado requires an intermediate wrapper file for parameterization. --- fpga/generator/wally.tcl | 22 +++++---- fpga/src/fpgaTop.v | 11 ++--- fpga/src/wallypipelinedsocwrapper.sv | 72 ++++++++++++++++++++++++++++ testbench/wallywrapper.sv | 20 -------- 4 files changed, 89 insertions(+), 36 deletions(-) create mode 100644 fpga/src/wallypipelinedsocwrapper.sv diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index c7ae69d48..6a774fddc 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -12,6 +12,17 @@ if {$boardName!="ArtyA7"} { set_property board_part $boardName [current_project] } +# read package first +read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv +read_verilog -sv ../src/wallypipelinedsocwrapper.sv +# then read top level +if {$board=="ArtyA7"} { + read_verilog {../src/fpgaTopArtyA7.v} +} else { + read_verilog {../src/fpgaTop.v} +} + +# read in ip read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci @@ -23,17 +34,13 @@ if {$board=="ArtyA7"} { read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci } -read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] -if {$board=="ArtyA7"} { - read_verilog {../src/fpgaTopArtyA7.v} -} else { - read_verilog {../src/fpgaTop.v} -} +# read in all other rtl +read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] + read_verilog -sv [glob -type f ../src/sdc/*.sv] set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset] - if {$board=="ArtyA7"} { add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc] @@ -45,7 +52,6 @@ if {$board=="ArtyA7"} { # define top level set_property top fpgaTop [current_fileset] - update_compile_order -fileset sources_1 # This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on. exec mkdir -p reports/ diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 0076e0279..b6d2a4d9e 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -24,8 +24,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "config.vh" - module fpgaTop (input default_250mhz_clk1_0_n, input default_250mhz_clk1_0_p, @@ -62,9 +60,6 @@ module fpgaTop output [0 : 0] c0_ddr4_ck_t ); -`include "parameter-defs.vh" - - wire CPUCLK; wire c0_ddr4_ui_clk_sync_rst; wire bus_struct_reset; @@ -75,12 +70,12 @@ module fpgaTop wire HCLKOpen; wire HRESETnOpen; - wire [P.AHBW-1:0] HRDATAEXT; + wire [64-1:0] HRDATAEXT; wire HREADYEXT; wire HRESPEXT; wire HSELEXT; wire [31:0] HADDR; - wire [P.AHBW-1:0] HWDATA; + wire [64-1:0] HWDATA; wire HWRITE; wire [2:0] HSIZE; wire [2:0] HBURST; @@ -214,7 +209,7 @@ module fpgaTop // wally - wallypipelinedsoc #(P) wallypipelinedsoc + wallypipelinedsocwrapper wallypipelinedsocwrapper (.clk(CPUCLK), .reset_ext(bus_struct_reset), // bus interface diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv new file mode 100644 index 000000000..80adff7cf --- /dev/null +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -0,0 +1,72 @@ +/////////////////////////////////////////// +// wallypipelinedsocwrapper.sv +// +// Written: Ross Thompson ross1728@gmail.com 16 June 2023 +// Modified: +// +// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, +// not system verilog. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "config.vh" + +import cvw::*; + +module wallypipelinedsocwrapper ( + input logic clk, + input logic reset_ext, // external asynchronous reset pin + output logic reset, // reset synchronized to clk to prevent races on release + // AHB Interface + input logic [P.AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + output logic HSELEXT, + // outputs to external memory, shared with uncore memory + output logic HCLK, HRESETn, + output logic [64-1:0] HADDR, + output logic [64-1:0] HWDATA, + output logic [64/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, + output logic HREADY, + // I/O Interface + input logic TIMECLK, // optional for CLINT MTIME counter + input logic [31:0] GPIOIN, // inputs from GPIO + output logic [31:0] GPIOOUT, // output values for GPIO + output logic [31:0] GPIOEN, // output enables for GPIO + input logic UARTSin, // UART serial data input + output logic UARTSout, // UART serial data output + input logic SDCCmdIn, // SDC Command input + output logic SDCCmdOut, // SDC Command output + output logic SDCCmdOE, // SDC Command output enable + input logic [3:0] SDCDatIn, // SDC data input + output logic SDCCLK // SDC clock +); + `include "parameter-defs.vh" + + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, + .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); + +endmodule diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv index 747b31806..1a13392d1 100644 --- a/testbench/wallywrapper.sv +++ b/testbench/wallywrapper.sv @@ -26,36 +26,16 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "config.vh" -`include "tests.vh" - -`define PrintHPMCounters 0 -`define BPRED_LOGGER 0 -`define I_CACHE_ADDR_LOGGER 0 -`define D_CACHE_ADDR_LOGGER 0 import cvw::*; module wallywrapper; - parameter DEBUG=0; - parameter TEST="none"; `include "parameter-defs.vh" logic clk; logic reset_ext, reset; - parameter SIGNATURESIZE = 5000000; - - int test, i, errors, totalerrors; - logic [31:0] sig32[0:SIGNATURESIZE]; - logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; - logic [P.XLEN-1:0] testadr, testadrNoBase; - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - logic [31:0] InstrW; - - string tests[]; - logic [3:0] dummy; - logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [P.PA_BITS-1:0] HADDR; From 24b8c6c391789f706bba884b2aeb7bea2af23f33 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 16 Jun 2023 17:00:27 -0500 Subject: [PATCH 05/54] I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. --- fpga/constraints/debug2.xdc | 448 ++++++++++++++++++------------------ fpga/constraints/debug4.xdc | 278 +++++++++++----------- fpga/generator/wally.tcl | 5 +- 3 files changed, 366 insertions(+), 365 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 4b760eb65..58e2fa643 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -17,1130 +17,1130 @@ endgroup connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]] set_property port_width 64 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe1] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]] +connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe2] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] +connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe3] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe4] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe5] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe7] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe8] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe9] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe10] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe11] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe12] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe13] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe14] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe15] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 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{wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} 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{wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 5 [get_debug_ports u_ila_0/probe17] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe18] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe19] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] create_debug_port u_ila_0 probe set_property port_width 63 [get_debug_ports u_ila_0/probe20] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe21] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe22] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe23] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe24] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]] +connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe25] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]] +connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe26] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2] ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe27] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]] +connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe28] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]] +connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe29] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]] +connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe30] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]] +connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe31] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]] +connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe32] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]] +connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe33] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] +connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe34] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]] +connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe35] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]] +connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe36] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]] +connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe37] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]] +connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe38] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]] +connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/mretM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe39] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]] +connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe40] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]] +connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe41] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]] +connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe42] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]] +connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe43] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]] +connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe44] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]] +connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe45] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] -connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/sretM ]] +connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/sretM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe46] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] -connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]] +connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe47] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] -connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]] +connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe48] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48] -connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]] +connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe49] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49] -connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/TrapM ]] +connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe50] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] -connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]] +connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe51] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] -connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]] +connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPWrongE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe52] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] -connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]] +connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFenceM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe53] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] -connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]] +connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/RetM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] -connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/core/hzu/LoadStallD ]] +connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe56] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] -connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/core/hzu/StoreStallD ]] +connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe57] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] -connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/hzu/MDUStallD ]] +connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe58] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] -connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CSRRdStallD ]] +connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe59] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] -connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]] +connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe60] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] -connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]] +connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe61] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FPUStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe62] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] -connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]] +connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FCvtIntStallD ]] create_debug_port u_ila_0 probe set_property port_width 7 [get_debug_ports u_ila_0/probe63] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63] -connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]] +connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe64] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64] -connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]] +connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe65] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65] -connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/hzu/EcallFaultM ]] +connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe66] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] -connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/hzu/BreakpointFaultM ]] +connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe67] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] -connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] +connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe68] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] -connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]] +connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe69] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallDCause]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe70] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] -connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe71] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] -connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]] +connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]] # StallW is StallM. trying to connect to StallW causes issues. create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe72] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72] -connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]] +connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe73] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73] -connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] +connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe74] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74] -connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]] +connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe75] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75] -connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]] +connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe76] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76] -connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]] +connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe77] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77] -connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]] +connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe78] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78] -connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]] +connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe79] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79] -connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] +connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe80] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80] -connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]] +connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHREADY ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe81] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81] -connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]] +connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[31]}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe82] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82] -connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]] +connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe83] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83] -connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] +connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] create_debug_port u_ila_0 probe set_property port_width 53 [get_debug_ports u_ila_0/probe84] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84] -connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]] +connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe85] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85] -connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]] +connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe86] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86] -connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]] +connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe87] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87] -connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]] +connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe88] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] -connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]] +connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe89] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89] -connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]] +connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe90] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90] -connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]] +connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe91] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91] -connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]] +connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe92] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92] -connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]] +connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe93] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93] -connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]] +connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe94] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94] -connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]] +connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe95] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95] -connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]] +connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe96] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96] -connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]] +connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe97] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97] -connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]] +connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe98] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98] -connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]] +connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe99] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] -connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]] +connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[63]}]] create_debug_port u_ila_0 probe set_property port_width 56 [get_debug_ports u_ila_0/probe100] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100] -connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]] +connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe101] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101] -connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] +connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe102] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102] -connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]] +connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe103] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103] -connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] +connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 7 [get_debug_ports u_ila_0/probe104] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104] -connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]] +connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe105] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105] -connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]] +connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe106] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106] -connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]] +connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe107] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107] -connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]] +connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe108] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108] -connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]] +connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/RegWriteW]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe109] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109] -connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]] +connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/CSRWriteM} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe110] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110] -connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]] +connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe111] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111] -connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]] +connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe112] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112] -connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]] +connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe113] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113] -connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]] +connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe114] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114] -connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]] +connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe115] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115] -connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]] +connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe116] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116] -connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]] +connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe117] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117] -connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] +connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe118] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118] -connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] +connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe119] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119] -connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]] +connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe120] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120] -connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]] +connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe121] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121] -connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]] +connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe122] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122] -connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]] +connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe123] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123] -connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]] +connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe124] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124] -connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]] +connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe125] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125] -connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]] +connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe126] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] -connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]] +connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe127] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127] -connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]] +connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe128] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128] -connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} 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{wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]] +connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} 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{wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe129] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129] -connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]] +connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe130] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130] -connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]] +connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe131] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131] -connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]] +connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe132] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132] -connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]] +connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe133] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133] -connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]] +connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe134] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134] -connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]] +connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe135] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135] -connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]] +connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe136] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136] -connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]] +connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe137] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137] -connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]] +connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] -connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] +connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] # UART Signals ------------------------------------------------------- create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe139] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] -connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]] +connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Din[7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe140] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] -connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]] +connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/Dout[7]}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe141] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] -connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]] +connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/A[2]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe142] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] -connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]] +connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMWb}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe143] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] -connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]] +connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SIN}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]] +connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SOUT}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe145] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] -connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]] +connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe146] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] -connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]] +connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe147] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] -connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]] +connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe148] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] -connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]] +connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe149] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149] -connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]] +connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe150] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe150] -connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]] +connect_debug_port u_ila_0/probe150 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe151] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe151] -connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]] +connect_debug_port u_ila_0/probe151 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe152] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe152] -connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]] +connect_debug_port u_ila_0/probe152 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe153] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe153] -connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]] +connect_debug_port u_ila_0/probe153 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe154] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] -connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]] +connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] -connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]] +connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]}]] create_debug_port u_ila_0 probe set_property port_width 5 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]] +connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]] +connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[0][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]] +connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[1][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]] +connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[2][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]] +connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[3][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]] +connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[4][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe162] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] -connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]] +connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[5][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe163] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] -connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]] +connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[6][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe164] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] -connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]] +connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[7][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe165] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] -connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]] +connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[8][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe166] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] -connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]] +connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[9][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe167] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] -connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]] +connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[10][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe168] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] -connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]] +connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[11][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe169] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] -connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]] +connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[12][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe170] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] -connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]] +connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[13][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe171] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] -connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]] +connect_debug_port u_ila_0/probe171 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[14][7]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe172] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] -connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]] +connect_debug_port u_ila_0/probe172 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifo_reg[15][7]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe173] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] -connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]] +connect_debug_port u_ila_0/probe173 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsrfull}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe174] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] -connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]] +connect_debug_port u_ila_0/probe174 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txhrfull}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe175] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] -connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]] +connect_debug_port u_ila_0/probe175 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifofull}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe176] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] -connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]] +connect_debug_port u_ila_0/probe176 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifoempty}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe177] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] -connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]] +connect_debug_port u_ila_0/probe177 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifotail[3]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe178] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] -connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]] +connect_debug_port u_ila_0/probe178 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txfifohead[3]}]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe179] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] -connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]] +connect_debug_port u_ila_0/probe179 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txsr[11]}]] create_debug_port u_ila_0 probe set_property port_width 7 [get_debug_ports u_ila_0/probe180] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] -connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]] +connect_debug_port u_ila_0/probe180 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxtimeoutcnt[6]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe181] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] -connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]] +connect_debug_port u_ila_0/probe181 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotimeout}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe182] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] -connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]] +connect_debug_port u_ila_0/probe182 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoempty}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] -connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]] +connect_debug_port u_ila_0/probe183 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe184] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]] +connect_debug_port u_ila_0/probe184 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxbaudpulse}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe185] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe185] -connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]] +connect_debug_port u_ila_0/probe185 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohead[3]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe186] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe186] -connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]] +connect_debug_port u_ila_0/probe186 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotail[3]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe187] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe187] -connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]] +connect_debug_port u_ila_0/probe187 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe188] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe188] -connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]] +connect_debug_port u_ila_0/probe188 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]}]] create_debug_port u_ila_0 probe set_property port_width 31 [get_debug_ports u_ila_0/probe189] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe189] -connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]] +connect_debug_port u_ila_0/probe189 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbitunwrapped[30]}]] create_debug_port u_ila_0 probe set_property port_width 16 [get_debug_ports u_ila_0/probe190] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe190] -connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]] +connect_debug_port u_ila_0/probe190 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfullbit[15]}]] create_debug_port u_ila_0 probe set_property port_width 16 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] -connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]] +connect_debug_port u_ila_0/probe191 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrbit[15]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe192] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] -connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]] +connect_debug_port u_ila_0/probe192 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdata[7]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe193] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] -connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] +connect_debug_port u_ila_0/probe193 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe194] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] -connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] +connect_debug_port u_ila_0/probe194 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifohaserr}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe195] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] -connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]] +connect_debug_port u_ila_0/probe195 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxoverrunerr}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe196] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] -connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]] +connect_debug_port u_ila_0/probe196 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxframingerr}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe197] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] -connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]] +connect_debug_port u_ila_0/probe197 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe198] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] -connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]] +connect_debug_port u_ila_0/probe198 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[0]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe199] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] -connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]] +connect_debug_port u_ila_0/probe199 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[1]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe200] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] -connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]] +connect_debug_port u_ila_0/probe200 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[2]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe201] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] -connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]] +connect_debug_port u_ila_0/probe201 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[3]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe202] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] -connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]] +connect_debug_port u_ila_0/probe202 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[4]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe203] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] -connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]] +connect_debug_port u_ila_0/probe203 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[5]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe204] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] -connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]] +connect_debug_port u_ila_0/probe204 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[6]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe205] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] -connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]] +connect_debug_port u_ila_0/probe205 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[7]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe206] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] -connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]] +connect_debug_port u_ila_0/probe206 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[8]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe207] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] -connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]] +connect_debug_port u_ila_0/probe207 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[9]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe208] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] -connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]] +connect_debug_port u_ila_0/probe208 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifo[10]__0[10]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe209] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] -connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]] +connect_debug_port u_ila_0/probe209 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MEMRb}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe210] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] -connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]] +connect_debug_port u_ila_0/probe210 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXRDYb}]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe211] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] -connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]] +connect_debug_port u_ila_0/probe211 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe212] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] -connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]] +connect_debug_port u_ila_0/probe212 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe213] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] -connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]] +connect_debug_port u_ila_0/probe213 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]] create_debug_port u_ila_0 probe set_property port_width 70 [get_debug_ports u_ila_0/probe214] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] -connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]] +connect_debug_port u_ila_0/probe214 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe215] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] -connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]] +connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]] create_debug_port u_ila_0 probe set_property port_width 10 [get_debug_ports u_ila_0/probe216] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] +connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe217] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] -connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]] +connect_debug_port u_ila_0/probe217 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[0][5]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe218] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe218] -connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]] +connect_debug_port u_ila_0/probe218 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intClaim[1][5]} ]] create_debug_port u_ila_0 probe set_property port_width 7 [get_debug_ports u_ila_0/probe219] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe219] -connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]] +connect_debug_port u_ila_0/probe219 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[0][7]} ]] create_debug_port u_ila_0 probe set_property port_width 7 [get_debug_ports u_ila_0/probe220] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe220] -connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]] +connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/priorities_with_irqs[1][7]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe221] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] -connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]] +connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe222] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] -connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]] +connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]] create_debug_port u_ila_0 probe set_property port_width 53 [get_debug_ports u_ila_0/probe223] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe223] -connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]] +connect_debug_port u_ila_0/probe223 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[1][53]} ]] diff --git a/fpga/constraints/debug4.xdc b/fpga/constraints/debug4.xdc index 98200a3d1..170b38346 100644 --- a/fpga/constraints/debug4.xdc +++ b/fpga/constraints/debug4.xdc @@ -17,705 +17,705 @@ endgroup connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]] set_property port_width 64 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe1] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]] +connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe2] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] +connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe3] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe4] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe5] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe7] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe8] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe9] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe10] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe11] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe12] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] -connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe13] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] -connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe14] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe15] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 5 [get_debug_ports u_ila_0/probe17] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe18] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] -connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe19] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] -connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] create_debug_port u_ila_0 probe set_property port_width 63 [get_debug_ports u_ila_0/probe20] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe21] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe22] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe23] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe24] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]] +connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe25] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]] +connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe26] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2] ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe27] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]] +connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe28] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] -connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]] +connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe29] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]] +connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe30] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]] +connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe31] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] -connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]] +connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe32] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] -connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]] +connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe33] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] -connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] +connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe34] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] -connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]] +connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe35] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] -connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]] +connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe36] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] -connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]] +connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe37] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] -connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]] +connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe38] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]] +connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/mretM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe39] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]] +connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe40] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]] +connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe41] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]] +connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe42] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] -connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]] +connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe43] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] -connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]] +connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe44] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] -connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]] +connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe45] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] -connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/sretM ]] +connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/sretM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe46] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] -connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]] +connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe47] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] -connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]] +connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe48] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48] -connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]] +connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe49] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49] -connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/TrapM ]] +connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe50] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] -connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]] +connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe51] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] -connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]] +connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPWrongE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe52] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] -connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]] +connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFenceM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe53] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] -connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]] +connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/RetM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] -connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/core/hzu/LoadStallD ]] +connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe56] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] -connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/core/hzu/StoreStallD ]] +connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe57] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] -connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/hzu/MDUStallD ]] +connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe58] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] -connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CSRRdStallD ]] +connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe59] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] -connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]] +connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe60] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] -connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]] +connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe61] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] -connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]] +connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FPUStallD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe62] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] -connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/core/hzu/FCvtIntStallD ]] +connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FCvtIntStallD ]] create_debug_port u_ila_0 probe set_property port_width 7 [get_debug_ports u_ila_0/probe63] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63] -connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]] +connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[0][7]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe64] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64] -connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]] +connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe65] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65] -connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/hzu/EcallFaultM ]] +connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe66] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] -connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/hzu/BreakpointFaultM ]] +connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe67] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] -connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] +connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe68] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] -connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]] +connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe69] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallDCause]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe70] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] -connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe71] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] -connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]] +connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]] # StallW is StallM. trying to connect to StallW causes issues. create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe72] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72] -connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]] +connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe73] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73] -connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] +connect_debug_port u_ila_0/probe73 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe74] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74] -connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]] +connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe75] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75] -connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]] +connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe76] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76] -connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]] +connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe77] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77] -connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]] +connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe78] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78] -connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]] +connect_debug_port u_ila_0/probe78 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe79] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79] -connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] +connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe80] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80] -connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]] +connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHREADY ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe81] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81] -connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]] +connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHADDR[31]}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe82] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82] -connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]] +connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe83] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83] -connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] +connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] create_debug_port u_ila_0 probe set_property port_width 53 [get_debug_ports u_ila_0/probe84] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84] -connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]] +connect_debug_port u_ila_0/probe84 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/irqs_at_max_priority[0][53]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe85] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85] -connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]] +connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe86] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86] -connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]] +connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe87] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87] -connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]] +connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe88] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] -connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]] +connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe89] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89] -connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]] +connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe90] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90] -connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]] +connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe91] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91] -connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]] +connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe92] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92] -connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]] +connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe93] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93] -connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]] +connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe94] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94] -connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]] +connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe95] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95] -connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]] +connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe96] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96] -connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]] +connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe97] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97] -connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]] +connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe98] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98] -connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]] +connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe99] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] -connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]] +connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/SrcAM[63]}]] create_debug_port u_ila_0 probe set_property port_width 56 [get_debug_ports u_ila_0/probe100] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100] -connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]] +connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe101] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101] -connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] +connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe102] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102] -connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]] +connect_debug_port u_ila_0/probe102 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe103] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103] -connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] +connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 7 [get_debug_ports u_ila_0/probe104] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104] -connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]] +connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/threshMask[1][7]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe105] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105] -connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]] +connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe106] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106] -connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]] +connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe107] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107] -connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]] +connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe108] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108] -connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]] +connect_debug_port u_ila_0/probe108 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/RegWriteW]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe109] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109] -connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]] +connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/CSRWriteM} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe110] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110] -connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]] +connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe111] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111] -connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]] +connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63]}]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe112] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112] -connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]] +connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe113] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113] -connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]] +connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe114] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114] -connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]] +connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe115] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115] -connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]] +connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7]} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe116] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116] -connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]] +connect_debug_port u_ila_0/probe116 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe117] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117] -connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] +connect_debug_port u_ila_0/probe117 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe118] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118] -connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] +connect_debug_port u_ila_0/probe118 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe119] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119] -connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]] +connect_debug_port u_ila_0/probe119 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe120] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120] -connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]] +connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]] create_debug_port u_ila_0 probe set_property port_width 11 [get_debug_ports u_ila_0/probe121] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121] -connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]] +connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe122] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122] -connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]] +connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr} ]] create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe123] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123] -connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]] +connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1]} ]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe124] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124] -connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]] +connect_debug_port u_ila_0/probe124 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe125] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125] -connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]] +connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe126] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] -connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]] +connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe127] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127] -connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]] +connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe128] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128] -connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]] +connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe129] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129] -connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]] +connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe130] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130] -connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]] +connect_debug_port u_ila_0/probe130 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]] create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe131] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131] -connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]] +connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe132] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132] -connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]] +connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe133] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133] -connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]] +connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe134] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134] -connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]] +connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe135] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135] -connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]] +connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered} ]] create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe136] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136] -connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]] +connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe137] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137] -connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]] +connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] -connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] +connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] create_debug_port u_ila_0 probe diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 6a774fddc..0f32854de 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -82,8 +82,9 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { source ../constraints/small-debug.xdc -} else { - source ../constraints/debug4.xdc +} else { + # *** RT: 16 June 2023 must add back in the debugger + #source ../constraints/debug4.xdc } From 95960620a24dd0fca26359721b361bc5352dc647 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jun 2023 16:05:53 -0700 Subject: [PATCH 06/54] Removed redundant and not-covered atomic check from StoreStallD --- src/ieu/controller.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2314cb81e..838560ed1 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -339,5 +339,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write - assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)) | (|AtomicD)); + // atomic operations are also detected as MemRWD[1] + assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED))); endmodule From e2f927b4e6c52c5af903005536b6fe2d20098113 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Jun 2023 16:07:28 -0700 Subject: [PATCH 07/54] Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete --- testbench/tests.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 54167f73c..38f5bc2d8 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1466,7 +1466,7 @@ string arch64zbb[] = '{ "rv64i_m/B/src/andn-01.S", "rv64i_m/B/src/orn-01.S", "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/zext.h_64-01.S", "rv64i_m/B/src/sext.b-01.S", "rv64i_m/B/src/sext.h-01.S", "rv64i_m/B/src/clz-01.S", From 60931e7d5ccb2a0c3a86cd44908a45ad1c42f823 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 17 Jun 2023 20:38:51 -0700 Subject: [PATCH 08/54] Fixed embench to run all tests, even ones not in 1.0 --- benchmarks/embench/Makefile | 8 ++++++++ testbench/tests.vh | 16 ++++++++-------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 538fb64f9..3dba4daaa 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -16,10 +16,18 @@ buildsize: build_speedopt_size build_sizeopt_size # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size build_speedopt_speed: $(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" + # remove files not used in embench1.0 When changing to 2.0, restore these files + #rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum + #rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind + #rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done build_sizeopt_speed: $(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" + # remove files not used in embench1.0 When changing to 2.0, restore these files + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind + #rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size diff --git a/testbench/tests.vh b/testbench/tests.vh index 38f5bc2d8..f38f28056 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -75,26 +75,26 @@ string tvpaths[] = '{ string embench[] = '{ `EMBENCH, - "bd_speedopt_speed/src/nsichneu/nsichneu", - "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/aha-mont64/aha-mont64", "bd_speedopt_speed/src/crc32/crc32", + "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/edn/edn", "bd_speedopt_speed/src/huffbench/huffbench", "bd_speedopt_speed/src/matmult-int/matmult-int", - // "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back + "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back "bd_speedopt_speed/src/minver/minver", "bd_speedopt_speed/src/nettle-aes/nettle-aes", "bd_speedopt_speed/src/nettle-sha256/nettle-sha256", + "bd_speedopt_speed/src/nsichneu/nsichneu", "bd_speedopt_speed/src/nbody/nbody", "bd_speedopt_speed/src/picojpeg/picojpeg", - // "bd_speedopt_speed/src/primecount/primecount", + "bd_speedopt_speed/src/primecount/primecount", "bd_speedopt_speed/src/qrduino/qrduino", "bd_speedopt_speed/src/sglib-combined/sglib-combined", "bd_speedopt_speed/src/slre/slre", "bd_speedopt_speed/src/st/st", "bd_speedopt_speed/src/statemate/statemate", - // "bd_speedopt_speed/src/tarfind/tarfind", + "bd_speedopt_speed/src/tarfind/tarfind", "bd_speedopt_speed/src/ud/ud", "bd_speedopt_speed/src/wikisort/wikisort", "bd_sizeopt_speed/src/aha-mont64/aha-mont64", @@ -103,20 +103,20 @@ string tvpaths[] = '{ "bd_sizeopt_speed/src/edn/edn", "bd_sizeopt_speed/src/huffbench/huffbench", "bd_sizeopt_speed/src/matmult-int/matmult-int", - // "bd_sizeopt_speed/src/md5sum/md5sum", + "bd_sizeopt_speed/src/md5sum/md5sum", "bd_sizeopt_speed/src/minver/minver", "bd_sizeopt_speed/src/nbody/nbody", "bd_sizeopt_speed/src/nettle-aes/nettle-aes", "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256", "bd_sizeopt_speed/src/nsichneu/nsichneu", "bd_sizeopt_speed/src/picojpeg/picojpeg", - // "bd_sizeopt_speed/src/primecount/primecount", + "bd_sizeopt_speed/src/primecount/primecount", "bd_sizeopt_speed/src/qrduino/qrduino", "bd_sizeopt_speed/src/sglib-combined/sglib-combined", "bd_sizeopt_speed/src/slre/slre", "bd_sizeopt_speed/src/st/st", "bd_sizeopt_speed/src/statemate/statemate", - // "bd_sizeopt_speed/src/tarfind/tarfind", + "bd_sizeopt_speed/src/tarfind/tarfind", "bd_sizeopt_speed/src/ud/ud", "bd_sizeopt_speed/src/wikisort/wikisort" }; From 8242544efa082f5b030065ec2849b9e8388556ff Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 19 Jun 2023 12:15:48 -0500 Subject: [PATCH 09/54] Updated fpga wally wrapper to work with the ILA. --- fpga/generator/wally.tcl | 3 +-- fpga/src/wallypipelinedsocwrapper.sv | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 0f32854de..63dbc0b79 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -83,8 +83,7 @@ if {$board=="ArtyA7"} { source ../constraints/small-debug.xdc } else { - # *** RT: 16 June 2023 must add back in the debugger - #source ../constraints/debug4.xdc + source ../constraints/debug4.xdc } diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index 80adff7cf..0ba69d167 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -64,7 +64,7 @@ module wallypipelinedsocwrapper ( ); `include "parameter-defs.vh" - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + wallypipelinedsoc #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); From 25103176a040462ecf7c0b3ea6ddb5bae740a87b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 19 Jun 2023 12:28:30 -0500 Subject: [PATCH 10/54] Updated fpga wave config. --- fpga/generator/wave_config.wcfg | 458 ++++++++++++++++---------------- 1 file changed, 229 insertions(+), 229 deletions(-) diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg index 0d36926cf..81fc67f05 100644 --- a/fpga/generator/wave_config.wcfg +++ b/fpga/generator/wave_config.wcfg @@ -20,17 +20,17 @@ - + FullPathName - wallypipelinedsoc/core/PCM[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63:0] PCM[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/InstrM[31:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31:0] InstrM[31:0] HEXRADIX true @@ -40,37 +40,37 @@ rd label UNSIGNEDDECRADIX - + [11] [11] - + [10] [10] - + [9] [9] - + [8] [8] - + [7] [7] - + FullPathName - wallypipelinedsoc/core/InstrValidM + wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM InstrValidM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/TrapM + wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM TrapM true STYLE_DIGITAL @@ -78,66 +78,66 @@ CPU to LSU label - + FullPathName - wallypipelinedsoc/core/IEUAdrM[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63:0] IEUAdrM[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/MemRWM[1:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1:0] MemRWM[1:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/ReadDataM[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0] ReadDataM[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/WriteDataM[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63:0] WriteDataM[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/IEUAdrM[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/IEUAdrM[63:0] IEUAdrM[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/MemRWM[1:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/MemRWM[1:0] MemRWM[1:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/ReadDataM[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ReadDataM[63:0] ReadDataM[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/WriteDataM[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/WriteDataM[63:0] WriteDataM[63:0] HEXRADIX true @@ -150,49 +150,49 @@ interrupts label - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] MEDELEG_REGW[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0] MIDELEG_REGW[11:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/InterruptM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM InterruptM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] MEDELEG_REGW[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0] MIDELEG_REGW[11:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/InterruptM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/InterruptM InterruptM true STYLE_DIGITAL @@ -200,55 +200,55 @@ LSU to Bus label - + FullPathName - wallypipelinedsoc/core/lsu/LSUHADDR[31:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31:0] LSUHADDR[31:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/LSUHBURST[2:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHBURST[2:0] LSUHBURST[2:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/LSUHREADY + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY LSUHREADY true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/LSUHSIZE[1:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHSIZE[1:0] LSUHSIZE[1:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/LSUHWDATA[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63:0] LSUHWDATA[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/LSUHWRITE + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWRITE LSUHWRITE true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/HRDATA[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63:0] HRDATA[63:0] HEXRADIX true @@ -259,9 +259,9 @@ dcache label - + FullPathName - wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0] CurrState[3:0] HEXRADIX true @@ -273,71 +273,71 @@ EBU label - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0] HTRANS[1:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HWRITE + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWRITE HWRITE true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HBURST[2:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HBURST[2:0] HBURST[2:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HSIZE[2:0] HSIZE[2:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HADDR[31:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HADDR[31:0] HADDR[31:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/HRDATA[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/HRDATA[63:0] HRDATA[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HWDATA[63:0] HWDATA[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HREADY + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HREADY HREADY true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ebu.ebu/HRESP + wallypipelinedsocwrapper/wallypipelinedsoc/core/ebu.ebu/HRESP HRESP true STYLE_DIGITAL @@ -346,225 +346,225 @@ uart label - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/DTRb + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/DTRb DTRb true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/INTR + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/INTR INTR true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT1b OUT1b true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b OUT2b true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/RTSb + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RTSb RTSb true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/RXRDYb RXRDYb true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/SIN + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SIN SIN true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/SOUT + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/SOUT SOUT true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb TXRDYb true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLL[7:0] DLL[7:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/DLM[7:0] DLM[7:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/FCR[7:0] FCR[7:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/fifoenabled fifoenabled true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/IER[3:0] IER[3:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/intrID[2:0] intrID[2:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7:0] LCR[7:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/LSR[7:0] LSR[7:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MCR[4:0] MCR[4:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/MSR[3:0] MSR[3:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RBR[10:0] RBR[10:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataavailintr rxdataavailintr true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxdataready rxdataready true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP RXerrIP true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1 + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/RXerrIP_1 RXerrIP_1 true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifoentries[3:0] rxfifoentries[3:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxfifotriggered rxfifotriggered true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxparityerr rxparityerr true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/rxstate[1:0] rxstate[1:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/SCR[7:0] SCR[7:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1:0] + wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/uart.uart/u/txstate[1:0] txstate[1:0] HEXRADIX true @@ -574,79 +574,79 @@ faults label - + FullPathName - wallypipelinedsoc/core/hzu/BreakpointFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM BreakpointFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/EcallFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM EcallFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM IllegalInstrFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM InstrAccessFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM InstrPageFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM LoadAccessFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM LoadMisalignedFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM LoadPageFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM StoreAmoAccessFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM StoreAmoMisalignedFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM StoreAmoPageFaultM true STYLE_DIGITAL @@ -655,86 +655,86 @@ hazards label - + FullPathName - wallypipelinedsoc/core/hzu/BPPredWrongE + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BPPredWrongE BPPredWrongE true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/BreakpointFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/BreakpointFaultM BreakpointFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/CSRRdStallD + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRRdStallD CSRRdStallD true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM CSRWriteFencePendingDEM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/DivBusyE + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/DivBusyE DivBusyE true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/EcallFaultM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/EcallFaultM EcallFaultM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/FDivBusyE + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FDivBusyE FDivBusyE true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/IFUStallF + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/IFUStallF IFUStallF true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/LoadStallD + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LoadStallD LoadStallD true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/LSUStallM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/LSUStallM LSUStallM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/MDUStallD + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/MDUStallD MDUStallD true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/StoreStallD + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StoreStallD StoreStallD true STYLE_DIGITAL @@ -744,74 +744,74 @@ flush/stall label - + FullPathName - wallypipelinedsoc/core/hzu/FlushD + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushD FlushD true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/FlushE + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushE FlushE true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/FlushM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushM FlushM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/FlushW + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/FlushW FlushW true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/StallD + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallD StallD true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/StallE + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallE StallE true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/StallF + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallF StallF true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/hzu/StallM + wallypipelinedsocwrapper/wallypipelinedsoc/core/hzu/StallM StallM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0] csrs.SCAUSE_REGW[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63:0] MCAUSE_REGW[63:0] HEXRADIX true @@ -821,35 +821,35 @@ IFU label - + label - wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0] CurrState[3:0] HEXRADIX icache fsm true STYLE_DIGITAL - + label - wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0] CurrState[2:0] HEXRADIX ifu bus fsm true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ifu/PCNextF[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCNextF[63:0] PCNextF[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ifu/PCPF[55:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ifu/PCPF[55:0] PCPF[55:0] HEXRADIX true @@ -860,78 +860,78 @@ TLB label - + FullPathName - wallypipelinedsoc/core/lsu/DTLBMissM + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBMissM DTLBMissM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/DTLBWriteM + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/DTLBWriteM DTLBWriteM true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/ITLBMissF + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBMissF ITLBMissF true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/ITLBWriteF + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/ITLBWriteF ITLBWriteF true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0] MEPC_REGW[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0] SEPC_REGW[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0] rf[2]__0[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0] rf[4]__0[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0] rf[10]__0[63:0] HEXRADIX true STYLE_DIGITAL - + FullPathName - wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3:0] + wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.hptw/WalkerState[3:0] WalkerState[3:0] HEXRADIX true From 626a918668b043ec5e1e48b4848b8b367ee1a671 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Jun 2023 11:11:34 -0500 Subject: [PATCH 11/54] FPGA updates. --- fpga/constraints/debug2.xdc | 6 +++--- fpga/generator/wally.tcl | 2 +- fpga/src/wallypipelinedsocwrapper.sv | 2 +- testbench/testbench.sv | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 58e2fa643..f09acb6c1 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -1107,7 +1107,7 @@ connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsocwrapper/wa create_debug_port u_ila_0 probe set_property port_width 10 [get_debug_ports u_ila_0/probe216] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] +connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][10]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe217] @@ -1132,12 +1132,12 @@ connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsocwrapper/wa create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe221] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] -connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]] +connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][2]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe222] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] -connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]] +connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][2]} ]] create_debug_port u_ila_0 probe set_property port_width 53 [get_debug_ports u_ila_0/probe223] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 63dbc0b79..a28d42654 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -83,7 +83,7 @@ if {$board=="ArtyA7"} { source ../constraints/small-debug.xdc } else { - source ../constraints/debug4.xdc + source ../constraints/vcu-small-debug.xdc } diff --git a/fpga/src/wallypipelinedsocwrapper.sv b/fpga/src/wallypipelinedsocwrapper.sv index 0ba69d167..bdde7f4fc 100644 --- a/fpga/src/wallypipelinedsocwrapper.sv +++ b/fpga/src/wallypipelinedsocwrapper.sv @@ -34,7 +34,7 @@ module wallypipelinedsocwrapper ( input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [P.AHBW-1:0] HRDATAEXT, + input logic [64-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, // outputs to external memory, shared with uncore memory diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4cab1a105..9ed35496d 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -35,7 +35,7 @@ module testbench; /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; parameter TEST="none"; - parameter PrintHPMCounters=0; + parameter PrintHPMCounters=1; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; From 394c7ac9afe8133386f6914495a690d950d00ac9 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 20 Jun 2023 17:26:54 -0500 Subject: [PATCH 12/54] Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file --- sim/FPbuild.txt | 18 +- sim/sim-testfloat-batch | 3 - sim/testfloat.do | 14 +- testbench/testbench-fp.sv | 2471 +++++++++++++++++++------------------ 4 files changed, 1255 insertions(+), 1251 deletions(-) diff --git a/sim/FPbuild.txt b/sim/FPbuild.txt index edb4a645c..99f414804 100644 --- a/sim/FPbuild.txt +++ b/sim/FPbuild.txt @@ -34,18 +34,14 @@ other FP tests given by the great SoftFloat/TestFloat output. 4a.) Each test will test all its vectors - if you want to test a subset of the vectors (e.g., only binary16), you should modify the -cvw/testbench/tests-fp.h and comment out the tests you do not want to -test. The best way to do this is to comment out each item out with -the // comment option in SV. For example, - -string f128div[] = '{ -// "f128_div_rne.tv", -// "f128_div_rz.tv", -// "f128_div_ru.tv", -// "f128_div_rd.tv", -// "f128_div_rnm.tv" -}; +testfloat.do in the sim directory. Change the TEST_SIZE="all" to the +specific test you want to run. For example, if you want to run only +binary16, you should set this variable to TEST_SIZE="HP". +4b.) If you want to turn off the generation of wlf files while running +sim-testfloat-batch, you can modify testfloat.do in the sim +directory. Inside this DO file, modify the WAV file to 0 --> i.e., +set "quietly set WAV 0;" diff --git a/sim/sim-testfloat-batch b/sim/sim-testfloat-batch index 4cb03792e..31ff21a6c 100755 --- a/sim/sim-testfloat-batch +++ b/sim/sim-testfloat-batch @@ -10,6 +10,3 @@ # sqrt - test square root # all - test everything -# nowave for 2nd argument supresses wlf files - -vsim -c -do "do testfloat.do rv64fpquad $1 $2" \ No newline at end of file diff --git a/sim/testfloat.do b/sim/testfloat.do index c8e8ae7b4..ffa03dc8d 100644 --- a/sim/testfloat.do +++ b/sim/testfloat.do @@ -27,12 +27,16 @@ vlib work # $num = the added words after the call vlog +incdir+../config/$1 +incdir+../config/shared ../src/wally/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 -vsim -voptargs=+acc work.testbenchfp -G TEST=$2 +# Change TEST_SIZE to only test certain FP width +# values are QP, DP, SP, HP +vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" -# Determine if nowave argument is provided -# this removes any output to a wlf or wave window to reduce -# disk space. -if {($argc > 2) && ($3 eq "nowave")} { +# Set WAV variable to avoid having any output to wave (to limit disk space) +quietly set WAV 1; + +# Determine if nowave argument is provided this removes any output to +# a wlf or wave window to reduce disk space. +if {$WAV eq 0} { puts "No wave output is selected" } else { puts "wave output is selected" diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 63660b025..413dc11e5 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -1,8 +1,9 @@ /////////////////////////////////////////// // -// Written: me@KatherineParry.com +// Written: me@KatherineParry.com, james.stine@okstate.edu // Modified: 7/5/2022 // Modified: 4/2/2023 +// Modified: 6/19/2023 // // Purpose: Testbench for Testfloat // @@ -30,1323 +31,1329 @@ import cvw::*; module testbenchfp; - parameter TEST="none"; + parameter TEST="none"; + parameter TEST_SIZE="none"; - string Tests[]; // list of tests to be run - logic [2:0] OpCtrl[]; // list of op controls - logic [2:0] Unit[]; // list of units being tested - logic WriteInt[]; // Is being written to integer resgiter - logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 - logic [1:0] Fmt[]; // list of formats for the other units + string Tests[]; // list of tests to be run + logic [2:0] OpCtrl[]; // list of op controls + logic [2:0] Unit[]; // list of units being tested + logic WriteInt[]; // Is being written to integer resgiter + logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 + logic [1:0] Fmt[]; // list of formats for the other units - logic clk=0; - logic [31:0] TestNum=0; // index for the test - logic [31:0] OpCtrlNum=0; // index for OpCtrl - logic [31:0] errors=0; // how many errors - logic [31:0] VectorNum=0; // index for test vector - logic [31:0] FrmNum=0; // index for rounding mode - logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic clk=0; + logic [31:0] TestNum=0; // index for the test + logic [31:0] OpCtrlNum=0; // index for OpCtrl + logic [31:0] errors=0; // how many errors + logic [31:0] VectorNum=0; // index for test vector + logic [31:0] FrmNum=0; // index for rounding mode + logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors - logic [1:0] FmtVal; // value of the current Fmt - logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal - logic WriteIntVal; // value of the current WriteInt - logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat - logic [`FLEN-1:0] XPostBox; // inputs read from TestFloat - logic [`XLEN-1:0] SrcA; // integer input - logic [`FLEN-1:0] Ans; // correct answer from TestFloat - logic [`FLEN-1:0] Res; // result from other units - logic [4:0] AnsFlg; // correct flags read from testfloat - logic [4:0] ResFlg, Flg; // Result flags - logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad - logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit - logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit - logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags - logic AnsNaN, ResNaN, NaNGood; - logic Xs, Ys, Zs; // sign of the inputs - logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs - logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs - logic XNaN, YNaN, ZNaN; // is the input NaN - logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN - logic XSubnorm, ZSubnorm; // is the input denormalized - logic XInf, YInf, ZInf; // is the input infinity - logic XZero, YZero, ZZero; // is the input zero - logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones - logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) - logic IntZero; - logic CvtResSgnE; - logic [`NE:0] CvtCalcExpE; // the calculated expoent - logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by - logic [`DIVb:0] Quot; - logic CvtResSubnormUfE; - logic DivStart, FDivBusyE, OldFDivBusyE; - logic reset = 1'b0; - logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; - logic [`DURLEN-1:0] Dur; + logic [1:0] FmtVal; // value of the current Fmt + logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal + logic WriteIntVal; // value of the current WriteInt + logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [`FLEN-1:0] XPostBox; // inputs read from TestFloat + logic [`XLEN-1:0] SrcA; // integer input + logic [`FLEN-1:0] Ans; // correct answer from TestFloat + logic [`FLEN-1:0] Res; // result from other units + logic [4:0] AnsFlg; // correct flags read from testfloat + logic [4:0] ResFlg, Flg; // Result flags + logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad + logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit + logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit + logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags + logic AnsNaN, ResNaN, NaNGood; + logic Xs, Ys, Zs; // sign of the inputs + logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs + logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs + logic XNaN, YNaN, ZNaN; // is the input NaN + logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN + logic XSubnorm, ZSubnorm; // is the input denormalized + logic XInf, YInf, ZInf; // is the input infinity + logic XZero, YZero, ZZero; // is the input zero + logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones + logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) + logic IntZero; + logic CvtResSgnE; + logic [`NE:0] CvtCalcExpE; // the calculated expoent + logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by + logic [`DIVb:0] Quot; + logic CvtResSubnormUfE; + logic DivStart, FDivBusyE, OldFDivBusyE; + logic reset = 1'b0; + logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; + logic [`DURLEN-1:0] Dur; - // in-between FMA signals - logic Mult; - logic Ss; - logic [`NE+1:0] Pe; - logic [`NE+1:0] Se; - logic ASticky; - logic KillProd; - logic [$clog2(3*`NF+5)-1:0] SCnt; - logic [3*`NF+3:0] Sm; - logic InvA; - logic NegSum; - logic As; - logic Ps; - logic DivSticky; - logic DivDone; - logic DivNegSticky; - logic [`NE+1:0] DivCalcExp; - logic divsqrtop; + // in-between FMA signals + logic Mult; + logic Ss; + logic [`NE+1:0] Pe; + logic [`NE+1:0] Se; + logic ASticky; + logic KillProd; + logic [$clog2(3*`NF+5)-1:0] SCnt; + logic [3*`NF+3:0] Sm; + logic InvA; + logic NegSum; + logic As; + logic Ps; + logic DivSticky; + logic DivDone; + logic DivNegSticky; + logic [`NE+1:0] DivCalcExp; + logic divsqrtop; // Missing logic vectors fdivsqrt - logic [2:0] Funct3E; - logic [2:0] Funct3M; - logic FlushE; - logic IFDivStartE, FDivDoneE; - logic [`NE+1:0] QeM; - logic [`DIVb:0] QmM; - logic [`XLEN-1:0] FIntDivResultM; + logic [2:0] Funct3E; + logic [2:0] Funct3M; + logic FlushE; + logic IFDivStartE, FDivDoneE; + logic [`NE+1:0] QeM; + logic [`DIVb:0] QmM; + logic [`XLEN-1:0] FIntDivResultM; `include "parameter-defs.vh" - - /////////////////////////////////////////////////////////////////////////////////////////////// - // ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| ||| - // ||| ||| ||| ||| ||| ||| ||| - // ||| |||||||| ||||||| ||| ||||||| |||||||| ||| - // ||| ||| ||| ||| ||| ||| ||| - // ||| |||||||| ||||||| ||| ||||||| |||||||| ||||||||| + /////////////////////////////////////////////////////////////////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////////////////////// + // ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||||||||| - // select tests relevent to the specified configuration - // cvtint - test integer conversion unit (fcvtint) - // cvtfp - test floating-point conversion unit (fcvtfp) - // cmp - test comparison unit's LT, LE, EQ opperations (fcmp) - // add - test addition - // sub - test subtraction - // div - test division - // sqrt - test square root - // all - test all of the above - initial begin - $display("TEST is %s", TEST); - if (`Q_SUPPORTED) begin // if Quad percision is supported - if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion - // add the 128-bit cvtint tests to the to-be-tested list - Tests = {Tests, f128rv32cvtint}; - // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; - // add what unit is used and the fmt to their lists (one for each test) - for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b11}; - end - if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions - Tests = {Tests, f128rv64cvtint}; + /////////////////////////////////////////////////////////////////////////////////////////////// + + // select tests relevent to the specified configuration + // cvtint - test integer conversion unit (fcvtint) + // cvtfp - test floating-point conversion unit (fcvtfp) + // cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + // add - test addition + // sub - test subtraction + // div - test division + // sqrt - test square root + // all - test all of the above + + initial begin + $display("\nThe start of simulation..."); + $display("This simulation for TEST is %s", TEST); + $display("This simulation for TEST is of the operand size of %s", TEST_SIZE); + if (`Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported + if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion + // add the 128-bit cvtint tests to the to-be-tested list + Tests = {Tests, f128rv32cvtint}; // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b11}; end - end - end - // if the floating-point conversions are being tested - if (TEST === "cvtfp" | TEST === "all") begin - if(`D_SUPPORTED) begin // if double precision is supported - // add the 128 <-> 64 bit conversions to the to-be-tested list - Tests = {Tests, f128f64cvt}; - // add the op-ctrls (i.e. the format of the result) - OpCtrl = {OpCtrl, 3'b01, 3'b11}; - WriteInt = {WriteInt, 1'b0, 1'b0}; - // add the unit being tested and fmt (input format) - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b11}; - end - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if(`F_SUPPORTED) begin // if single precision is supported - // add the 128 <-> 32 bit conversions to the to-be-tested list - Tests = {Tests, f128f32cvt}; - // add the op-ctrls (i.e. the format of the result) - OpCtrl = {OpCtrl, 3'b00, 3'b11}; - WriteInt = {WriteInt, 1'b0, 1'b0}; - // add the unit being tested and fmt (input format) - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b11}; - end - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if(`ZFH_SUPPORTED) begin // if half precision is supported - // add the 128 <-> 16 bit conversions to the to-be-tested list - Tests = {Tests, f128f16cvt}; - // add the op-ctrls (i.e. the format of the result) - OpCtrl = {OpCtrl, 3'b10, 3'b11}; - WriteInt = {WriteInt, 1'b0, 1'b0}; - // add the unit being tested and fmt (input format) - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b11}; - end - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b10}; - end - end + if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions + Tests = {Tests, f128rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + // if the floating-point conversions are being tested + if (TEST === "cvtfp" | TEST === "all") begin + if(`D_SUPPORTED) begin // if double precision is supported + // add the 128 <-> 64 bit conversions to the to-be-tested list + Tests = {Tests, f128f64cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b01, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if(`F_SUPPORTED) begin // if single precision is supported + // add the 128 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f128f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 128 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f128f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested + // add the compare tests/op-ctrls/unit/fmt + Tests = {Tests, f128cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the addition tests/op-ctrls/unit/fmt + Tests = {Tests, f128add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the subtraction tests/op-ctrls/unit/fmt + Tests = {Tests, f128sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the multiply tests/op-ctrls/unit/fmt + Tests = {Tests, f128mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f128div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f128sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested + Tests = {Tests, f128fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end end - if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested - // add the compare tests/op-ctrls/unit/fmt - Tests = {Tests, f128cmp}; - OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; - for(int i = 0; i<15; i++) begin - Unit = {Unit, `CMPUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "add" | TEST === "all") begin // if addition is being tested - // add the addition tests/op-ctrls/unit/fmt - Tests = {Tests, f128add}; - OpCtrl = {OpCtrl, `ADD_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested - // add the subtraction tests/op-ctrls/unit/fmt - Tests = {Tests, f128sub}; - OpCtrl = {OpCtrl, `SUB_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested - // add the multiply tests/op-ctrls/unit/fmt - Tests = {Tests, f128mul}; - OpCtrl = {OpCtrl, `MUL_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the divide tests/op-ctrls/unit/fmt - Tests = {Tests, f128div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested - // add the square-root tests/op-ctrls/unit/fmt - Tests = {Tests, f128sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested - Tests = {Tests, f128fma}; - OpCtrl = {OpCtrl, `FMA_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - end - if (`D_SUPPORTED) begin // if double precision is supported - if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested - Tests = {Tests, f64rv32cvtint}; - // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; - // add what unit is used and the fmt to their lists (one for each test) - for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b01}; - end - if (`XLEN == 64) begin // if 64-bit integers are being supported - Tests = {Tests, f64rv64cvtint}; + if (`D_SUPPORTED & (TEST_SIZE == "DP" | TEST_SIZE == "all")) begin // if double precision is supported + if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f64rv32cvtint}; // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b01}; end - end + if (`XLEN == 64) begin // if 64-bit integers are being supported + Tests = {Tests, f64rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested + if(`F_SUPPORTED) begin // if single precision is supported + // add the 64 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f64f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b01}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 64 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f64f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b01}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested + Tests = {Tests, f64fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end end - if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested - if(`F_SUPPORTED) begin // if single precision is supported - // add the 64 <-> 32 bit conversions to the to-be-tested list - Tests = {Tests, f64f32cvt}; - // add the op-ctrls (i.e. the format of the result) - OpCtrl = {OpCtrl, 3'b00, 3'b01}; - WriteInt = {WriteInt, 1'b0, 1'b0}; - // add the unit being tested and fmt (input format) - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b01}; - end - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if(`ZFH_SUPPORTED) begin // if half precision is supported - // add the 64 <-> 16 bit conversions to the to-be-tested list - Tests = {Tests, f64f16cvt}; - // add the op-ctrls (i.e. the format of the result) - OpCtrl = {OpCtrl, 3'b10, 3'b01}; - WriteInt = {WriteInt, 1'b0, 1'b0}; - // add the unit being tested and fmt (input format) - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b01}; - end - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - end - if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64cmp}; - OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; - for(int i = 0; i<15; i++) begin - Unit = {Unit, `CMPUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "add" | TEST === "all") begin // if addition is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64add}; - OpCtrl = {OpCtrl, `ADD_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "sub" | TEST === "all") begin // if subtration is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64sub}; - OpCtrl = {OpCtrl, `SUB_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64mul}; - OpCtrl = {OpCtrl, `MUL_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested - Tests = {Tests, f64fma}; - OpCtrl = {OpCtrl, `FMA_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - end - if (`F_SUPPORTED) begin // if single precision being supported - if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested - Tests = {Tests, f32rv32cvtint}; - // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; - // add what unit is used and the fmt to their lists (one for each test) - for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b00}; - end - if (`XLEN == 64) begin // if 64-bit integers are supported - Tests = {Tests, f32rv64cvtint}; + if (`F_SUPPORTED & (TEST_SIZE == "SP" | TEST_SIZE == "all")) begin // if single precision being supported + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f32rv32cvtint}; // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b00}; end - end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f32rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested + if(`ZFH_SUPPORTED) begin + // add the 32 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f32f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b00}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiply is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + Tests = {Tests, f32fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end end - if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested - if(`ZFH_SUPPORTED) begin - // add the 32 <-> 16 bit conversions to the to-be-tested list - Tests = {Tests, f32f16cvt}; - // add the op-ctrls (i.e. the format of the result) - OpCtrl = {OpCtrl, 3'b10, 3'b00}; - WriteInt = {WriteInt, 1'b0, 1'b0}; - // add the unit being tested and fmt (input format) - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b00}; - end - for(int i = 0; i<5; i++) begin - Unit = {Unit, `CVTFPUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - end - if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32cmp}; - OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; - for(int i = 0; i<15; i++) begin - Unit = {Unit, `CMPUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "add" | TEST === "all") begin // if addition is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32add}; - OpCtrl = {OpCtrl, `ADD_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "sub" | TEST === "all") begin // if subtration is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32sub}; - OpCtrl = {OpCtrl, `SUB_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "mul" | TEST === "all") begin // if multiply is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32mul}; - OpCtrl = {OpCtrl, `MUL_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "fma" | TEST === "all") begin // if fma is being tested - Tests = {Tests, f32fma}; - OpCtrl = {OpCtrl, `FMA_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - end - if (`ZFH_SUPPORTED) begin // if half precision supported - if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested - Tests = {Tests, f16rv32cvtint}; - // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; - // add what unit is used and the fmt to their lists (one for each test) - for(int i = 0; i<20; i++) begin - Unit = {Unit, `CVTINTUNIT}; - Fmt = {Fmt, 2'b10}; - end - if (`XLEN == 64) begin // if 64-bit integers are supported - Tests = {Tests, f16rv64cvtint}; + if (`ZFH_SUPPORTED & (TEST_SIZE == "HP" | TEST_SIZE == "all")) begin // if half precision supported + if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested + Tests = {Tests, f16rv32cvtint}; // add the op-codes for these tests to the op-code list - OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; // add what unit is used and the fmt to their lists (one for each test) for(int i = 0; i<20; i++) begin Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b10}; end - end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f16rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + Tests = {Tests, f16fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end end - if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16cmp}; - OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; - WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; - for(int i = 0; i<15; i++) begin - Unit = {Unit, `CMPUNIT}; - Fmt = {Fmt, 2'b10}; - end + + // check if nothing is being tested + if (Tests.size() == 0) begin + $display("TEST %s not supported in this configuration", TEST); + $stop; end - if (TEST === "add" | TEST === "all") begin // if addition is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16add}; - OpCtrl = {OpCtrl, `ADD_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16sub}; - OpCtrl = {OpCtrl, `SUB_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16mul}; - OpCtrl = {OpCtrl, `MUL_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - if (TEST === "fma" | TEST === "all") begin // if fma is being tested - Tests = {Tests, f16fma}; - OpCtrl = {OpCtrl, `FMA_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `FMAUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - end + end - // check if nothing is being tested - if (Tests.size() == 0) begin - $display("TEST %s not supported in this configuration", TEST); - $stop; - end - end + /////////////////////////////////////////////////////////////////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////////////////////// + // ||||||||| |||||||| ||||||||| ||||||| ||||||||| |||||||| ||||||| ||||||||| + // ||| ||| ||| ||| ||| || || ||| ||| ||| ||| + // |||||||| |||||||| ||||||||| || || ||| |||||||| ||||||| ||| + // ||| || ||| ||| ||| || || ||| ||| ||| ||| + // ||| ||| |||||||| ||| ||| ||||||| ||| |||||||| ||||||| ||| - // ||||||||| |||||||| ||||||||| ||||||| ||||||||| |||||||| ||||||| ||||||||| - // ||| ||| ||| ||| ||| || || ||| ||| ||| ||| - // |||||||| |||||||| ||||||||| || || ||| |||||||| ||||||| ||| - // ||| || ||| ||| ||| || || ||| ||| ||| ||| - // ||| ||| |||||||| ||| ||| ||||||| ||| |||||||| ||||||| ||| + /////////////////////////////////////////////////////////////////////////////////////////////// - /////////////////////////////////////////////////////////////////////////////////////////////// + // Read the first test + initial begin + //string testname = {`PATH, Tests[TestNum]}; + string p = `PATH; + string testname; + string tt0; + tt0 = $psprintf("%s", Tests[TestNum]); + testname = {p, tt0}; + // $display("Here you are %s", testname); + $display("\n\nRunning %s vectors ", Tests[TestNum]); + $readmemh(testname, TestVectors); + // set the test index to 0 + TestNum = 0; + end - // Read the first test - initial begin - $display("\n\nRunning %s vectors", Tests[TestNum]); - $readmemh({`PATH, Tests[TestNum]}, TestVectors); - // set the test index to 0 - TestNum = 0; - end + // set a the signals for all tests + always_comb UnitVal = Unit[TestNum]; + always_comb FmtVal = Fmt[TestNum]; + always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; + always_comb WriteIntVal = WriteInt[OpCtrlNum]; + always_comb FrmVal = Frm[FrmNum]; - // set a the signals for all tests - always_comb UnitVal = Unit[TestNum]; - always_comb FmtVal = Fmt[TestNum]; - always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; - always_comb WriteIntVal = WriteInt[OpCtrlNum]; - always_comb FrmVal = Frm[FrmNum]; + // modify the format signal if only 2 percisions supported + // - 1 for the larger precision + // - 0 for the smaller precision + always_comb begin + if(`FMTBITS == 1) ModFmt = FmtVal == `FMT; + else ModFmt = FmtVal; + end - // modify the format signal if only 2 percisions supported - // - 1 for the larger precision - // - 0 for the smaller precision - always_comb begin - if(`FMTBITS == 1) ModFmt = FmtVal == `FMT; - else ModFmt = FmtVal; - end + // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector + readvectors #(P) readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), + .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, + .Xs, .Ys, .Zs, .Unit(UnitVal), + .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), + .Xm, .Ym, .Zm, .DivStart, + .XNaN, .YNaN, .ZNaN, + .XSNaN, .YSNaN, .ZSNaN, + .XSubnorm, .ZSubnorm, + .XZero, .YZero, .ZZero, + .XInf, .YInf, .ZInf, .XExpMax, + .X, .Y, .Z, .XPostBox); - // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector - readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), - .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, - .Xs, .Ys, .Zs, .Unit(UnitVal), - .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), - .Xm, .Ym, .Zm, .DivStart, - .XNaN, .YNaN, .ZNaN, - .XSNaN, .YSNaN, .ZSNaN, - .XSubnorm, .ZSubnorm, - .XZero, .YZero, .ZZero, - .XInf, .YInf, .ZInf, .XExpMax, - .X, .Y, .Z, .XPostBox); + /////////////////////////////////////////////////////////////////////////////////////////////// + // ||||||| ||| ||| ||||||||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||||||| ||||||||| ||| - /////////////////////////////////////////////////////////////////////////////////////////////// + /////////////////////////////////////////////////////////////////////////////////////////////// - // ||||||| ||| ||| ||||||||| - // ||| ||| ||| ||| ||| - // ||| ||| ||| ||| ||| - // ||| ||| ||| ||| ||| - // ||||||| ||||||||| ||| - - /////////////////////////////////////////////////////////////////////////////////////////////// - - // instantiate devices under test - if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma - fma #(P) fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), - .Xe(Xe), .Ye(Ye), .Ze(Ze), - .Xm(Xm), .Ym(Ym), .Zm(Zm), - .XZero, .YZero, .ZZero, .Ss, .Se, - .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps, - .ASticky); - end - - postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]), - .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp), - .Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss), - .XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE), - .XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE), - .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal), - .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero, - .FmaASticky(ASticky), .FmaSe(Se), - .FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), - .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); - - if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt - fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), - .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero, - .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); - end - - if (TEST === "cmp" | TEST === "all") begin: fcmp - fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, - .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), - .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); - end - if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt - fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), - .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), - .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), - .XNaNE(XNaN), .YNaNE(YNaN), - .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0), - .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp), - .QmM(Quot), - .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M), - .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM), - .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE)); - end - - assign CmpFlg[3:0] = 0; - - // produce clock - always begin - clk = 1; #5; clk = 0; #5; - end - - // Provide reset for divsqrt to reset state to IDLE - // Previous version did not initiate a divide due to missing state - // information. This starts the FSM by putting the fdivsqrt into - // the IDLE state. - initial - begin - #0 reset = 1'b1; - #25 reset = 1'b0; - end - -/////////////////////////////////////////////////////////////////////////////////////////////// - -// ||||| ||| |||||||||| ||||| ||| -// ||||||| ||| ||| ||| ||||||| ||| -// |||| ||| ||| |||||||||| |||| ||| ||| -// |||| ||| ||| ||| ||| |||| ||| ||| -// |||| ||| ||| ||| ||| |||| ||| ||| -// |||| |||||| ||| ||| |||| |||||| - -/////////////////////////////////////////////////////////////////////////////////////////////// - - // Check if the correct answer and result is a NaN - always_comb begin - if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin - // an integer output can't be a NaN - AnsNaN = 1'b0; - ResNaN = 1'b0; - end - else if (UnitVal === `CVTFPUNIT) begin - case (OpCtrlVal[1:0]) - 4'b11: begin // quad - AnsNaN = &Ans[`Q_LEN-2:`NF]&(|Ans[`Q_NF-1:0]); - ResNaN = &Res[`Q_LEN-2:`NF]&(|Res[`Q_NF-1:0]); - end - 4'b01: begin // double - AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); - ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); - end - 4'b00: begin // single - AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); - ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); - end - 4'b10: begin // half - AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); - ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); - end - endcase - end - else begin - case (FmtVal) - 4'b11: begin // quad - AnsNaN = &Ans[`Q_LEN-2:`Q_NF]&(|Ans[`Q_NF-1:0]); - ResNaN = &Res[`Q_LEN-2:`Q_NF]&(|Res[`Q_NF-1:0]); - end - 4'b01: begin // double - AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); - ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); - end - 4'b00: begin // single - AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); - ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); - end - 4'b10: begin // half - AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); - ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); - end - endcase - end - end -always_comb begin - // select the result to check - case (UnitVal) - `FMAUNIT: Res = FpRes; - `DIVUNIT: Res = FpRes; - `CMPUNIT: Res = CmpRes; - `CVTINTUNIT: if(WriteIntVal) Res = IntRes; else Res = FpRes; - `CVTFPUNIT: Res = FpRes; - endcase - - // select the flag to check - case (UnitVal) - `FMAUNIT: ResFlg = Flg; - `DIVUNIT: ResFlg = Flg; - `CMPUNIT: ResFlg = CmpFlg; - `CVTINTUNIT: ResFlg = Flg; - `CVTFPUNIT: ResFlg = Flg; - endcase -end - - logic ResMatch, FlagMatch, CheckNow; - -always @(posedge clk) - OldFDivBusyE = FDivDoneE; - -// check results on falling edge of clk -always @(negedge clk) begin - - - // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: - // - the sign of the NaN does not matter for the opperations being tested - // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter - if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) - case (FmtVal) - 4'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | - (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | - (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); - 4'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | - (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | - (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); - 4'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | - (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | - (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); - 4'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | - (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | - (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]}))); - endcase - else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format - case (OpCtrlVal[1:0]) - 2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | - (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | - (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); - 2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | - (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | - (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); - 2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | - (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | - (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); - 2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | - (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | - (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); - endcase - else NaNGood = 1'b0; // integers can't be NaNs - - - /////////////////////////////////////////////////////////////////////////////////////////////// - - // ||||||| ||| ||| ||||||| ||||||| ||| ||| - // ||| ||| ||| ||| ||| ||| ||| - // ||| |||||||||| ||||||| ||| |||||| - // ||| ||| ||| ||| ||| ||| ||| - // ||||||| ||| ||| ||||||| ||||||| ||| ||| - - /////////////////////////////////////////////////////////////////////////////////////////////// - - // check if result is correct - // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) - // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin - assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); - assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); - assign divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; - assign DivDone = OldFDivBusyE & ~FDivBusyE; - - //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL; - assign CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); - if(~(ResMatch & FlagMatch) & CheckNow) begin -// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin - errors += 1; - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("Error in %s", Tests[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; - end - - // TestFloat sets the result to all 1's when there is an invalid result, however in - // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says - // for an unsigned integer result 0 is also okay - - // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but - // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... - else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[`XLEN-1:0] === (`XLEN)'(0))) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | - (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin - errors += 1; - $display("There is an error in %s", Tests[TestNum]); - $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); - $stop; - end - - // Add extra clock cycles in beginning for fdivsqrt to adequate reset state - if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin - repeat (12) - @(posedge clk); - if (reset != 1'b1) - VectorNum += 1; // increment the vector - end + // instantiate devices under test + if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma + fma #(P) fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), + .Xe(Xe), .Ye(Ye), .Ze(Ze), + .Xm(Xm), .Ym(Ym), .Zm(Zm), + .XZero, .YZero, .ZZero, .Ss, .Se, + .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps, + .ASticky); + end - if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof + postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]), + .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp), + .Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss), + .XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE), + .XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE), + .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal), + .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero, + .FmaASticky(ASticky), .FmaSe(Se), + .FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), + .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); + + if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt + fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), + .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero, + .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), + .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); + end - // increment the test - TestNum += 1; + if (TEST === "cmp" | TEST === "all") begin: fcmp + fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, + .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), + .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); + end + if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt + fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), + .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), + .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), + .XNaNE(XNaN), .YNaNE(YNaN), + .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0), + .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp), + .QmM(Quot), + .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M), + .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM), + .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE)); + end - // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}}; - // read next files - $readmemh({`PATH, Tests[TestNum]}, TestVectors); + assign CmpFlg[3:0] = 0; - // set the vector index back to 0 - VectorNum = 0; - // incemet the operation if all the rounding modes have been tested - if(FrmNum === 4) OpCtrlNum += 1; - // increment the rounding mode or loop back to rne - if(FrmNum < 4) FrmNum += 1; - else FrmNum = 0; + // produce clock + always begin + clk = 1; #5; clk = 0; #5; + end - // if no more Tests - finish - if(Tests[TestNum] === "") begin - $display("\nAll Tests completed with %d errors\n", errors); - $stop; - end + // Provide reset for divsqrt to reset state to IDLE + // Previous version did not initiate a divide due to missing state + // information. This starts the FSM by putting the fdivsqrt into + // the IDLE state. + initial + begin + #0 reset = 1'b1; + #25 reset = 1'b0; + end + + /////////////////////////////////////////////////////////////////////////////////////////////// - $display("Running %s vectors", Tests[TestNum]); - end - end + // ||||| ||| |||||||||| ||||| ||| + // ||||||| ||| ||| ||| ||||||| ||| + // |||| ||| ||| |||||||||| |||| ||| ||| + // |||| ||| ||| ||| ||| |||| ||| ||| + // |||| ||| ||| ||| ||| |||| ||| ||| + // |||| |||||| ||| ||| |||| |||||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // Check if the correct answer and result is a NaN + always_comb begin + if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin + // an integer output can't be a NaN + AnsNaN = 1'b0; + ResNaN = 1'b0; + end + else if (UnitVal === `CVTFPUNIT) begin + case (OpCtrlVal[1:0]) + 4'b11: begin // quad + AnsNaN = &Ans[`Q_LEN-2:`NF]&(|Ans[`Q_NF-1:0]); + ResNaN = &Res[`Q_LEN-2:`NF]&(|Res[`Q_NF-1:0]); + end + 4'b01: begin // double + AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); + ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); + end + 4'b00: begin // single + AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); + ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); + end + 4'b10: begin // half + AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); + ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); + end + endcase + end + else begin + case (FmtVal) + 4'b11: begin // quad + AnsNaN = &Ans[`Q_LEN-2:`Q_NF]&(|Ans[`Q_NF-1:0]); + ResNaN = &Res[`Q_LEN-2:`Q_NF]&(|Res[`Q_NF-1:0]); + end + 4'b01: begin // double + AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); + ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); + end + 4'b00: begin // single + AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); + ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); + end + 4'b10: begin // half + AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); + ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); + end + endcase + end + end + always_comb begin + // select the result to check + case (UnitVal) + `FMAUNIT: Res = FpRes; + `DIVUNIT: Res = FpRes; + `CMPUNIT: Res = CmpRes; + `CVTINTUNIT: if(WriteIntVal) Res = IntRes; else Res = FpRes; + `CVTFPUNIT: Res = FpRes; + endcase + + // select the flag to check + case (UnitVal) + `FMAUNIT: ResFlg = Flg; + `DIVUNIT: ResFlg = Flg; + `CMPUNIT: ResFlg = CmpFlg; + `CVTINTUNIT: ResFlg = Flg; + `CVTFPUNIT: ResFlg = Flg; + endcase + end + + logic ResMatch, FlagMatch, CheckNow; + + always @(posedge clk) + OldFDivBusyE = FDivDoneE; + + // check results on falling edge of clk + always @(negedge clk) begin + + // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: + // - the sign of the NaN does not matter for the opperations being tested + // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter + if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) + case (FmtVal) + 4'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | + (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); + 4'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | + (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); + 4'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | + (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); + 4'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | + (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]}))); + endcase + else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + case (OpCtrlVal[1:0]) + 2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); + 2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); + 2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); + 2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); + endcase + else NaNGood = 1'b0; // integers can't be NaNs + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||||| ||||||| ||| |||||| + // ||| ||| ||| ||| ||| ||| ||| + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // check if result is correct + // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) + ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); + FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); + divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; + assign DivDone = OldFDivBusyE & ~FDivBusyE; + + //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL; + CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); + if(~(ResMatch & FlagMatch) & CheckNow) begin + errors += 1; + $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); + $display("Error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + + // TestFloat sets the result to all 1's when there is an invalid result, however in + // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says + // for an unsigned integer result 0 is also okay + + // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but + // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... + else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[`XLEN-1:0] === (`XLEN)'(0))) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | + (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + + // Add extra clock cycles in beginning for fdivsqrt to adequate reset state + if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin + repeat (12) + @(posedge clk); + if (reset != 1'b1) + VectorNum += 1; // increment the vector + end + + if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof + // increment the test + TestNum += 1; + // clear the vectors + for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}}; + // read next files + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + // set the vector index back to 0 + VectorNum = 0; + // incemet the operation if all the rounding modes have been tested + if(FrmNum === 4) OpCtrlNum += 1; + // increment the rounding mode or loop back to rne + if(FrmNum < 4) FrmNum += 1; + else FrmNum = 0; + + // if no more Tests - finish + if(Tests[TestNum] === "") begin + $display("\nAll Tests completed with %d errors\n", errors); + $stop; + end + + $display("Running %s vectors", Tests[TestNum]); + end + end endmodule module readvectors ( - input logic clk, - input logic [`FLEN*4+7:0] TestVector, - input logic [`FMTBITS-1:0] ModFmt, - input logic [1:0] Fmt, - input logic [2:0] Unit, - input logic [31:0] VectorNum, - input logic [31:0] TestNum, - input logic [2:0] OpCtrl, - output logic [`FLEN-1:0] Ans, - output logic [`XLEN-1:0] SrcA, - output logic [4:0] AnsFlg, - output logic Xs, Ys, Zs, // sign bits of XYZ - output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) - output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) - output logic XNaN, YNaN, ZNaN, // is XYZ a NaN - output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN - output logic XSubnorm, ZSubnorm, // is XYZ denormalized - output logic XZero, YZero, ZZero, // is XYZ zero - output logic XInf, YInf, ZInf, // is XYZ infinity - output logic XExpMax, - output logic DivStart, - output logic [`FLEN-1:0] X, Y, Z, XPostBox -); + input logic clk, + input logic [`FLEN*4+7:0] TestVector, + input logic [`FMTBITS-1:0] ModFmt, + input logic [1:0] Fmt, + input logic [2:0] Unit, + input logic [31:0] VectorNum, + input logic [31:0] TestNum, + input logic [2:0] OpCtrl, + output logic [`FLEN-1:0] Ans, + output logic [`XLEN-1:0] SrcA, + output logic [4:0] AnsFlg, + output logic Xs, Ys, Zs, // sign bits of XYZ + output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) + output logic XNaN, YNaN, ZNaN, // is XYZ a NaN + output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN + output logic XSubnorm, ZSubnorm, // is XYZ denormalized + output logic XZero, YZero, ZZero, // is XYZ zero + output logic XInf, YInf, ZInf, // is XYZ infinity + output logic XExpMax, + output logic DivStart, + output logic [`FLEN-1:0] X, Y, Z, XPostBox + ); + +`include "parameter-defs.vh" + localparam Q_LEN = 32'd128; - logic XEn, YEn, ZEn; + logic XEn, YEn, ZEn; - `include "parameter-defs.vh" - - // apply test vectors on rising edge of clk - // Format of vectors Inputs(1/2/3)_AnsFlg - always @(VectorNum) begin - #1; - AnsFlg = TestVector[4:0]; - DivStart = 1'b0; - case (Unit) - `FMAUNIT: - case (Fmt) - 2'b11: begin // quad - if(OpCtrl === `FMA_OPCTRL) begin - X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)]; - Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN]; - end - else begin - X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; - end - Ans = TestVector[8+(`Q_LEN-1):8]; - end - 2'b01: if (`D_SUPPORTED)begin // double - if(OpCtrl === `FMA_OPCTRL) begin - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; - Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]}; - end - else begin - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; - else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - end - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - end - 2'b00: if (`S_SUPPORTED)begin // single - if(OpCtrl === `FMA_OPCTRL) begin - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; - Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]}; - end - else begin - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; - else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; - else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; - end - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - end - 2'b10: begin // half - if(OpCtrl === `FMA_OPCTRL) begin - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; - Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]}; - end - else begin - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; - else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - end - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - end - endcase - `DIVUNIT: - if(OpCtrl[0]) + // apply test vectors on rising edge of clk + // Format of vectors Inputs(1/2/3)_AnsFlg + always @(VectorNum) begin + #1; + AnsFlg = TestVector[4:0]; + DivStart = 1'b0; + case (Unit) + `FMAUNIT: case (Fmt) 2'b11: begin // quad - X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; - Ans = TestVector[8+(`Q_LEN-1):8]; - if (~clk) #5; - DivStart = 1'b1; #10 // one clk cycle - DivStart = 1'b0; + if(OpCtrl === `FMA_OPCTRL) begin + X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)]; + Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN]; + end + else begin + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + end + Ans = TestVector[8+(`Q_LEN-1):8]; end 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; + if(OpCtrl === `FMA_OPCTRL) begin + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]}; + end + else begin + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; + else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + end + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; end 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; + if(OpCtrl === `FMA_OPCTRL) begin + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]}; + end + else begin + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; + else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + end + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; + if(OpCtrl === `FMA_OPCTRL) begin + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]}; + end + else begin + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; + else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + end + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; end endcase - else + `DIVUNIT: + if(OpCtrl[0]) + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + if (~clk) #5; + DivStart = 1'b1; #10 // one clk cycle + DivStart = 1'b0; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + endcase + else + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + if (~clk) #5; + DivStart = 1'b1; #10 // one clk cycle + DivStart = 1'b0; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + endcase + `CMPUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)]; + Y = TestVector[12+(`Q_LEN)-1:12]; + Ans = TestVector[8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]}; + Ans = TestVector[8]; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]}; + Ans = TestVector[8]; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+2*(`H_LEN)-1:12+(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]}; + Ans = TestVector[8]; + end + endcase + `CVTFPUNIT: case (Fmt) 2'b11: begin // quad - X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; - Ans = TestVector[8+(`Q_LEN-1):8]; - if (~clk) #5; - DivStart = 1'b1; #10 // one clk cycle - DivStart = 1'b0; + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase end 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase end 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - if (~clk) #5; - DivStart = 1'b1; #10 - DivStart = 1'b0; + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase end endcase - `CMPUNIT: - case (Fmt) - 2'b11: begin // quad - X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)]; - Y = TestVector[12+(`Q_LEN)-1:12]; - Ans = TestVector[8]; - end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]}; - Ans = TestVector[8]; - end - 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]}; - Ans = TestVector[8]; - end - 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+2*(`H_LEN)-1:12+(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]}; - Ans = TestVector[8]; - end - endcase - `CVTFPUNIT: - case (Fmt) - 2'b11: begin // quad - case (OpCtrl[1:0]) - 2'b11: begin // quad - X = {TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; - end - 2'b01: if (`D_SUPPORTED)begin // double - X = {TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - end - 2'b00: begin // single - X = {TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - end - 2'b10: begin // half - X = {TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - end - endcase - end - 2'b01: if (`D_SUPPORTED)begin // double - case (OpCtrl[1:0]) - 2'b11: begin // quad - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; - end - 2'b01: begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - end - 2'b00: begin // single - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - end - 2'b10: begin // half - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - end - endcase - end - 2'b00: if (`S_SUPPORTED)begin // single - case (OpCtrl[1:0]) - 2'b11: begin // quad - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; - end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - end - 2'b00: begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - end - 2'b10: begin // half - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - end - endcase - end - 2'b10: begin // half - case (OpCtrl[1:0]) - 2'b11: begin // quad - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; - end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - end - 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - end - 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - end - endcase - end - endcase - `CVTINTUNIT: - case (Fmt) - 2'b11: begin // quad - // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> quad - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]; - Ans = TestVector[8+(`Q_LEN-1):8]; - end - 2'b10: begin // int -> quad - // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+32-1]}}, TestVector[8+`Q_LEN+32-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; - end - 2'b01: begin // quad -> long - X = {TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; - end - 2'b00: begin // quad -> int - X = {TestVector[8+32+`Q_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; - end - endcase - end - 2'b01: if (`D_SUPPORTED)begin // double - // {Int->Fp?, is the integer a long} - casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> double - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - end - 2'b10: begin // int -> double - // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`D_LEN+32-1]}}, TestVector[8+`D_LEN+32-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; - end - 2'b01: begin // double -> long - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; - end - 2'b00: begin // double -> int - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+32+`D_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; - end - endcase - end - 2'b00: if (`S_SUPPORTED)begin // single - // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> single - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - end - 2'b10: begin // int -> single - // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`S_LEN+32-1]}}, TestVector[8+`S_LEN+32-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; - end - 2'b01: begin // single -> long - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; - end - 2'b00: begin // single -> int - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+32+`S_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; - end - endcase - end - 2'b10: begin // half - // {is the integer a long, is the opperation to an integer} - casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> half - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - end - 2'b10: begin // int -> half - // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`H_LEN+32-1]}}, TestVector[8+`H_LEN+32-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; - end - 2'b01: begin // half -> long - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; - end - 2'b00: begin // half -> int - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+32+`H_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; - end - endcase - end - endcase - endcase - end - - assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]); - assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0])); - assign ZEn = (Unit == `FMAUNIT); - - unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, - .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, - .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf, - .XEn, .YEn, .ZEn, .XExpMax, .XPostBox); + `CVTINTUNIT: + case (Fmt) + 2'b11: begin // quad + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> quad + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b10: begin // int -> quad + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+32-1]}}, TestVector[8+`Q_LEN+32-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // quad -> long + X = {TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // quad -> int + X = {TestVector[8+32+`Q_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end + endcase + end + 2'b01: if (`D_SUPPORTED)begin // double + // {Int->Fp?, is the integer a long} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> double + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b10: begin // int -> double + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`D_LEN+32-1]}}, TestVector[8+`D_LEN+32-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b01: begin // double -> long + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // double -> int + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+32+`D_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end + endcase + end + 2'b00: if (`S_SUPPORTED)begin // single + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> single + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // int -> single + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`S_LEN+32-1]}}, TestVector[8+`S_LEN+32-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b01: begin // single -> long + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // single -> int + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+32+`S_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end + endcase + end + 2'b10: begin // half + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> half + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + 2'b10: begin // int -> half + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`H_LEN+32-1]}}, TestVector[8+`H_LEN+32-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + 2'b01: begin // half -> long + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // half -> int + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+32+`H_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; + end + endcase + end + endcase + endcase + end + + assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]); + assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0])); + assign ZEn = (Unit == `FMAUNIT); + + unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, + .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, + .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf, + .XEn, .YEn, .ZEn, .XExpMax, .XPostBox); endmodule From 7e185a2f0dffbac436697675bce75383d482ee45 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 22 Jun 2023 09:13:22 -0700 Subject: [PATCH 13/54] fixed bug in testvector extract script -old script skips first 2 lines in rv32m case, new script only skips first line - prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer - prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file) --- .../extract_arch_vectors.py | 57 ++++++++++++++++--- 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/tests/fp/combined_IF_vectors/extract_arch_vectors.py b/tests/fp/combined_IF_vectors/extract_arch_vectors.py index 8d3945f14..12669bc58 100755 --- a/tests/fp/combined_IF_vectors/extract_arch_vectors.py +++ b/tests/fp/combined_IF_vectors/extract_arch_vectors.py @@ -1,7 +1,7 @@ #! /usr/bin/python3 -# author: Alessandro Maiuolo -# contact: amaiuolo@g.hmc.edu +# author: Alessandro Maiuolo, Kevin Kim +# contact: amaiuolo@g.hmc.edu, kekim@hmc.edu # date created: 3-29-2023 # extract all arch test vectors @@ -77,7 +77,7 @@ def create_vectors(my_config): rounding_mode = "X" flags = "XX" # use name to create our new tv - dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a') + dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'w') # open vectors src_file1 = open(source_dir1 + vector1,'r') src_file2 = open(source_dir2 + vector2,'r') @@ -144,7 +144,7 @@ def create_vectors(my_config): answer2 = src_file2.readline().strip() answer1 = src_file2.readline().strip() answer = answer1 + answer2 - # print(answer1,answer2) + #print(answer1,answer2) if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read # parse through .S file detected = False @@ -179,13 +179,56 @@ def create_vectors(my_config): else: # print("read false") reading = False + elif my_config.letter == "M" and my_config.bits == 32: + reading = True + while reading: + # print("trigger 64M") + # get answer from Ref...signature + # answers span two lines and are reversed + answer = src_file2.readline().strip() + print(f"Answer: {answer}") + #print(answer1,answer2) + if not (answer == "6f5ca309"): # if there is still stuff to read + # parse through .S file + detected = False + done = False + op1val = "0" + op2val = "0" + while not (detected or done): + # print("det1") + line = src_file1.readline() + # print(line) + if "op1val" in line: + # print("det2") + # parse line + op1val = line.split("op1val")[1].split("x")[1].split(";")[0] + if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling + op1val = twos_comp(my_config.bits, op1val) + if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later + op2val = line.split("op2val")[1].split("x")[1].strip() + if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there + if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling + op2val = twos_comp(my_config.bits, op2val) + # go to next test in vector + detected = True + elif "RVTEST_CODE_END" in line: + done = True + # ints don't have flags + flags = "XX" + # put it all together + if not done: + translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode) + dest_file.write(translation + "\n") + else: + # print("read false") + reading = False else: while reading: # get answer and flags from Ref...signature answer = src_file2.readline() - # print(answer) + print(answer) packed = src_file2.readline()[6:] - # print(packed) + print("Packed: ", packed) if len(packed.strip())>0: # if there is still stuff to read # print("packed") # parse through .S file @@ -229,7 +272,7 @@ def create_vectors(my_config): src_file2.close() config_list = [ -Config(32, "M", "div", "div_", 0), +Config(32, "M", "div", "div-", 0), Config(32, "F", "fdiv", "fdiv", 1), Config(32, "F", "fsqrt", "fsqrt", 2), Config(32, "M", "rem", "rem-", 3), From 4b3b590f214e8cc55fd9e56041218fd9f90bf1c4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 22 Jun 2023 12:55:49 -0500 Subject: [PATCH 14/54] Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits. --- .gitignore | 52 ++++++++ config/fpga/config.vh | 174 +++++++++++++++++++++++++++ fpga/constraints/small-debug.xdc | 14 +-- fpga/constraints/vcu-small-debug.xdc | 52 ++++++++ 4 files changed, 285 insertions(+), 7 deletions(-) create mode 100644 config/fpga/config.vh create mode 100644 fpga/constraints/vcu-small-debug.xdc diff --git a/.gitignore b/.gitignore index 6f529d883..41ccba5f9 100644 --- a/.gitignore +++ b/.gitignore @@ -119,3 +119,55 @@ tests/coverage/*.elf sim/*Cache.log sim/branch tests/fp/combined_IF_vectors/IF_vectors/*.tv +/sim/branch-march14.tar.gz +/sim/gshareforward-no-class +/sim/lint-wally_32 +/sim/lint-wally_32e +/sim/local16.txt +/sim/localhistory_m6k10_results_april24.txt +/sim/log.log +/sim/obj_dir/Vtestbench.cpp +/sim/obj_dir/Vtestbench.h +/sim/obj_dir/Vtestbench.mk +/sim/obj_dir/Vtestbench__ConstPool_0.cpp +/sim/obj_dir/Vtestbench__Syms.cpp +/sim/obj_dir/Vtestbench__Syms.h +/sim/obj_dir/Vtestbench___024root.h +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp +/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp +/sim/obj_dir/Vtestbench___024root__Slow.cpp +/sim/obj_dir/Vtestbench___024unit.h +/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp +/sim/obj_dir/Vtestbench___024unit__Slow.cpp +/sim/obj_dir/Vtestbench__verFiles.dat +/sim/obj_dir/Vtestbench_classes.mk +/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h +/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp +/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp +/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp +/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp +/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp +/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp +/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h +/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp +/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp +/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp +/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp diff --git a/config/fpga/config.vh b/config/fpga/config.vh new file mode 100644 index 000000000..25fbaae13 --- /dev/null +++ b/config/fpga/config.vh @@ -0,0 +1,174 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// include shared configuration +`include "BranchPredictorType.vh" + +localparam FPGA = 1; +localparam QEMU = 0; + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd64; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +// MISA RISC-V configuration per specification +localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 0; +localparam ZICBOM_SUPPORTED = 0; +localparam ZICBOZ_SUPPORTED = 0; +localparam ZICBOP_SUPPORTED = 0; +localparam SVPBMT_SUPPORTED = 0; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 1; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h0000000000001000; + +// Bus Interface width +localparam AHBW = 32'd64; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Physical Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h00001FFF; + +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h00001FFF; + +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; + +localparam UNCORE_RAM_SUPPORTED = 1'b0; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; + +localparam EXT_MEM_SUPPORTED = 1'b1; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; + +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; + +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; + +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; + +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; + +localparam SDC_SUPPORTED = 1'b1; +localparam logic [63:0] SDC_BASE = 64'h00012100; +localparam logic [63:0] SDC_RANGE = 64'h0000001F; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 0; + +// Hardware configuration +localparam UART_PRESCALE = 32'd0; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd53; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; + +localparam BPRED_SUPPORTED = 1; +localparam BranchPredictorType BPRED_TYPE = BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_NUM_LHR = 32'd6; +localparam BPRED_SIZE = 32'd12; +localparam BTB_SIZE = 32'd10; + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'h4; +localparam DIVCOPIES = 32'h4; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "test-shared.vh" diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc index b50777f0d..2938c3ec0 100644 --- a/fpga/constraints/small-debug.xdc +++ b/fpga/constraints/small-debug.xdc @@ -21,32 +21,32 @@ connect_debug_port u_ila_0/clk [get_nets CPUCLK] set_property port_width 64 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe1] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe2] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe3] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe4] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe5] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]] +connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]] create_debug_port u_ila_0 probe set_property port_width 28 [get_debug_ports u_ila_0/probe6] @@ -131,7 +131,7 @@ connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe22] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] diff --git a/fpga/constraints/vcu-small-debug.xdc b/fpga/constraints/vcu-small-debug.xdc new file mode 100644 index 000000000..62fea508f --- /dev/null +++ b/fpga/constraints/vcu-small-debug.xdc @@ -0,0 +1,52 @@ +create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]] + +set_property port_width 64 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] + From 6d5d95b0f3b57cabd62c35f7cc24411886253bb3 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 22 Jun 2023 15:25:56 -0500 Subject: [PATCH 15/54] Remove path for cvw.sv so its found --- sim/testfloat.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/testfloat.do b/sim/testfloat.do index ffa03dc8d..85bd6dfc5 100644 --- a/sim/testfloat.do +++ b/sim/testfloat.do @@ -25,7 +25,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/$1 +incdir+../config/shared ../src/wally/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 # Change TEST_SIZE to only test certain FP width # values are QP, DP, SP, HP From 8f7ba2b8d2a6ef78d328580e4f0eada1395f3826 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 22 Jun 2023 15:26:22 -0500 Subject: [PATCH 16/54] For some reason this was modified - I probably made a mistake - put back vsim --- sim/sim-testfloat-batch | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/sim-testfloat-batch b/sim/sim-testfloat-batch index 31ff21a6c..073553e52 100755 --- a/sim/sim-testfloat-batch +++ b/sim/sim-testfloat-batch @@ -10,3 +10,4 @@ # sqrt - test square root # all - test everything +vsim -c -do "do testfloat.do rv64fpquad $1" \ No newline at end of file From e913c1ea464e396f54cad2ec3e1737055c6d52cd Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 22 Jun 2023 15:27:17 -0500 Subject: [PATCH 17/54] Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works --- testbench/testbench-fp.sv | 553 +++++++++++++++++++------------------- 1 file changed, 277 insertions(+), 276 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 413dc11e5..985561e3d 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -1,9 +1,6 @@ /////////////////////////////////////////// // // Written: me@KatherineParry.com, james.stine@okstate.edu -// Modified: 7/5/2022 -// Modified: 4/2/2023 -// Modified: 6/19/2023 // // Purpose: Testbench for Testfloat // @@ -24,7 +21,7 @@ // either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" +//`include "wally-config.vh" `include "config.vh" `include "tests-fp.vh" @@ -32,7 +29,9 @@ import cvw::*; module testbenchfp; parameter TEST="none"; - parameter TEST_SIZE="none"; + parameter TEST_SIZE="none"; + + `include "parameter-defs.vh" string Tests[]; // list of tests to be run logic [2:0] OpCtrl[]; // list of op controls @@ -47,53 +46,53 @@ module testbenchfp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal logic WriteIntVal; // value of the current WriteInt - logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat - logic [`FLEN-1:0] XPostBox; // inputs read from TestFloat - logic [`XLEN-1:0] SrcA; // integer input - logic [`FLEN-1:0] Ans; // correct answer from TestFloat - logic [`FLEN-1:0] Res; // result from other units + logic [P.FLEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [P.FLEN-1:0] XPostBox; // inputs read from TestFloat + logic [P.XLEN-1:0] SrcA; // integer input + logic [P.FLEN-1:0] Ans; // correct answer from TestFloat + logic [P.FLEN-1:0] Res; // result from other units logic [4:0] AnsFlg; // correct flags read from testfloat logic [4:0] ResFlg, Flg; // Result flags - logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad - logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit - logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit + logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad + logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit + logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags logic AnsNaN, ResNaN, NaNGood; logic Xs, Ys, Zs; // sign of the inputs - logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs - logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs + logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs + logic [P.NF:0] Xm, Ym, Zm; // mantissas of the inputs logic XNaN, YNaN, ZNaN; // is the input NaN logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN logic XSubnorm, ZSubnorm; // is the input denormalized logic XInf, YInf, ZInf; // is the input infinity logic XZero, YZero, ZZero; // is the input zero logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones - logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) + logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) logic IntZero; logic CvtResSgnE; - logic [`NE:0] CvtCalcExpE; // the calculated expoent - logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by - logic [`DIVb:0] Quot; + logic [P.NE:0] CvtCalcExpE; // the calculated expoent + logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by + logic [P.DIVb:0] Quot; logic CvtResSubnormUfE; logic DivStart, FDivBusyE, OldFDivBusyE; logic reset = 1'b0; - logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; - logic [`DURLEN-1:0] Dur; + logic [$clog2(P.NF+2)-1:0] XZeroCnt, YZeroCnt; + logic [P.DURLEN-1:0] Dur; // in-between FMA signals logic Mult; logic Ss; - logic [`NE+1:0] Pe; - logic [`NE+1:0] Se; + logic [P.NE+1:0] Pe; + logic [P.NE+1:0] Se; logic ASticky; logic KillProd; - logic [$clog2(3*`NF+5)-1:0] SCnt; - logic [3*`NF+3:0] Sm; + logic [$clog2(3*P.NF+5)-1:0] SCnt; + logic [3*P.NF+3:0] Sm; logic InvA; logic NegSum; logic As; @@ -101,7 +100,7 @@ module testbenchfp; logic DivSticky; logic DivDone; logic DivNegSticky; - logic [`NE+1:0] DivCalcExp; + logic [P.NE+1:0] DivCalcExp; logic divsqrtop; // Missing logic vectors fdivsqrt @@ -109,11 +108,9 @@ module testbenchfp; logic [2:0] Funct3M; logic FlushE; logic IFDivStartE, FDivDoneE; - logic [`NE+1:0] QeM; - logic [`DIVb:0] QmM; - logic [`XLEN-1:0] FIntDivResultM; - - `include "parameter-defs.vh" + logic [P.NE+1:0] QeM; + logic [P.DIVb:0] QmM; + logic [P.XLEN-1:0] FIntDivResultM; /////////////////////////////////////////////////////////////////////////////////////////////// @@ -139,7 +136,7 @@ module testbenchfp; $display("\nThe start of simulation..."); $display("This simulation for TEST is %s", TEST); $display("This simulation for TEST is of the operand size of %s", TEST_SIZE); - if (`Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported + if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion // add the 128-bit cvtint tests to the to-be-tested list Tests = {Tests, f128rv32cvtint}; @@ -151,7 +148,7 @@ module testbenchfp; Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b11}; end - if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions + if (P.XLEN == 64) begin // if 64-bit integers are supported add their conversions Tests = {Tests, f128rv64cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; @@ -165,7 +162,7 @@ module testbenchfp; end // if the floating-point conversions are being tested if (TEST === "cvtfp" | TEST === "all") begin - if(`D_SUPPORTED) begin // if double precision is supported + if(P.D_SUPPORTED) begin // if double precision is supported // add the 128 <-> 64 bit conversions to the to-be-tested list Tests = {Tests, f128f64cvt}; // add the op-ctrls (i.e. the format of the result) @@ -181,7 +178,7 @@ module testbenchfp; Fmt = {Fmt, 2'b01}; end end - if(`F_SUPPORTED) begin // if single precision is supported + if(P.F_SUPPORTED) begin // if single precision is supported // add the 128 <-> 32 bit conversions to the to-be-tested list Tests = {Tests, f128f32cvt}; // add the op-ctrls (i.e. the format of the result) @@ -197,7 +194,7 @@ module testbenchfp; Fmt = {Fmt, 2'b00}; end end - if(`ZFH_SUPPORTED) begin // if half precision is supported + if(P.ZFH_SUPPORTED) begin // if half precision is supported // add the 128 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f128f16cvt}; // add the op-ctrls (i.e. the format of the result) @@ -284,7 +281,7 @@ module testbenchfp; end end end - if (`D_SUPPORTED & (TEST_SIZE == "DP" | TEST_SIZE == "all")) begin // if double precision is supported + if (P.D_SUPPORTED & (TEST_SIZE == "DP" | TEST_SIZE == "all")) begin // if double precision is supported if (TEST === "cvtint" | TEST === "all") begin // if integer conversion is being tested Tests = {Tests, f64rv32cvtint}; // add the op-codes for these tests to the op-code list @@ -295,7 +292,7 @@ module testbenchfp; Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b01}; end - if (`XLEN == 64) begin // if 64-bit integers are being supported + if (P.XLEN == 64) begin // if 64-bit integers are being supported Tests = {Tests, f64rv64cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; @@ -308,7 +305,7 @@ module testbenchfp; end end if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested - if(`F_SUPPORTED) begin // if single precision is supported + if(P.F_SUPPORTED) begin // if single precision is supported // add the 64 <-> 32 bit conversions to the to-be-tested list Tests = {Tests, f64f32cvt}; // add the op-ctrls (i.e. the format of the result) @@ -324,7 +321,7 @@ module testbenchfp; Fmt = {Fmt, 2'b00}; end end - if(`ZFH_SUPPORTED) begin // if half precision is supported + if(P.ZFH_SUPPORTED) begin // if half precision is supported // add the 64 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f64f16cvt}; // add the op-ctrls (i.e. the format of the result) @@ -411,7 +408,7 @@ module testbenchfp; end end end - if (`F_SUPPORTED & (TEST_SIZE == "SP" | TEST_SIZE == "all")) begin // if single precision being supported + if (P.F_SUPPORTED & (TEST_SIZE == "SP" | TEST_SIZE == "all")) begin // if single precision being supported if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested Tests = {Tests, f32rv32cvtint}; // add the op-codes for these tests to the op-code list @@ -422,7 +419,7 @@ module testbenchfp; Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b00}; end - if (`XLEN == 64) begin // if 64-bit integers are supported + if (P.XLEN == 64) begin // if 64-bit integers are supported Tests = {Tests, f32rv64cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; @@ -435,7 +432,7 @@ module testbenchfp; end end if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested - if(`ZFH_SUPPORTED) begin + if(P.ZFH_SUPPORTED) begin // add the 32 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f32f16cvt}; // add the op-ctrls (i.e. the format of the result) @@ -522,7 +519,7 @@ module testbenchfp; end end end - if (`ZFH_SUPPORTED & (TEST_SIZE == "HP" | TEST_SIZE == "all")) begin // if half precision supported + if (P.ZFH_SUPPORTED & (TEST_SIZE == "HP" | TEST_SIZE == "all")) begin // if half precision supported if (TEST === "cvtint" | TEST === "all") begin // if in conversions are being tested Tests = {Tests, f16rv32cvtint}; // add the op-codes for these tests to the op-code list @@ -533,7 +530,7 @@ module testbenchfp; Unit = {Unit, `CVTINTUNIT}; Fmt = {Fmt, 2'b10}; end - if (`XLEN == 64) begin // if 64-bit integers are supported + if (P.XLEN == 64) begin // if 64-bit integers are supported Tests = {Tests, f16rv64cvtint}; // add the op-codes for these tests to the op-code list OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; @@ -641,7 +638,7 @@ module testbenchfp; string tt0; tt0 = $psprintf("%s", Tests[TestNum]); testname = {p, tt0}; - // $display("Here you are %s", testname); + //$display("Here you are %s", testname); $display("\n\nRunning %s vectors ", Tests[TestNum]); $readmemh(testname, TestVectors); // set the test index to 0 @@ -659,7 +656,7 @@ module testbenchfp; // - 1 for the larger precision // - 0 for the smaller precision always_comb begin - if(`FMTBITS == 1) ModFmt = FmtVal == `FMT; + if(P.FMTBITS == 1) ModFmt = FmtVal == P.FMT; else ModFmt = FmtVal; end @@ -770,40 +767,40 @@ module testbenchfp; else if (UnitVal === `CVTFPUNIT) begin case (OpCtrlVal[1:0]) 4'b11: begin // quad - AnsNaN = &Ans[`Q_LEN-2:`NF]&(|Ans[`Q_NF-1:0]); - ResNaN = &Res[`Q_LEN-2:`NF]&(|Res[`Q_NF-1:0]); + AnsNaN = &Ans[P.Q_LEN-2:P.NF]&(|Ans[P.Q_NF-1:0]); + ResNaN = &Res[P.Q_LEN-2:P.NF]&(|Res[P.Q_NF-1:0]); end 4'b01: begin // double - AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); - ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); + AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]); + ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]); end 4'b00: begin // single - AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); - ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); + AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]); + ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]); end 4'b10: begin // half - AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); - ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); + AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]); + ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]); end endcase end else begin case (FmtVal) 4'b11: begin // quad - AnsNaN = &Ans[`Q_LEN-2:`Q_NF]&(|Ans[`Q_NF-1:0]); - ResNaN = &Res[`Q_LEN-2:`Q_NF]&(|Res[`Q_NF-1:0]); + AnsNaN = &Ans[P.Q_LEN-2:P.Q_NF]&(|Ans[P.Q_NF-1:0]); + ResNaN = &Res[P.Q_LEN-2:P.Q_NF]&(|Res[P.Q_NF-1:0]); end 4'b01: begin // double - AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); - ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); + AnsNaN = &Ans[P.D_LEN-2:P.D_NF]&(|Ans[P.D_NF-1:0]); + ResNaN = &Res[P.D_LEN-2:P.D_NF]&(|Res[P.D_NF-1:0]); end 4'b00: begin // single - AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); - ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); + AnsNaN = &Ans[P.S_LEN-2:P.S_NF]&(|Ans[P.S_NF-1:0]); + ResNaN = &Res[P.S_LEN-2:P.S_NF]&(|Res[P.S_NF-1:0]); end 4'b10: begin // half - AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); - ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); + AnsNaN = &Ans[P.H_LEN-2:P.H_NF]&(|Ans[P.H_NF-1:0]); + ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]); end endcase end @@ -841,49 +838,49 @@ module testbenchfp; // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) case (FmtVal) - 4'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | - (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | - (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); - 4'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | - (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | - (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); - 4'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | - (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | - (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); - 4'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | - (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | - (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]}))); + 4'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | + (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | + (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]})) | + (ZNaN&(Res[P.Q_LEN-2:0] === {Z[P.Q_LEN-2:P.Q_NF],1'b1,Z[P.Q_NF-2:0]}))); + 4'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | + (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) | + (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]})) | + (ZNaN&(Res[P.D_LEN-2:0] === {Z[P.D_LEN-2:P.D_NF],1'b1,Z[P.D_NF-2:0]}))); + 4'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | + (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) | + (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]})) | + (ZNaN&(Res[P.S_LEN-2:0] === {Z[P.S_LEN-2:P.S_NF],1'b1,Z[P.S_NF-2:0]}))); + 4'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | + (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | + (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) | + (ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]}))); endcase else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format case (OpCtrlVal[1:0]) - 2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | - (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | - (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | - (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); - 2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | - (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | - (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | - (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); - 2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | - (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | - (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | - (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); - 2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | - (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | - (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | - (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); + 2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) | + (AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) | + (XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) | + (YNaN&(Res[P.Q_LEN-2:0] === {Y[P.Q_LEN-2:P.Q_NF],1'b1,Y[P.Q_NF-2:0]}))); + 2'b01: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.D_LEN-1:0] === {1'b0, {P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.D_LEN-2:0] === {{P.D_NE+1{1'b1}}, {P.D_NF-1{1'b0}}})) | + (AnsNaN&(Res[P.D_LEN-2:0] === Ans[P.D_LEN-2:0])) | + (XNaN&(Res[P.D_LEN-2:0] === {X[P.D_LEN-2:P.D_NF],1'b1,X[P.D_NF-2:0]})) | + (YNaN&(Res[P.D_LEN-2:0] === {Y[P.D_LEN-2:P.D_NF],1'b1,Y[P.D_NF-2:0]}))); + 2'b00: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.S_LEN-1:0] === {1'b0, {P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.S_LEN-2:0] === {{P.S_NE+1{1'b1}}, {P.S_NF-1{1'b0}}})) | + (AnsNaN&(Res[P.S_LEN-2:0] === Ans[P.S_LEN-2:0])) | + (XNaN&(Res[P.S_LEN-2:0] === {X[P.S_LEN-2:P.S_NF],1'b1,X[P.S_NF-2:0]})) | + (YNaN&(Res[P.S_LEN-2:0] === {Y[P.S_LEN-2:P.S_NF],1'b1,Y[P.S_NF-2:0]}))); + 2'b10: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res[P.H_LEN-1:0] === {1'b0, {P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[P.H_LEN-2:0] === {{P.H_NE+1{1'b1}}, {P.H_NF-1{1'b0}}})) | + (AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) | + (XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) | + (YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]}))); endcase else NaNGood = 1'b0; // integers can't be NaNs @@ -921,9 +918,9 @@ module testbenchfp; // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... - else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[`XLEN-1:0] === (`XLEN)'(0))) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | + else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); @@ -943,7 +940,7 @@ module testbenchfp; // increment the test TestNum += 1; // clear the vectors - for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}}; + for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; // read next files $readmemh({`PATH, Tests[TestNum]}, TestVectors); // set the vector index back to 0 @@ -968,19 +965,19 @@ endmodule module readvectors ( input logic clk, - input logic [`FLEN*4+7:0] TestVector, - input logic [`FMTBITS-1:0] ModFmt, + input logic [P.FLEN*4+7:0] TestVector, + input logic [P.FMTBITS-1:0] ModFmt, input logic [1:0] Fmt, input logic [2:0] Unit, input logic [31:0] VectorNum, input logic [31:0] TestNum, input logic [2:0] OpCtrl, - output logic [`FLEN-1:0] Ans, - output logic [`XLEN-1:0] SrcA, + output logic [P.FLEN-1:0] Ans, + output logic [P.XLEN-1:0] SrcA, output logic [4:0] AnsFlg, output logic Xs, Ys, Zs, // sign bits of XYZ - output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) - output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) + output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) + output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) output logic XNaN, YNaN, ZNaN, // is XYZ a NaN output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN output logic XSubnorm, ZSubnorm, // is XYZ denormalized @@ -988,13 +985,15 @@ module readvectors ( output logic XInf, YInf, ZInf, // is XYZ infinity output logic XExpMax, output logic DivStart, - output logic [`FLEN-1:0] X, Y, Z, XPostBox + output logic [P.FLEN-1:0] X, Y, Z, XPostBox ); -`include "parameter-defs.vh" - localparam Q_LEN = 32'd128; + localparam Q_LEN = 32'd128; + `include "parameter-defs.vh" logic XEn, YEn, ZEn; + logic FPUActive; + // apply test vectors on rising edge of clk // Format of vectors Inputs(1/2/3)_AnsFlg @@ -1007,90 +1006,90 @@ module readvectors ( case (Fmt) 2'b11: begin // quad if(OpCtrl === `FMA_OPCTRL) begin - X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)]; - Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN]; + X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)]; + Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; + Z = TestVector[8+2*(P.Q_LEN)-1:8+P.Q_LEN]; end else begin - X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; + if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; end - Ans = TestVector[8+(`Q_LEN-1):8]; + Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (`D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED)begin // double if(OpCtrl === `FMA_OPCTRL) begin - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; - Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]}; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]}; + Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; + Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]}; end else begin - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; - else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; + else Y = {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}}; + else Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; end - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (`S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED)begin // single if(OpCtrl === `FMA_OPCTRL) begin - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; - Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]}; + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]}; + Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; + Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]}; end else begin - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; - else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; - else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; + else Y = {{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}}; + else Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; end - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // half if(OpCtrl === `FMA_OPCTRL) begin - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; - Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]}; + Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; + Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]}; end else begin - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; - else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; + else Y = {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}}; + else Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; end - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase `DIVUNIT: if(OpCtrl[0]) case (Fmt) 2'b11: begin // quad - X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; + Ans = TestVector[8+(P.Q_LEN-1):8]; if (~clk) #5; DivStart = 1'b1; #10 // one clk cycle DivStart = 1'b0; end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + 2'b01: if (P.D_SUPPORTED)begin // double + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; end - 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + 2'b00: if (P.S_SUPPORTED)begin // single + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; @@ -1099,33 +1098,33 @@ module readvectors ( else case (Fmt) 2'b11: begin // quad - X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; + Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; + Ans = TestVector[8+(P.Q_LEN-1):8]; if (~clk) #5; DivStart = 1'b1; #10 // one clk cycle DivStart = 1'b0; end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + 2'b01: if (P.D_SUPPORTED)begin // double + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; + Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; end - 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + 2'b00: if (P.S_SUPPORTED)begin // single + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; + Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; + Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; @@ -1134,23 +1133,23 @@ module readvectors ( `CMPUNIT: case (Fmt) 2'b11: begin // quad - X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)]; - Y = TestVector[12+(`Q_LEN)-1:12]; + X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)]; + Y = TestVector[12+(P.Q_LEN)-1:12]; Ans = TestVector[8]; end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]}; - Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]}; + 2'b01: if (P.D_SUPPORTED)begin // double + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]}; + Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]}; Ans = TestVector[8]; end - 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]}; - Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]}; + 2'b00: if (P.S_SUPPORTED)begin // single + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]}; + Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]}; Ans = TestVector[8]; end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+2*(`H_LEN)-1:12+(`H_LEN)]}; - Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]}; + Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]}; Ans = TestVector[8]; end endcase @@ -1159,80 +1158,80 @@ module readvectors ( 2'b11: begin // quad case (OpCtrl[1:0]) 2'b11: begin // quad - X = {TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = {TestVector[8+P.Q_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; + Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (`D_SUPPORTED)begin // double - X = {TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + 2'b01: if (P.D_SUPPORTED)begin // double + X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b00: begin // single - X = {TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // half - X = {TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end - 2'b01: if (`D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED)begin // double case (OpCtrl[1:0]) 2'b11: begin // quad - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; + Ans = TestVector[8+(P.Q_LEN-1):8]; end 2'b01: begin // double - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b00: begin // single - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // half - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end - 2'b00: if (`S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED)begin // single case (OpCtrl[1:0]) 2'b11: begin // quad - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; + Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + 2'b01: if (P.D_SUPPORTED)begin // double + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b00: begin // single - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // half - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end 2'b10: begin // half case (OpCtrl[1:0]) 2'b11: begin // quad - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; + Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (`D_SUPPORTED)begin // double - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + 2'b01: if (P.D_SUPPORTED)begin // double + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (`S_SUPPORTED)begin // single - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + 2'b00: if (P.S_SUPPORTED)begin // single + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // half - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end @@ -1244,77 +1243,77 @@ module readvectors ( // {is the integer a long, is the opperation to an integer} casex ({OpCtrl[2:1]}) 2'b11: begin // long -> quad - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = {P.FLEN{1'bx}}; + SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; + Ans = TestVector[8+(P.Q_LEN-1):8]; end 2'b10: begin // int -> quad // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+32-1]}}, TestVector[8+`Q_LEN+32-1:8+(`Q_LEN)]}; - Ans = TestVector[8+(`Q_LEN-1):8]; + X = {P.FLEN{1'bx}}; + SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]}; + Ans = TestVector[8+(P.Q_LEN-1):8]; end 2'b01: begin // quad -> long - X = {TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; + X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // quad -> int - X = {TestVector[8+32+`Q_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end - 2'b01: if (`D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double // {Int->Fp?, is the integer a long} casex ({OpCtrl[2:1]}) 2'b11: begin // long -> double - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + X = {P.FLEN{1'bx}}; + SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b10: begin // int -> double // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`D_LEN+32-1]}}, TestVector[8+`D_LEN+32-1:8+(`D_LEN)]}; - Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + X = {P.FLEN{1'bx}}; + SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]}; + Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b01: begin // double -> long - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // double -> int - X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+32+`D_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end - 2'b00: if (`S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED)begin // single // {is the integer a long, is the opperation to an integer} casex ({OpCtrl[2:1]}) 2'b11: begin // long -> single - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + X = {P.FLEN{1'bx}}; + SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // int -> single // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`S_LEN+32-1]}}, TestVector[8+`S_LEN+32-1:8+(`S_LEN)]}; - Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + X = {P.FLEN{1'bx}}; + SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]}; + Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b01: begin // single -> long - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // single -> int - X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+32+`S_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end @@ -1322,25 +1321,25 @@ module readvectors ( // {is the integer a long, is the opperation to an integer} casex ({OpCtrl[2:1]}) 2'b11: begin // long -> half - X = {`FLEN{1'bx}}; - SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {P.FLEN{1'bx}}; + SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)]; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end 2'b10: begin // int -> half // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {`FLEN{1'bx}}; - SrcA = {{`XLEN-32{TestVector[8+`H_LEN+32-1]}}, TestVector[8+`H_LEN+32-1:8+(`H_LEN)]}; - Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + X = {P.FLEN{1'bx}}; + SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]}; + Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end 2'b01: begin // half -> long - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {TestVector[8+(`XLEN-1):8]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // half -> int - X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+32+`H_LEN-1:8+(32)]}; - SrcA = {`XLEN{1'bx}}; - Ans = {{`XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; + X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; + SrcA = {P.XLEN{1'bx}}; + Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; end endcase end @@ -1351,8 +1350,10 @@ module readvectors ( assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]); assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0])); assign ZEn = (Unit == `FMAUNIT); + // Will fix with better activation - for now, this works (jes) + assign FPUActive = 1'b1; - unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, + unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .FPUActive, .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf, .XEn, .YEn, .ZEn, .XExpMax, .XPostBox); From 83a79b3a40d13d0396f342c37f071a952d8964ba Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 26 Jun 2023 10:14:49 -0500 Subject: [PATCH 18/54] Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly --- testbench/testbench-fp.sv | 97 ++++++++++++++++++++++----------------- 1 file changed, 54 insertions(+), 43 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 985561e3d..207282157 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -46,7 +46,7 @@ module testbenchfp; logic [31:0] errors=0; // how many errors logic [31:0] VectorNum=0; // index for test vector logic [31:0] FrmNum=0; // index for rounding mode - logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors + logic [P.FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors logic [1:0] FmtVal; // value of the current Fmt logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal @@ -75,14 +75,16 @@ module testbenchfp; logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) logic IntZero; logic CvtResSgnE; - logic [P.NE:0] CvtCalcExpE; // the calculated expoent + logic [P.NE:0] CvtCalcExpE; // the calculated exponent logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [P.DIVb:0] Quot; logic CvtResSubnormUfE; - logic DivStart, FDivBusyE, OldFDivBusyE; + logic DivStart; + logic FDivBusyE; + logic OldFDivBusyE; logic reset = 1'b0; logic [$clog2(P.NF+2)-1:0] XZeroCnt, YZeroCnt; - logic [P.DURLEN-1:0] Dur; + logic [P.DURLEN-1:0] Dur; // in-between FMA signals logic Mult; @@ -91,7 +93,7 @@ module testbenchfp; logic [P.NE+1:0] Se; logic ASticky; logic KillProd; - logic [$clog2(3*P.NF+5)-1:0] SCnt; + logic [$clog2(3*P.NF+5)-1:0] SCnt; logic [3*P.NF+3:0] Sm; logic InvA; logic NegSum; @@ -107,10 +109,14 @@ module testbenchfp; logic [2:0] Funct3E; logic [2:0] Funct3M; logic FlushE; - logic IFDivStartE, FDivDoneE; + logic IFDivStartE; + logic FDivDoneE; logic [P.NE+1:0] QeM; logic [P.DIVb:0] QmM; logic [P.XLEN-1:0] FIntDivResultM; + logic ResMatch; // Check if result matches + logic FlagMatch; // Check if flag matches + logic CheckNow; // Final check /////////////////////////////////////////////////////////////////////////////////////////////// @@ -804,7 +810,8 @@ module testbenchfp; end endcase end - end + end + always_comb begin // select the result to check case (UnitVal) @@ -825,11 +832,22 @@ module testbenchfp; endcase end - logic ResMatch, FlagMatch, CheckNow; - always @(posedge clk) OldFDivBusyE = FDivDoneE; + // For FP division this adds extra clock cycles to make sure the + // computation completes. 18 clocks cycles are utilize to handle + // Quad, but this can be changed for each precision to go faster. + always @(posedge clk) begin + // Add extra clock cycles in beginning for fdivsqrt to adequate reset state + if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin + repeat (18) + @(posedge clk); + if (reset != 1'b1) + VectorNum += 1; // increment the vector + end + end + // check results on falling edge of clk always @(negedge clk) begin @@ -896,15 +914,14 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// // check if result is correct - // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) - ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); - FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); - divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; + // wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) + assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); + assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); + assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign DivDone = OldFDivBusyE & ~FDivBusyE; - //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL; - CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); - if(~(ResMatch & FlagMatch) & CheckNow) begin + assign CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); + if (~(ResMatch & FlagMatch) & CheckNow) begin errors += 1; $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("Error in %s", Tests[TestNum]); @@ -928,14 +945,6 @@ module testbenchfp; $stop; end - // Add extra clock cycles in beginning for fdivsqrt to adequate reset state - if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin - repeat (12) - @(posedge clk); - if (reset != 1'b1) - VectorNum += 1; // increment the vector - end - if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof // increment the test TestNum += 1; @@ -964,41 +973,43 @@ endmodule module readvectors ( - input logic clk, + input logic clk, input logic [P.FLEN*4+7:0] TestVector, input logic [P.FMTBITS-1:0] ModFmt, - input logic [1:0] Fmt, - input logic [2:0] Unit, - input logic [31:0] VectorNum, - input logic [31:0] TestNum, - input logic [2:0] OpCtrl, + input logic [1:0] Fmt, + input logic [2:0] Unit, + input logic [31:0] VectorNum, + input logic [31:0] TestNum, + input logic [2:0] OpCtrl, output logic [P.FLEN-1:0] Ans, output logic [P.XLEN-1:0] SrcA, - output logic [4:0] AnsFlg, - output logic Xs, Ys, Zs, // sign bits of XYZ + output logic [4:0] AnsFlg, + output logic Xs, Ys, Zs, // sign bits of XYZ output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) - output logic XNaN, YNaN, ZNaN, // is XYZ a NaN - output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN - output logic XSubnorm, ZSubnorm, // is XYZ denormalized - output logic XZero, YZero, ZZero, // is XYZ zero - output logic XInf, YInf, ZInf, // is XYZ infinity - output logic XExpMax, - output logic DivStart, + output logic XNaN, YNaN, ZNaN, // is XYZ a NaN + output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN + output logic XSubnorm, ZSubnorm, // is XYZ denormalized + output logic XZero, YZero, ZZero, // is XYZ zero + output logic XInf, YInf, ZInf, // is XYZ infinity + output logic XExpMax, + output logic DivStart, output logic [P.FLEN-1:0] X, Y, Z, XPostBox ); localparam Q_LEN = 32'd128; `include "parameter-defs.vh" - logic XEn, YEn, ZEn; - logic FPUActive; - + logic XEn, YEn, ZEn; + logic FPUActive; // apply test vectors on rising edge of clk // Format of vectors Inputs(1/2/3)_AnsFlg always @(VectorNum) begin - #1; + // Initial delay is given to allow vector to work for fdiv + // otherwise it will fail on first vector - fix needed (jes) + DivStart = 1'b0; + #20; AnsFlg = TestVector[4:0]; DivStart = 1'b0; case (Unit) From a0c9ef03ff30e8d0622ce5033b8b2529a6057eac Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 26 Jun 2023 10:15:46 -0500 Subject: [PATCH 19/54] Add signals for ResMatch & CheckNow to sim window that are related to TestFloat operation --- sim/wave-fpu.do | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sim/wave-fpu.do b/sim/wave-fpu.do index 05ccb2154..a1cfa8731 100644 --- a/sim/wave-fpu.do +++ b/sim/wave-fpu.do @@ -9,6 +9,12 @@ add wave -noupdate /testbenchfp/Res add wave -noupdate /testbenchfp/Ans add wave -noupdate /testbenchfp/DivStart add wave -noupdate /testbenchfp/FDivBusyE +add wave -noupdate /testbenchfp/CheckNow +add wave -noupdate /testbenchfp/DivDone +add wave -noupdate /testbenchfp/ResMatch +add wave -noupdate /testbenchfp/FlagMatch +add wave -noupdate /testbenchfp/CheckNow +add wave -noupdate /testbenchfp/NaNGood add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/* From 012316aa94676ef3db786674ee7774f78a477225 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Mon, 26 Jun 2023 14:25:44 -0500 Subject: [PATCH 20/54] Minor tweak to fix vectors not working for fadd. --- testbench/testbench-fp.sv | 255 +++++++++++++++++++++----------------- 1 file changed, 143 insertions(+), 112 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 207282157..91deec4dd 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -2,7 +2,7 @@ // // Written: me@KatherineParry.com, james.stine@okstate.edu // -// Purpose: Testbench for Testfloat +// Purpose: Testbench for UCB Testfloat on Wally // // A component of the Wally configurable RISC-V project. // @@ -21,18 +21,21 @@ // either express or implied. See the License for the specific language governing permissions // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -//`include "wally-config.vh" + `include "config.vh" `include "tests-fp.vh" import cvw::*; module testbenchfp; + // Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir + // to run specific precisions (e.g., quad or all) parameter TEST="none"; parameter TEST_SIZE="none"; `include "parameter-defs.vh" + // FIXME: needs cleaning of unused variables (jes) string Tests[]; // list of tests to be run logic [2:0] OpCtrl[]; // list of op controls logic [2:0] Unit[]; // list of units being tested @@ -61,7 +64,8 @@ module testbenchfp; logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit - logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags + logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags + logic [4:0] CmpFlg; // Outputed flags logic AnsNaN, ResNaN, NaNGood; logic Xs, Ys, Zs; // sign of the inputs logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs @@ -72,7 +76,7 @@ module testbenchfp; logic XInf, YInf, ZInf; // is the input infinity logic XZero, YZero, ZZero; // is the input zero logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones - logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) + logic [P.CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) logic IntZero; logic CvtResSgnE; logic [P.NE:0] CvtCalcExpE; // the calculated exponent @@ -114,8 +118,8 @@ module testbenchfp; logic [P.NE+1:0] QeM; logic [P.DIVb:0] QmM; logic [P.XLEN-1:0] FIntDivResultM; - logic ResMatch; // Check if result matches - logic FlagMatch; // Check if flag matches + logic ResMatch; // Check if result match + logic FlagMatch; // Check if IEEE flags match logic CheckNow; // Final check /////////////////////////////////////////////////////////////////////////////////////////////// @@ -139,6 +143,7 @@ module testbenchfp; // all - test all of the above initial begin + // Information displayed for user on what is simulating $display("\nThe start of simulation..."); $display("This simulation for TEST is %s", TEST); $display("This simulation for TEST is of the operand size of %s", TEST_SIZE); @@ -168,7 +173,7 @@ module testbenchfp; end // if the floating-point conversions are being tested if (TEST === "cvtfp" | TEST === "all") begin - if(P.D_SUPPORTED) begin // if double precision is supported + if (P.D_SUPPORTED) begin // if double precision is supported // add the 128 <-> 64 bit conversions to the to-be-tested list Tests = {Tests, f128f64cvt}; // add the op-ctrls (i.e. the format of the result) @@ -184,7 +189,7 @@ module testbenchfp; Fmt = {Fmt, 2'b01}; end end - if(P.F_SUPPORTED) begin // if single precision is supported + if (P.F_SUPPORTED) begin // if single precision is supported // add the 128 <-> 32 bit conversions to the to-be-tested list Tests = {Tests, f128f32cvt}; // add the op-ctrls (i.e. the format of the result) @@ -200,7 +205,7 @@ module testbenchfp; Fmt = {Fmt, 2'b00}; end end - if(P.ZFH_SUPPORTED) begin // if half precision is supported + if (P.ZFH_SUPPORTED) begin // if half precision is supported // add the 128 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f128f16cvt}; // add the op-ctrls (i.e. the format of the result) @@ -311,7 +316,7 @@ module testbenchfp; end end if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested - if(P.F_SUPPORTED) begin // if single precision is supported + if (P.F_SUPPORTED) begin // if single precision is supported // add the 64 <-> 32 bit conversions to the to-be-tested list Tests = {Tests, f64f32cvt}; // add the op-ctrls (i.e. the format of the result) @@ -327,7 +332,7 @@ module testbenchfp; Fmt = {Fmt, 2'b00}; end end - if(P.ZFH_SUPPORTED) begin // if half precision is supported + if (P.ZFH_SUPPORTED) begin // if half precision is supported // add the 64 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f64f16cvt}; // add the op-ctrls (i.e. the format of the result) @@ -438,7 +443,7 @@ module testbenchfp; end end if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested - if(P.ZFH_SUPPORTED) begin + if (P.ZFH_SUPPORTED) begin // add the 32 <-> 16 bit conversions to the to-be-tested list Tests = {Tests, f32f16cvt}; // add the op-ctrls (i.e. the format of the result) @@ -618,7 +623,6 @@ module testbenchfp; end end end - // check if nothing is being tested if (Tests.size() == 0) begin $display("TEST %s not supported in this configuration", TEST); @@ -644,7 +648,7 @@ module testbenchfp; string tt0; tt0 = $psprintf("%s", Tests[TestNum]); testname = {p, tt0}; - //$display("Here you are %s", testname); + $display("Here you are %s", testname); $display("\n\nRunning %s vectors ", Tests[TestNum]); $readmemh(testname, TestVectors); // set the test index to 0 @@ -662,7 +666,7 @@ module testbenchfp; // - 1 for the larger precision // - 0 for the smaller precision always_comb begin - if(P.FMTBITS == 1) ModFmt = FmtVal == P.FMT; + if (P.FMTBITS == 1) ModFmt = FmtVal == P.FMT; else ModFmt = FmtVal; end @@ -722,6 +726,7 @@ module testbenchfp; .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); end + if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt fdivsqrt #(P) fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), @@ -765,7 +770,7 @@ module testbenchfp; // Check if the correct answer and result is a NaN always_comb begin - if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin + if (UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin // an integer output can't be a NaN AnsNaN = 1'b0; ResNaN = 1'b0; @@ -818,7 +823,7 @@ module testbenchfp; `FMAUNIT: Res = FpRes; `DIVUNIT: Res = FpRes; `CMPUNIT: Res = CmpRes; - `CVTINTUNIT: if(WriteIntVal) Res = IntRes; else Res = FpRes; + `CVTINTUNIT: if (WriteIntVal) Res = IntRes; else Res = FpRes; `CVTFPUNIT: Res = FpRes; endcase @@ -836,13 +841,35 @@ module testbenchfp; OldFDivBusyE = FDivDoneE; // For FP division this adds extra clock cycles to make sure the - // computation completes. 18 clocks cycles are utilize to handle - // Quad, but this can be changed for each precision to go faster. + // computation completes. always @(posedge clk) begin // Add extra clock cycles in beginning for fdivsqrt to adequate reset state - if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin - repeat (18) - @(posedge clk); + if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin + // This allows specific number of clocks to allow each vector + // to complete for division or square root. It is an + // arbitrary value and can be changed, if needed. + case (FmtVal) + // QP + 4'b11: begin + repeat (20) + @(posedge clk); + end + // HP + 4'b10: begin + repeat (14) + @(posedge clk); + end + // DP + 4'b01: begin + repeat (18) + @(posedge clk); + end + // SP + 4'b00: begin + repeat (16) + @(posedge clk); + end + endcase // case (FmtVal) if (reset != 1'b1) VectorNum += 1; // increment the vector end @@ -850,7 +877,6 @@ module testbenchfp; // check results on falling edge of clk always @(negedge clk) begin - // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: // - the sign of the NaN does not matter for the opperations being tested // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter @@ -935,10 +961,11 @@ module testbenchfp; // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... - else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | - (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | - (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin + else if ((UnitVal === `CVTINTUNIT) & + ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[P.XLEN-1:0] === (P.XLEN)'(0))) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[P.XLEN-1:0] === {1'b0, {P.XLEN-1{1'b1}}})) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[P.XLEN-1:0] === {{P.XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | + (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin errors += 1; $display("There is an error in %s", Tests[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); @@ -955,17 +982,15 @@ module testbenchfp; // set the vector index back to 0 VectorNum = 0; // incemet the operation if all the rounding modes have been tested - if(FrmNum === 4) OpCtrlNum += 1; + if (FrmNum === 4) OpCtrlNum += 1; // increment the rounding mode or loop back to rne - if(FrmNum < 4) FrmNum += 1; + if (FrmNum < 4) FrmNum += 1; else FrmNum = 0; - // if no more Tests - finish - if(Tests[TestNum] === "") begin + if (Tests[TestNum] === "") begin $display("\nAll Tests completed with %d errors\n", errors); $stop; end - $display("Running %s vectors", Tests[TestNum]); end end @@ -1000,105 +1025,108 @@ module readvectors ( localparam Q_LEN = 32'd128; `include "parameter-defs.vh" - logic XEn, YEn, ZEn; + logic XEn; + logic YEn; + logic ZEn; logic FPUActive; // apply test vectors on rising edge of clk // Format of vectors Inputs(1/2/3)_AnsFlg always @(VectorNum) begin - // Initial delay is given to allow vector to work for fdiv - // otherwise it will fail on first vector - fix needed (jes) DivStart = 1'b0; - #20; + #1; AnsFlg = TestVector[4:0]; - DivStart = 1'b0; case (Unit) `FMAUNIT: case (Fmt) - 2'b11: begin // quad - if(OpCtrl === `FMA_OPCTRL) begin + 2'b11: begin // quad + if (OpCtrl === `FMA_OPCTRL) begin X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)]; Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; Z = TestVector[8+2*(P.Q_LEN)-1:8+P.Q_LEN]; end else begin X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; - if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; + if (OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)}; + if (OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; end Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (P.D_SUPPORTED)begin // double - if(OpCtrl === `FMA_OPCTRL) begin + 2'b01: if (P.D_SUPPORTED) begin // double + if (OpCtrl === `FMA_OPCTRL) begin X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]}; Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]}; end else begin X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; + if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; else Y = {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}}; + if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}}; else Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; end Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (P.S_SUPPORTED)begin // single - if(OpCtrl === `FMA_OPCTRL) begin + 2'b00: if (P.S_SUPPORTED) begin // single + if (OpCtrl === `FMA_OPCTRL) begin X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]}; end else begin X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; + if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; else Y = {{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}}; + if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}}; else Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; end Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end - 2'b10: begin // half - if(OpCtrl === `FMA_OPCTRL) begin + 2'b10: begin // half + if (OpCtrl === `FMA_OPCTRL) begin X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]}; Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]}; end else begin X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; - if(OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; + if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; else Y = {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}; - if(OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}}; + if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}}; else Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; end Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase `DIVUNIT: - if(OpCtrl[0]) + if (OpCtrl[0]) case (Fmt) - 2'b11: begin // quad + 2'b11: begin // quad + #20; X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; if (~clk) #5; DivStart = 1'b1; #10 // one clk cycle DivStart = 1'b0; end - 2'b01: if (P.D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double + #20; X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; end - 2'b00: if (P.S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED) begin // single + #20; X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; if (~clk) #5; DivStart = 1'b1; #10 DivStart = 1'b0; end - 2'b10: begin // half + 2'b10: begin // half + #20; X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; if (~clk) #5; @@ -1108,7 +1136,8 @@ module readvectors ( endcase else case (Fmt) - 2'b11: begin // quad + 2'b11: begin // quad + #20; X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)]; Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; @@ -1116,7 +1145,8 @@ module readvectors ( DivStart = 1'b1; #10 // one clk cycle DivStart = 1'b0; end - 2'b01: if (P.D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double + #20; X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; @@ -1124,7 +1154,8 @@ module readvectors ( DivStart = 1'b1; #10 DivStart = 1'b0; end - 2'b00: if (P.S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED) begin // single + #20; X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; @@ -1132,7 +1163,8 @@ module readvectors ( DivStart = 1'b1; #10 DivStart = 1'b0; end - 2'b10: begin // half + 2'b10: begin // half + #20; X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; @@ -1143,22 +1175,22 @@ module readvectors ( endcase `CMPUNIT: case (Fmt) - 2'b11: begin // quad + 2'b11: begin // quad X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)]; Y = TestVector[12+(P.Q_LEN)-1:12]; Ans = TestVector[8]; end - 2'b01: if (P.D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]}; Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]}; Ans = TestVector[8]; end - 2'b00: if (P.S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]}; Ans = TestVector[8]; end - 2'b10: begin // half + 2'b10: begin // half X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]}; Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]}; Ans = TestVector[8]; @@ -1166,188 +1198,187 @@ module readvectors ( endcase `CVTFPUNIT: case (Fmt) - 2'b11: begin // quad + 2'b11: begin // quad case (OpCtrl[1:0]) - 2'b11: begin // quad + 2'b11: begin // quad X = {TestVector[8+P.Q_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (P.D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: begin // single + 2'b00: begin // single X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end - 2'b10: begin // half + 2'b10: begin // half X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end - 2'b01: if (P.D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double case (OpCtrl[1:0]) - 2'b11: begin // quad + 2'b11: begin // quad X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: begin // double + 2'b01: begin // double X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: begin // single + 2'b00: begin // single X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end - 2'b10: begin // half + 2'b10: begin // half X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end - 2'b00: if (P.S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED) begin // single case (OpCtrl[1:0]) - 2'b11: begin // quad + 2'b11: begin // quad X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (P.D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: begin // single + 2'b00: begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end - 2'b10: begin // half + 2'b10: begin // half X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end - 2'b10: begin // half + 2'b10: begin // half case (OpCtrl[1:0]) - 2'b11: begin // quad + 2'b11: begin // quad X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: if (P.D_SUPPORTED)begin // double + 2'b01: if (P.D_SUPPORTED) begin // double X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (P.S_SUPPORTED)begin // single + 2'b00: if (P.S_SUPPORTED) begin // single X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end - 2'b10: begin // half + 2'b10: begin // half X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end endcase end - endcase - + endcase `CVTINTUNIT: case (Fmt) - 2'b11: begin // quad - // {is the integer a long, is the opperation to an integer} + 2'b11: begin // quad + // {is the integer a long, is the opperation to an integer} casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> quad + 2'b11: begin // long -> quad X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b10: begin // int -> quad + 2'b10: begin // int -> quad // correctly sign extend the integer depending on if it's a signed/unsigned test X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; end - 2'b01: begin // quad -> long + 2'b01: begin // quad -> long X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; Ans = {TestVector[8+(P.XLEN-1):8]}; end - 2'b00: begin // quad -> int + 2'b00: begin // quad -> int X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end - 2'b01: if (P.D_SUPPORTED) begin // double - // {Int->Fp?, is the integer a long} + 2'b01: if (P.D_SUPPORTED) begin // double + // {Int->Fp?, is the integer a long} casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> double + 2'b11: begin // long -> double X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b10: begin // int -> double + 2'b10: begin // int -> double // correctly sign extend the integer depending on if it's a signed/unsigned test X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b01: begin // double -> long + 2'b01: begin // double -> long X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; Ans = {TestVector[8+(P.XLEN-1):8]}; end - 2'b00: begin // double -> int + 2'b00: begin // double -> int X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end - 2'b00: if (P.S_SUPPORTED)begin // single - // {is the integer a long, is the opperation to an integer} + 2'b00: if (P.S_SUPPORTED) begin // single + // {is the integer a long, is the opperation to an integer} casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> single + 2'b11: begin // long -> single X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end - 2'b10: begin // int -> single + 2'b10: begin // int -> single // correctly sign extend the integer depending on if it's a signed/unsigned test X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end - 2'b01: begin // single -> long + 2'b01: begin // single -> long X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; Ans = {TestVector[8+(P.XLEN-1):8]}; end - 2'b00: begin // single -> int + 2'b00: begin // single -> int X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end - 2'b10: begin // half - // {is the integer a long, is the opperation to an integer} + 2'b10: begin // half + // {is the integer a long, is the opperation to an integer} casex ({OpCtrl[2:1]}) - 2'b11: begin // long -> half + 2'b11: begin // long -> half X = {P.FLEN{1'bx}}; SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)]; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end - 2'b10: begin // int -> half + 2'b10: begin // int -> half // correctly sign extend the integer depending on if it's a signed/unsigned test X = {P.FLEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]}; Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end - 2'b01: begin // half -> long + 2'b01: begin // half -> long X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; Ans = {TestVector[8+(P.XLEN-1):8]}; end - 2'b00: begin // half -> int + 2'b00: begin // half -> int X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; From ebb44e9df3bd79ba47c58fab088879e11f94d4d1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 27 Jun 2023 11:04:20 -0500 Subject: [PATCH 21/54] Updates for fpga. --- fpga/constraints/debug2.xdc | 6 +- fpga/constraints/small-debug.xdc | 14 ++-- sim/wave.do | 140 +++++++++++++++---------------- 3 files changed, 77 insertions(+), 83 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 58e2fa643..f09acb6c1 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -1107,7 +1107,7 @@ connect_debug_port u_ila_0/probe215 [get_nets [list {wallypipelinedsocwrapper/wa create_debug_port u_ila_0 probe set_property port_width 10 [get_debug_ports u_ila_0/probe216] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] -connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] +connect_debug_port u_ila_0/probe216 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][2]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][3]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][4]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][5]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][6]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][7]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][8]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][9]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1][10]} ]] create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe217] @@ -1132,12 +1132,12 @@ connect_debug_port u_ila_0/probe220 [get_nets [list {wallypipelinedsocwrapper/wa create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe221] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe221] -connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0]__0[2]} ]] +connect_debug_port u_ila_0/probe221 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[0][2]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe222] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe222] -connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1]__0[2]} ]] +connect_debug_port u_ila_0/probe222 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][0]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][1]} {wallypipelinedsocwrapper/wallypipelinedsoc/uncore.uncore/plic.plic/intThreshold[1][2]} ]] create_debug_port u_ila_0 probe set_property port_width 53 [get_debug_ports u_ila_0/probe223] diff --git a/fpga/constraints/small-debug.xdc b/fpga/constraints/small-debug.xdc index b50777f0d..2938c3ec0 100644 --- a/fpga/constraints/small-debug.xdc +++ b/fpga/constraints/small-debug.xdc @@ -21,32 +21,32 @@ connect_debug_port u_ila_0/clk [get_nets CPUCLK] set_property port_width 64 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/PCM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe1] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe2] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] -connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] +connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrValidM ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe3] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/InstrM[31]} ]] create_debug_port u_ila_0 probe set_property port_width 32 [get_debug_ports u_ila_0/probe4] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe5] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]] +connect_debug_port u_ila_0/probe5 [get_nets [list wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHREADY ]] create_debug_port u_ila_0 probe set_property port_width 28 [get_debug_ports u_ila_0/probe6] @@ -131,7 +131,7 @@ connect_debug_port u_ila_0/probe21 [get_nets [list {BUS_axi_wvalid}]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe22] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsocwrapper/wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] diff --git a/sim/wave.do b/sim/wave.do index e9461d589..73aaf02d8 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -11,37 +11,37 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -74,26 +74,27 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW -add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW -add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW -add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW +add wave -noupdate -expand -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]} +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check} add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE @@ -520,8 +521,8 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} -add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -group {Performance Counters} -label MCYCLE -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} @@ -594,26 +595,19 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE -add wave -noupdate /testbench/LoadMem -add wave -noupdate /testbench/CurrState -add wave -noupdate /testbench/DCacheFlushStart -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/InstrMName -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/c/InstrValidM -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/a3 -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/rf -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/wd3 -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/we3 -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ifu/InstrM -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/ecf -add wave -noupdate /testbench/ecf -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/ce -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/we -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/addr -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/dout -add wave -noupdate /testbench/reset +add wave -noupdate /testbench/dut/core/priv/priv/privmode/PrivilegeModeW +add wave -noupdate /testbench/dut/core/priv/priv/STATUS_MIE +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/clk +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrValidW +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/PCW +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrRawW +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/valid TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {320072 ns} 0} {{Cursor 4} {19809168 ns} 1} +WaveRestoreCursors {{Cursor 4} {6170 ns} 0} {{Cursor 4} {19809168 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -629,4 +623,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {319935 ns} {320329 ns} +WaveRestoreZoom {6124 ns} {6284 ns} From 407bf4454859c956ce71f88ddaafbd332b17ef14 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 29 Jun 2023 08:46:11 -0500 Subject: [PATCH 22/54] Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion. --- testbench/testbench-fp.sv | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index 91deec4dd..08d674f1d 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -121,7 +121,8 @@ module testbenchfp; logic ResMatch; // Check if result match logic FlagMatch; // Check if IEEE flags match logic CheckNow; // Final check - + logic FMAop; // Is this a FMA operation? + /////////////////////////////////////////////////////////////////////////////////////////////// // ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| ||| @@ -944,13 +945,15 @@ module testbenchfp; assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); + assign FMAop = (OpCtrlVal == `FMAUNIT); assign DivDone = OldFDivBusyE & ~FDivBusyE; - assign CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); + // Maybe change OpCtrl but for now just look at TEST for fma test + assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT); if (~(ResMatch & FlagMatch) & CheckNow) begin errors += 1; - $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); - $display("Error in %s", Tests[TestNum]); + $display("\nError in %s", Tests[TestNum]); + $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $stop; end From 76a2a51d688dda1467db3b0f6a77ae12c58734c7 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Thu, 29 Jun 2023 08:47:16 -0500 Subject: [PATCH 23/54] Add reset to wave window --- sim/wave-fpu.do | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/wave-fpu.do b/sim/wave-fpu.do index a1cfa8731..08b6b3378 100644 --- a/sim/wave-fpu.do +++ b/sim/wave-fpu.do @@ -7,6 +7,7 @@ add wave -noupdate /testbenchfp/Y add wave -noupdate /testbenchfp/Z add wave -noupdate /testbenchfp/Res add wave -noupdate /testbenchfp/Ans +add wave -noupdate /testbenchfp/reset add wave -noupdate /testbenchfp/DivStart add wave -noupdate /testbenchfp/FDivBusyE add wave -noupdate /testbenchfp/CheckNow From e05288afd92e2d184605e19667a2665ac0c79240 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 1 Jul 2023 22:48:04 -0700 Subject: [PATCH 24/54] Improved instruction decoding for illegal floating-point loads/stores and fences --- src/fpu/fctrl.sv | 4 ++-- src/ieu/controller.sv | 18 ++++++++++++++---- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 76855bf81..bdc61f784 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -101,13 +101,13 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed case(OpD) 7'b0000111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw + 3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw 3'b011: if (P.D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld 3'b100: if (P.Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq 3'b001: if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh endcase 7'b0100111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw + 3'b010: ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw 3'b011: if (P.D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd 3'b100: if (P.Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq 3'b001: if (P.ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 838560ed1..d191900cc 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -126,7 +126,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions + logic FLSFunctD; // Detect floating-point loads and stores logic JFunctD; // detect jalr instruction + logic FenceFunctD; // Detect fence instruction logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions @@ -156,6 +158,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign MFunctD = (Funct7D == 7'b0000001) & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv assign LFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | ((P.XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110)); + assign FLSFunctD = (Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) | + (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED); + assign FenceFunctD = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001); assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | ((P.XLEN == 64) & (Funct3D == 3'b011)); assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches @@ -166,6 +171,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign RFunctD = ~Funct7D[0]; // Not a multiply assign MFunctD = Funct7D[0] & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv assign LFunctD = 1; // don't bother to check Funct3 for loads + assign FLSFunctD = 1; // don't bother to check Func3 for floating-point loads/stores + assign FenceFunctD = 1; // don't bother to check fields for fences assign SFunctD = 1; // don't bother to check Funct3 for stores assign BFunctD = 1; // don't bother to check Funct3 for branches assign JFunctD = 1; // don't bother to check Funct3 for jumps @@ -178,13 +185,16 @@ module controller import cvw::*; #(parameter cvw_t P) ( ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // default: Illegal instruction case(OpD) // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal - 7'b0000011: if (LFunctD) + 7'b0000011: if (LFunctD) ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // loads - 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported - 7'b0001111: if (P.ZIFENCEI_SUPPORTED) + 7'b0000111: if (FLSFunctD) + ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported + 7'b0001111: if (FenceFunctD) begin + if (P.ZIFENCEI_SUPPORTED) ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence - else + else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop + end 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc From 07cf1dd9da288e9a84327e3bffed9cecfc1816d6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 1 Jul 2023 23:10:57 -0700 Subject: [PATCH 25/54] improved decoder checking atomic instructions --- src/ieu/controller.sv | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d191900cc..5a2542614 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -83,7 +83,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage - logic [4:0] Rs1D; // Rs1 source register in Decode stage + logic [4:0] Rs1D, Rs2D; // Rs1/2 source register in Decode stage `define CTRLW 23 @@ -129,6 +129,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FLSFunctD; // Detect floating-point loads and stores logic JFunctD; // detect jalr instruction logic FenceFunctD; // Detect fence instruction + logic AFunctD, AMOFunctD; // Detect atomic instructions logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions @@ -138,6 +139,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign Funct3D = InstrD[14:12]; assign Funct7D = InstrD[31:25]; assign Rs1D = InstrD[19:15]; + assign Rs2D = InstrD[24:20]; // Funct 7 checking // Be rigorous about detecting illegal instructions if CSRs or bit manipulation is supported @@ -161,6 +163,16 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign FLSFunctD = (Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) | (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED); assign FenceFunctD = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001); + assign AFunctD = (Funct3D == 3'b010); + assign AMOFunctD = (InstrD[31:27] == 5'b00001) | + (InstrD[31:27] == 5'b00000) | + (InstrD[31:27] == 5'b00100) | + (InstrD[31:27] == 5'b01100) | + (InstrD[31:27] == 5'b01000) | + (InstrD[31:27] == 5'b10000) | + (InstrD[31:27] == 5'b10100) | + (InstrD[31:27] == 5'b11000) | + (InstrD[31:27] == 5'b11100); assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | ((P.XLEN == 64) & (Funct3D == 3'b011)); assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches @@ -173,6 +185,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign LFunctD = 1; // don't bother to check Funct3 for loads assign FLSFunctD = 1; // don't bother to check Func3 for floating-point loads/stores assign FenceFunctD = 1; // don't bother to check fields for fences + assign AFunctD = 1; // don't bother to check fields for atomics + assign AMOFunctD = 1; // don't bother to check Funct7 for AMO operations assign SFunctD = 1; // don't bother to check Funct3 for stores assign BFunctD = 1; // don't bother to check Funct3 for branches assign JFunctD = 1; // don't bother to check Funct3 for jumps @@ -202,13 +216,14 @@ module controller import cvw::*; #(parameter cvw_t P) ( ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i 7'b0100011: if (SFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores - 7'b0100111: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported - 7'b0101111: if (P.A_SUPPORTED) begin - if (InstrD[31:27] == 5'b00010) + 7'b0100111: if (FLSFunctD) + ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported + 7'b0101111: if (P.A_SUPPORTED & AFunctD) begin + if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr else if (InstrD[31:27] == 5'b00011) ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc - else + else if (AMOFunctD) ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end 7'b0110011: if (RFunctD) From 110dd42cfbfa925324dd1b341b32b8336fe3d1eb Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 00:02:03 -0700 Subject: [PATCH 26/54] improved decoder checking atomic and RW and MW and privileged instructions --- src/ieu/controller.sv | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 5a2542614..677c6b0a2 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -83,7 +83,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage - logic [4:0] Rs1D, Rs2D; // Rs1/2 source register in Decode stage + logic [4:0] Rs1D, Rs2D, RdD; // Rs1/2 source register / dest reg in Decode stage `define CTRLW 23 @@ -127,19 +127,22 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions logic FLSFunctD; // Detect floating-point loads and stores - logic JFunctD; // detect jalr instruction + logic JRFunctD; // detect jalr instruction logic FenceFunctD; // Detect fence instruction logic AFunctD, AMOFunctD; // Detect atomic instructions + logic RWFunctD, MWFunctD; // detect RW/MW instructions + logic PFunctD, CSRFunctD; // detect privileged / CSR instruction logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions // Extract fields - assign OpD = InstrD[6:0]; + assign OpD = InstrD[6:0]; assign Funct3D = InstrD[14:12]; assign Funct7D = InstrD[31:25]; - assign Rs1D = InstrD[19:15]; - assign Rs2D = InstrD[24:20]; + assign Rs1D = InstrD[19:15]; + assign Rs2D = InstrD[24:20]; + assign RdD = InstrD[11:7]; // Funct 7 checking // Be rigorous about detecting illegal instructions if CSRs or bit manipulation is supported @@ -163,7 +166,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign FLSFunctD = (Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) | (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED); assign FenceFunctD = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001); - assign AFunctD = (Funct3D == 3'b010); + assign AFunctD = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011); assign AMOFunctD = (InstrD[31:27] == 5'b00001) | (InstrD[31:27] == 5'b00000) | (InstrD[31:27] == 5'b00100) | @@ -173,10 +176,15 @@ module controller import cvw::*; #(parameter cvw_t P) ( (InstrD[31:27] == 5'b10100) | (InstrD[31:27] == 5'b11000) | (InstrD[31:27] == 5'b11100); + assign RWFunctD = ((Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101) & Funct7ZeroD | + (Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) & (P.XLEN == 64); + assign MWFunctD = MFunctD & (P.XLEN == 64) & ~(Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b011); assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | ((P.XLEN == 64) & (Funct3D == 3'b011)); - assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches - assign JFunctD = (Funct3D == 3'b000); + assign BFunctD = Funct3D[2:1] != 2'b01; // legal branches + assign JRFunctD = Funct3D == 3'b000; + assign PFunctD = Funct3D == 3'b000 & Rs1D == 5'b0 & RdD == 5'b0; + assign CSRFunctD = Funct3D[1:0] != 2'b00; assign IWValidFunct3D = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101; end else begin:legalcheck2 assign IFunctD = 1; // Don't bother to separate out shift decoding @@ -187,9 +195,13 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign FenceFunctD = 1; // don't bother to check fields for fences assign AFunctD = 1; // don't bother to check fields for atomics assign AMOFunctD = 1; // don't bother to check Funct7 for AMO operations + assign RWFunctD = 1; // don't bother to check fields for RW instructions + assign MWFunctD = 1; // don't bother to check fields for MW instructions assign SFunctD = 1; // don't bother to check Funct3 for stores assign BFunctD = 1; // don't bother to check Funct3 for branches - assign JFunctD = 1; // don't bother to check Funct3 for jumps + assign JRFunctD = 1; // don't bother to check Funct3 for jalrs + assign PFunctD = 1; // don't bother to check fields for privileged instructions + assign CSRFunctD = 1; // don't bother to check Funct3 for CSR operations assign IWValidFunct3D = 1; end @@ -231,19 +243,19 @@ module controller import cvw::*; #(parameter cvw_t P) ( else if (MFunctD) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui - 7'b0111011: if (RFunctD & (P.XLEN == 64)) + 7'b0111011: if (RWFunctD) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i - else if (MFunctD & (P.XLEN == 64)) + else if (MWFunctD) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide 7'b1100011: if (BFunctD) ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches - 7'b1100111: if (JFunctD) + 7'b1100111: if (JRFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal 7'b1110011: if (P.ZICSR_SUPPORTED) begin - if (Funct3D == 3'b000) - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules - else + if (PFunctD) + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in privdec modules + else if (CSRFunctD) ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs end endcase From 4d1ddd0c914deacdaba169e12453ce1b38ff7cb5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 00:34:30 -0700 Subject: [PATCH 27/54] Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations --- src/ieu/controller.sv | 73 +++++++++++++++++++-------------- src/ieu/ieu.sv | 6 ++- src/privileged/csrm.sv | 6 +-- src/wally/wallypipelinedcore.sv | 5 ++- 4 files changed, 52 insertions(+), 38 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 677c6b0a2..28ca04e4d 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -32,6 +32,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage + input logic [1:0] STATUS_FS, // is FPU enabled? output logic [2:0] ImmSrcD, // Type of immediate extension input logic IllegalIEUFPUInstrD, // Illegal IEU and FPU instruction output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers @@ -60,6 +61,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE, // Bit manipulation instruction being executed output logic MDUActiveE, // Mul/Div instruction being executed + output logic CMOE, // Cache Management operation being executed // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage @@ -85,7 +87,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs1D, Rs2D, RdD; // Rs1/2 source register / dest reg in Decode stage - `define CTRLW 23 + `define CTRLW 24 // pipelined control signals logic RegWriteD, RegWriteE; // RegWrite (register will be written) @@ -103,6 +105,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic CSRReadD; // CSR read instruction logic [1:0] AtomicD; // Atomic (AMO) instruction logic FenceXD; // Fence instruction + logic CMOD; // Cache management instruction logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$ logic CSRWriteD, CSRWriteE; // CSR write logic PrivilegedD, PrivilegedE; // Privileged instruction @@ -129,6 +132,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FLSFunctD; // Detect floating-point loads and stores logic JRFunctD; // detect jalr instruction logic FenceFunctD; // Detect fence instruction + logic CMOFunctD; logic AFunctD, AMOFunctD; // Detect atomic instructions logic RWFunctD, MWFunctD; // detect RW/MW instructions logic PFunctD, CSRFunctD; // detect privileged / CSR instruction @@ -163,9 +167,13 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign MFunctD = (Funct7D == 7'b0000001) & (P.M_SUPPORTED | (P.ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv assign LFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | ((P.XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110)); - assign FLSFunctD = (Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) | - (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED); + assign FLSFunctD = (STATUS_FS != 2'b00) & ((Funct3D == 3'b010 & P.F_SUPPORTED) | (Funct3D == 3'b011 & P.D_SUPPORTED) | + (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED)); assign FenceFunctD = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001); + assign CMOFunctD = (Funct3D == 3'b010 & RdD == 5'b0) & + ((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4) | + (P.ZICBOM_SUPPORTED & (InstrD[31:20] == 12'd0 | InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2))); + // *** need to get with enable bits such as MENVCFG_CBZE assign AFunctD = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011); assign AMOFunctD = (InstrD[31:27] == 5'b00001) | (InstrD[31:27] == 5'b00000) | @@ -193,6 +201,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign LFunctD = 1; // don't bother to check Funct3 for loads assign FLSFunctD = 1; // don't bother to check Func3 for floating-point loads/stores assign FenceFunctD = 1; // don't bother to check fields for fences + assign CMOFunctD = 1; // don't bother to check fields for CMO instructions assign AFunctD = 1; // don't bother to check fields for atomics assign AMOFunctD = 1; // don't bother to check Funct7 for AMO operations assign RWFunctD = 1; // don't bother to check fields for RW instructions @@ -208,55 +217,57 @@ module controller import cvw::*; #(parameter cvw_t P) ( // Main Instruction Decoder /* verilator lint_off CASEINCOMPLETE */ always_comb begin - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // default: Illegal instruction + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_1; // default: Illegal instruction case(OpD) - // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal + // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_CMO_Illegal 7'b0000011: if (LFunctD) - ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // loads + ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_0; // loads 7'b0000111: if (FLSFunctD) - ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported + ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0_1; // flw - only legal if FP supported 7'b0001111: if (FenceFunctD) begin if (P.ZIFENCEI_SUPPORTED) - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0_0; // fence else - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // fence treated as nop + end else if (CMOFunctD) begin + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1_0; // CMO Instruction end 7'b0010011: if (IFunctD) - ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU - 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc + ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // I-type ALU + 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0_0; // auipc 7'b0011011: if (IFunctD & IWValidFunct3D & P.XLEN == 64) - ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i + ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // IW-type ALU for RV64i 7'b0100011: if (SFunctD) - ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores + ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores 7'b0100111: if (FLSFunctD) - ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported + ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported 7'b0101111: if (P.A_SUPPORTED & AFunctD) begin if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) - ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr + ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr else if (InstrD[31:27] == 5'b00011) - ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc + ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc else if (AMOFunctD) - ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo + ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo end 7'b0110011: if (RFunctD) - ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type + ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0_0; // R-type else if (MFunctD) - ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide - 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui + ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0_0; // Multiply/divide + 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0_0; // lui 7'b0111011: if (RWFunctD) - ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i + ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0_0; // R-type W instructions for RV64i else if (MWFunctD) - ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide + ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0_0; // W-type Multiply/Divide 7'b1100011: if (BFunctD) - ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches + ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0_0; // branches 7'b1100111: if (JRFunctD) - ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr - 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal + ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jalr + 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0_0; // jal 7'b1110011: if (P.ZICSR_SUPPORTED) begin if (PFunctD) - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in privdec modules + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0_0; // privileged; decoded further in privdec modules else if (CSRFunctD) - ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs + ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0_0; // csrs end endcase end @@ -269,7 +280,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( //assign IllegalBaseInstrD = 1'b0; assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, - PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; + PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros @@ -341,9 +352,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(29) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(30) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index c4e60aca9..444080c62 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -30,6 +30,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Decode stage signals input logic [31:0] InstrD, // Instruction + input logic [1:0] STATUS_FS, // is FPU enabled? input logic IllegalIEUFPUInstrD, // Illegal instruction output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers // Execute stage signals @@ -43,6 +44,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B output logic [4:0] RdE, // Destination register output logic MDUActiveE, // Mul/Div instruction being executed + output logic CMOE, // Cache management instruction being executed // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU output logic [1:0] MemRWM, // Read/write control goes to LSU @@ -97,11 +99,11 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic BMUActiveE; // Bit manipulation instruction being executed controller #(P) c( - .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, + .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, - .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, + .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 61226f790..bce7af681 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -197,10 +197,10 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign MENVCFG_STCE = MENVCFG_REGW[63]; // Uncomment these other fields when they are defined // assign MENVCFG_PBMTE = MENVCFG_REGW[62]; - // assign MENVCFG_CBZE = MENVCFG_REGW[7]; + // assign MENVCFG_CBZE = MENVCFG_REGW[7]; // assign MENVCFG_CBCFE = MENVCFG_REGW[6]; - // assign MENVCFG_CBIE = MENVCFG_REGW[5:4]; - // assign MENVCFG_FIOM = MENVCFG_REGW[0]; + // assign MENVCFG_CBIE = MENVCFG_REGW[5:4]; + // assign MENVCFG_FIOM = MENVCFG_REGW[0]; // Read machine mode CSRs // verilator lint_off WIDTH diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 39f780a60..ae9931e45 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -78,6 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic SquashSCW; logic MDUActiveE; // Mul/Div instruction being executed + logic CMOE; // Cache management instruction being executed // floating point unit signals logic [2:0] FRM_REGW; @@ -188,10 +189,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( // integer execution unit: integer register file, datapath and controller ieu #(P) ieu(.clk, .reset, // Decode Stage interface - .InstrD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, + .InstrD, .STATUS_FS, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU From e2708534cd2a0f61fcb81eced9bbd2c13b06a7a0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 01:52:25 -0700 Subject: [PATCH 28/54] Added environment configuration control (menvcfg/senvcfg) of cbo instructions --- src/ieu/controller.sv | 6 ++++-- src/ieu/ieu.sv | 3 ++- src/privileged/csr.sv | 25 ++++++++++++++++++++----- src/privileged/csri.sv | 4 ++-- src/privileged/csrm.sv | 12 +----------- src/privileged/csrs.sv | 25 +++++++++---------------- src/privileged/privileged.sv | 3 ++- src/wally/wallypipelinedcore.sv | 7 ++++--- 8 files changed, 44 insertions(+), 41 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 28ca04e4d..55a2d7bac 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -33,6 +33,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage input logic [1:0] STATUS_FS, // is FPU enabled? + input logic [3:0] ENVCFG_CBE, // Cache block operation enables output logic [2:0] ImmSrcD, // Type of immediate extension input logic IllegalIEUFPUInstrD, // Illegal IEU and FPU instruction output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers @@ -171,8 +172,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( (Funct3D == 3'b100 & P.Q_SUPPORTED) | (Funct3D == 3'b001 & P.ZFH_SUPPORTED)); assign FenceFunctD = (Funct3D == 3'b000) | (P.ZIFENCEI_SUPPORTED & Funct3D == 3'b001); assign CMOFunctD = (Funct3D == 3'b010 & RdD == 5'b0) & - ((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4) | - (P.ZICBOM_SUPPORTED & (InstrD[31:20] == 12'd0 | InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2))); + ((P.ZICBOZ_SUPPORTED & InstrD[31:20] == 12'd4 & ENVCFG_CBE[3]) | + (P.ZICBOM_SUPPORTED & ((InstrD[31:20] == 12'd0 & (ENVCFG_CBE[1:0] != 2'b00))) | + (InstrD[31:20] == 12'd1 | InstrD[31:20] == 12'd2) & ENVCFG_CBE[2])); // *** need to get with enable bits such as MENVCFG_CBZE assign AFunctD = (Funct3D == 3'b010) | (P.XLEN == 64 & Funct3D == 3'b011); assign AMOFunctD = (InstrD[31:27] == 5'b00001) | diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 444080c62..f930b1103 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -31,6 +31,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( // Decode stage signals input logic [31:0] InstrD, // Instruction input logic [1:0] STATUS_FS, // is FPU enabled? + input logic [3:0] ENVCFG_CBE, // Cache block operation enables input logic IllegalIEUFPUInstrD, // Illegal instruction output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers // Execute stage signals @@ -99,7 +100,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic BMUActiveE; // Bit manipulation instruction being executed controller #(P) c( - .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ImmSrcD, + .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index fba8a89c5..5b2ea802a 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -84,6 +84,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0], output logic [2:0] FRM_REGW, + output logic [3:0] ENVCFG_CBE, // output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns @@ -123,7 +124,11 @@ module csr import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] TVecAlignedM; logic InstrValidNotFlushedM; logic STimerInt; - logic MENVCFG_STCE; + logic [63:0] MENVCFG_REGW; + logic [P.XLEN-1:0] SENVCFG_REGW; + logic ENVCFG_STCE; // supervisor timer counter enable + logic ENVCFG_PBMTE; // page-based memory types enable + logic ENVCFG_FIOM; // fence implies io (presently not used) // only valid unflushed instructions can access CSRs assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW; @@ -214,7 +219,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( csri #(P) csri(.clk, .reset, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt, - .MIDELEG_REGW, .MENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); + .MIDELEG_REGW, .ENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); csrsr #(P) csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, @@ -233,10 +238,12 @@ module csr import cvw::*; #(parameter cvw_t P) ( .MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM, .IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM, - .MENVCFG_STCE); + .MENVCFG_REGW); if (P.S_SUPPORTED) begin:csrs + logic STCE; + assign STCE = P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_REGW[1] & ENVCFG_STCE)); csrs #(P) csrs(.clk, .reset, .CSRSWriteM, .STrapM, .CSRAdrM, .NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW, @@ -244,8 +251,8 @@ module csr import cvw::*; #(parameter cvw_t P) ( .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, - .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .MENVCFG_STCE, - .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt); + .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .STCE, + .WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt, .SENVCFG_REGW); end else begin assign WriteSSTATUSM = 0; assign CSRSReadValM = 0; @@ -282,6 +289,14 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign IllegalCSRCAccessM = 1; // counters aren't enabled end + // Broadcast appropriate environment configuration based on privilege mode + assign ENVCFG_STCE = MENVCFG_REGW[63]; // supervisor timer counter enable + assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable + assign ENVCFG_CBE = (PrivilegeModeW == P.M_MODE) ? 4'b1111 : + (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : SENVCFG_REGW[7:4]; + assign ENVCFG_FIOM = (PrivilegeModeW == P.M_MODE) ? 1'b1 : + (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[0] : SENVCFG_REGW[0]; + // merge CSR Reads assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; flopenrc #(P.XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW); diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index ca89617d9..2e5488af7 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -34,7 +34,7 @@ module csri import cvw::*; #(parameter cvw_t P) ( input logic [11:0] CSRAdrM, input logic MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt, input logic [11:0] MIDELEG_REGW, - input logic MENVCFG_STCE, + input logic ENVCFG_STCE, output logic [11:0] MIP_REGW, MIE_REGW, output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); @@ -61,7 +61,7 @@ module csri import cvw::*; #(parameter cvw_t P) ( if (P.S_SUPPORTED) begin:mask if (P.SSTC_SUPPORTED) begin assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec) - assign STIP = MENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5]; + assign STIP = ENVCFG_STCE ? STimerInt : MIP_REGW_writeable[5]; end else begin assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) assign STIP = MIP_REGW_writeable[5]; diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index bce7af681..fd2496c44 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -48,12 +48,11 @@ module csrm import cvw::*; #(parameter cvw_t P) ( output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], output logic WriteMSTATUSM, WriteMSTATUSHM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM, - output logic MENVCFG_STCE + output logic [63:0] MENVCFG_REGW ); logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; - logic [63:0] MENVCFG_REGW; logic [P.XLEN-1:0] MENVCFGH_REGW; logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; @@ -193,15 +192,6 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; end - // Extract bit fields - assign MENVCFG_STCE = MENVCFG_REGW[63]; - // Uncomment these other fields when they are defined - // assign MENVCFG_PBMTE = MENVCFG_REGW[62]; - // assign MENVCFG_CBZE = MENVCFG_REGW[7]; - // assign MENVCFG_CBCFE = MENVCFG_REGW[6]; - // assign MENVCFG_CBIE = MENVCFG_REGW[5:4]; - // assign MENVCFG_FIOM = MENVCFG_REGW[0]; - // Read machine mode CSRs // verilator lint_off WIDTH logic [5:0] entry; diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 97c8b3f22..84a4d0a4b 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -44,10 +44,12 @@ module csrs import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] SATP_REGW, input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic [63:0] MTIME_CLINT, - input logic MENVCFG_STCE, + input logic STCE, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM, - output logic STimerInt + output logic STimerInt, + output logic [P.XLEN-1:0] SENVCFG_REGW + ); // Supervisor CSRs @@ -75,7 +77,6 @@ module csrs import cvw::*; #(parameter cvw_t P) ( logic WriteSENVCFGM; logic [P.XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW; - logic [P.XLEN-1:0] SENVCFG_REGW; logic [P.XLEN-1:0] SENVCFG_WriteValM; logic [63:0] STIMECMP_REGW; @@ -90,8 +91,8 @@ module csrs import cvw::*; #(parameter cvw_t P) ( assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM); assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN); assign WriteSENVCFGM = CSRSWriteM & (CSRAdrM == SENVCFG); - assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE)); - assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM & MENVCFG_STCE)) & (P.XLEN == 32); + assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & STCE; + assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & STCE & (P.XLEN == 32); // CSRs flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); @@ -125,18 +126,10 @@ module csrs import cvw::*; #(parameter cvw_t P) ( CSRWriteValM[7] & P.ZICBOZ_SUPPORTED, CSRWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, 3'b0, - CSRWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED + CSRWriteValM[0] & P.VIRTMEM_SUPPORTED }; flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW); - - // Extract bit fields - // Uncomment these other fields when they are defined - // assign SENVCFG_PBMTE = SENVCFG_REGW[62]; - // assign SENVCFG_CBZE = SENVCFG_REGW[7]; - // assign SENVCFG_CBCFE = SENVCFG_REGW[6]; - // assign SENVCFG_CBIE = SENVCFG_REGW[5:4]; - // assign SENVCFG_FIOM = SENVCFG_REGW[0]; // CSR Reads always_comb begin:csrr @@ -157,13 +150,13 @@ module csrs import cvw::*; #(parameter cvw_t P) ( end SCOUNTEREN:CSRSReadValM = {{(P.XLEN-32){1'b0}}, SCOUNTEREN_REGW}; SENVCFG: CSRSReadValM = SENVCFG_REGW; - STIMECMP: if (P.SSTC_SUPPORTED & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE))) + STIMECMP: if (STCE) CSRSReadValM = STIMECMP_REGW[P.XLEN-1:0]; else begin CSRSReadValM = 0; IllegalCSRSAccessM = 1; end - STIMECMPH: if (P.SSTC_SUPPORTED & (P.XLEN == 32) & (PrivilegeModeW == P.M_MODE | (MCOUNTEREN_TM && MENVCFG_STCE))) + STIMECMPH: if (STCE) CSRSReadValM[31:0] = STIMECMP_REGW[63:32]; else begin // not supported for RV64 CSRSReadValM = 0; diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 95ba2b0bd..1023618b5 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -82,6 +82,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( output var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration entries to MMU output var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW [P.PMP_ENTRIES-1:0], // PMP address entries to MMU output logic [2:0] FRM_REGW, // FPU rounding mode + output logic [3:0] ENVCFG_CBE, // Cache block operation enables // PC logic output in privileged unit output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic // control outputs @@ -136,7 +137,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS, .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .SetFflagsM, .FRM_REGW, + .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM); // pipeline early-arriving trap sources diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index ae9931e45..563e4f987 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -79,6 +79,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic SquashSCW; logic MDUActiveE; // Mul/Div instruction being executed logic CMOE; // Cache management instruction being executed + logic [3:0] ENVCFG_CBE; // Cache block operation enables // floating point unit signals logic [2:0] FRM_REGW; @@ -189,7 +190,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( // integer execution unit: integer register file, datapath and controller ieu #(P) ieu(.clk, .reset, // Decode Stage interface - .InstrD, .STATUS_FS, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, + .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOE, @@ -290,9 +291,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .MTIME_CLINT, .IEUAdrM, .SetFflagsM, .InstrAccessFaultF, .HPTWInstrAccessFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, .PrivilegeModeW, .SATP_REGW, - .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, + .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM); + .FRM_REGW, .ENVCFG_CBE, .BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM); end else begin assign CSRReadValW = 0; assign UnalignedPCNextF = PC2NextF; From 96477a487963c3e487cfa8b87229a2371fed0fc9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 02:00:27 -0700 Subject: [PATCH 29/54] Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode --- src/privileged/csr.sv | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 5b2ea802a..c9cc88f3c 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -293,9 +293,18 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign ENVCFG_STCE = MENVCFG_REGW[63]; // supervisor timer counter enable assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable assign ENVCFG_CBE = (PrivilegeModeW == P.M_MODE) ? 4'b1111 : - (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : SENVCFG_REGW[7:4]; + (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : + (MSENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]); + // FIOM presently doesn't do anything because Wally fences don't do anything assign ENVCFG_FIOM = (PrivilegeModeW == P.M_MODE) ? 1'b1 : - (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[0] : SENVCFG_REGW[0]; + (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[0] : + (MENVCFG_REGW[0] & SENVCFG_REGW[0]); + +if (((priv_mode != M) && (menvcfg.CBIE == 00)) || + ((priv_mode == U) && (senvcfg.CBIE == 00))) + { + + } // merge CSR Reads assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; From 6a88ac28e48173bbe5e5c1ffe8bd4763346ffbbb Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 02:01:40 -0700 Subject: [PATCH 30/54] Fixed csr typos --- src/privileged/csr.sv | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index c9cc88f3c..ccca40a00 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -294,18 +294,12 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign ENVCFG_PBMTE = MENVCFG_REGW[62]; // page-based memory types enable assign ENVCFG_CBE = (PrivilegeModeW == P.M_MODE) ? 4'b1111 : (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[7:4] : - (MSENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]); + (MENVCFG_REGW[7:4] & SENVCFG_REGW[7:4]); // FIOM presently doesn't do anything because Wally fences don't do anything assign ENVCFG_FIOM = (PrivilegeModeW == P.M_MODE) ? 1'b1 : (PrivilegeModeW == P.S_MODE | !P.S_SUPPORTED) ? MENVCFG_REGW[0] : (MENVCFG_REGW[0] & SENVCFG_REGW[0]); -if (((priv_mode != M) && (menvcfg.CBIE == 00)) || - ((priv_mode == U) && (senvcfg.CBIE == 00))) - { - - } - // merge CSR Reads assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM; flopenrc #(P.XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW); From a5c6ae1f78422688c409be230374e8e193945ade Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 09:35:05 -0700 Subject: [PATCH 31/54] Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions --- src/ieu/controller.sv | 26 +++++++++++++++++++++----- src/ieu/ieu.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 4 ++-- 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 55a2d7bac..d87a43b4c 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -62,7 +62,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE, // Bit manipulation instruction being executed output logic MDUActiveE, // Mul/Div instruction being executed - output logic CMOE, // Cache Management operation being executed + output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage @@ -83,6 +83,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic StoreStallD // Store (memory write) causes stall ); + logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage @@ -133,13 +134,14 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FLSFunctD; // Detect floating-point loads and stores logic JRFunctD; // detect jalr instruction logic FenceFunctD; // Detect fence instruction - logic CMOFunctD; + logic CMOFunctD; // Detect CMO instruction logic AFunctD, AMOFunctD; // Detect atomic instructions logic RWFunctD, MWFunctD; // detect RW/MW instructions logic PFunctD, CSRFunctD; // detect privileged / CSR instruction logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions + logic [3:0] CMOpD; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero // Extract fields assign OpD = InstrD[6:0]; @@ -349,14 +351,28 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign InvalidateICacheD = 0; assign FlushDCacheD = 0; end + + // Cache Management instructions + if (P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) begin:cmo + always_comb + if (CMOD) begin + CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero + CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean + CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush + CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval + end else + CMOpD = 4'b0000; // not a cbo instruction + end else begin:cmo + assign CMOpD = 4'b0000; // cbo instructions not supported + end // Decode stage pipeline control register flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(30) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOE, InstrValidE}); + flopenrc #(33) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index f930b1103..9b653001f 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -45,7 +45,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B output logic [4:0] RdE, // Destination register output logic MDUActiveE, // Mul/Div instruction being executed - output logic CMOE, // Cache management instruction being executed + output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU output logic [1:0] MemRWM, // Read/write control goes to LSU @@ -104,7 +104,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, - .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOE, + .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 563e4f987..a6b463d61 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -78,7 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic SquashSCW; logic MDUActiveE; // Mul/Div instruction being executed - logic CMOE; // Cache management instruction being executed + logic [3:0] CMOpE; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero logic [3:0] ENVCFG_CBE; // Cache block operation enables // floating point unit signals @@ -193,7 +193,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU From cc873171897d4a6d7f8c7910ebd0acc89db1c47b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 10:06:58 -0700 Subject: [PATCH 32/54] Added prefetch signals --- src/ieu/controller.sv | 43 +++++++++++++++++++++------------ src/ieu/ieu.sv | 3 ++- src/wally/wallypipelinedcore.sv | 3 ++- 3 files changed, 32 insertions(+), 17 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d87a43b4c..28d0eef27 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -63,6 +63,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic BMUActiveE, // Bit manipulation instruction being executed output logic MDUActiveE, // Mul/Div instruction being executed output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + output logic [2:0] PrefetchE, // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage @@ -142,6 +143,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic [2:0] ALUSelectD; // ALU Output selection mux control logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions logic [3:0] CMOpD; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + logic [2:0] PrefetchD; // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w // Extract fields assign OpD = InstrD[6:0]; @@ -353,26 +355,37 @@ module controller import cvw::*; #(parameter cvw_t P) ( end // Cache Management instructions - if (P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) begin:cmo - always_comb - if (CMOD) begin - CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero - CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean - CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush - CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval - end else - CMOpD = 4'b0000; // not a cbo instruction - end else begin:cmo - assign CMOpD = 4'b0000; // cbo instructions not supported + always_comb begin + CMOpD = 4'b0000; // default: not a cbo instruction + if ((P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) & CMOD) begin + CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero + CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean + CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush + CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval + end end - + + // Prefetch Hints + always_comb begin + PrefetchD = 3'b000; // default: not a prefetch hint + if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destiation x0 is hint for Prefetch + case (Rs2D) // which type of prefectch? + 5'b00000: PrefetchD = 3'b001; // prefetch.i + 5'b00001: PrefetchD = 3'b010; // prefetch.r + 5'b00011: PrefetchD = 3'b100; // prefetch.w + // default: not a prefetch hint + endcase + end + end + //assign AnyPrefetchD = |PrefetchD; + // Decode stage pipeline control register flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(33) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, InstrValidE}); + flopenrc #(36) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, PrefetchD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, PrefetchE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 9b653001f..fe8fb4ef3 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -46,6 +46,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( output logic [4:0] RdE, // Destination register output logic MDUActiveE, // Mul/Div instruction being executed output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + output logic [2:0] PrefetchE, // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU output logic [1:0] MemRWM, // Read/write control goes to LSU @@ -104,7 +105,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, - .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpE, + .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpE, .PrefetchE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index a6b463d61..438214d2a 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -79,6 +79,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic SquashSCW; logic MDUActiveE; // Mul/Div instruction being executed logic [3:0] CMOpE; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + logic [2:0] PrefetchE; // 1: prefetch.i, 2: prefetch.r, 4: prefetch.w logic [3:0] ENVCFG_CBE; // Cache block operation enables // floating point unit signals @@ -193,7 +194,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpE, .PrefetchE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU From e6ba362794df1b836c8123e6be6ade10651acf97 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 10:55:35 -0700 Subject: [PATCH 33/54] Added prefetch instructions; sent cbo instructions to LSU --- src/ieu/controller.sv | 40 +++++++++++++++++++-------------- src/ieu/datapath.sv | 2 +- src/ieu/extend.sv | 25 +++++++++++---------- src/ieu/ieu.sv | 7 +++--- src/lsu/lsu.sv | 8 +++++-- src/wally/wallypipelinedcore.sv | 10 ++++----- 6 files changed, 52 insertions(+), 40 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 28d0eef27..c543348e5 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -62,8 +62,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE, // Bit manipulation instruction being executed output logic MDUActiveE, // Mul/Div instruction being executed - output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero - output logic [2:0] PrefetchE, // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w + output logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + output logic IFUPrefetchE, // instruction prefetch + output logic LSUPrefetchM, // data prefetch // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage @@ -95,6 +96,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( // pipelined control signals logic RegWriteD, RegWriteE; // RegWrite (register will be written) logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file + logic [2:0] PreImmSrcD; // Immediate source format (before amending for prefetches) logic [1:0] MemRWD, MemRWE; // Store (write to memory) logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic BaseW64D; // W64 for Base instructions specifically @@ -142,8 +144,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions - logic [3:0] CMOpD; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero - logic [2:0] PrefetchD; // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w + logic [3:0] CMOpD, CMOpE; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + logic IFUPrefetchD; // instruction prefetch + logic LSUPrefetchD, LSUPrefetchE; // data prefetch // Extract fields assign OpD = InstrD[6:0]; @@ -284,7 +287,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. assign IllegalERegAdrD = P.E_SUPPORTED & P.ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; //assign IllegalBaseInstrD = 1'b0; - assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, + assign {BaseRegWriteD, PreImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, CMOD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; @@ -367,25 +370,28 @@ module controller import cvw::*; #(parameter cvw_t P) ( // Prefetch Hints always_comb begin - PrefetchD = 3'b000; // default: not a prefetch hint + // default: not a prefetch hint + IFUPrefetchD = 1'b0; + LSUPrefetchD = 1'b0; + ImmSrcD = PreImmSrcD; if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destiation x0 is hint for Prefetch - case (Rs2D) // which type of prefectch? - 5'b00000: PrefetchD = 3'b001; // prefetch.i - 5'b00001: PrefetchD = 3'b010; // prefetch.r - 5'b00011: PrefetchD = 3'b100; // prefetch.w + case (Rs2D) // which type of prefectch? Note: prefetch.r and .w are handled the same in Wally + 5'b00000: IFUPrefetchD = 1'b1; // prefetch.i + 5'b00001: LSUPrefetchD = 1'b1; // prefetch.r + 5'b00011: LSUPrefetchD = 1'b1; // prefetch.w // default: not a prefetch hint endcase + if (IFUPrefetchD | LSUPrefetchD) ImmSrcD = 3'b001; // use S-type immediate format for prefetches end end - //assign AnyPrefetchD = |PrefetchD; // Decode stage pipeline control register flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(36) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, PrefetchD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, PrefetchE, InstrValidE}); + flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE @@ -404,9 +410,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign IntDivE = MDUE & Funct3E[2]; // Integer division operation // Memory stage pipeline control register - flopenrc #(20) controlregM(clk, reset, FlushM, ~StallM, - {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE}, - {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM}); + flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM, + {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE}, + {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM}); // Writeback stage pipeline control register flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 799a25988..bb7638514 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -98,7 +98,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); - extend #(P.XLEN, P.A_SUPPORTED) ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD); + extend #(P) ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD); // Execute stage pipeline register and logic flopenrc #(P.XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E); diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index e0551e9dc..bcda43e0a 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -27,28 +27,29 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module extend #(parameter XLEN, A_SUPPORTED) ( - input logic [31:7] InstrD, // All instruction bits except opcode (lower 7 bits) - input logic [2:0] ImmSrcD, // Select what kind of extension to perform - output logic [XLEN-1:0] ImmExtD); // Extended immediate +module extend import cvw::*; #(parameter cvw_t P) ( + input logic [31:7] InstrD, // All instruction bits except opcode (lower 7 bits) + input logic [2:0] ImmSrcD, // Select what kind of extension to perform + output logic [P.XLEN-1:0] ImmExtD); // Extended immediate - localparam [XLEN-1:0] undefined = {(XLEN){1'bx}}; // could change to 0 after debug + localparam [P.XLEN-1:0] undefined = {(P.XLEN){1'bx}}; // could change to 0 after debug always_comb - case(ImmSrcD) + case (ImmSrcD) // I-type - 3'b000: ImmExtD = {{(XLEN-12){InstrD[31]}}, InstrD[31:20]}; + 3'b000: ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:20]}; // S-type (stores) - 3'b001: ImmExtD = {{(XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]}; + 3'b001: ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]}; // B-type (branches) - 3'b010: ImmExtD = {{(XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; + 3'b010: ImmExtD = {{(P.XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; // J-type (jal) - 3'b011: ImmExtD = {{(XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; + 3'b011: ImmExtD = {{(P.XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; // U-type (lui, auipc) - 3'b100: ImmExtD = {{(XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; + 3'b100: ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; // Store Conditional: zero offset - 3'b101: if (A_SUPPORTED) ImmExtD = 0; + 3'b101: if (P.A_SUPPORTED) ImmExtD = 0; else ImmExtD = undefined; default: ImmExtD = undefined; // undefined endcase + endmodule diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index fe8fb4ef3..2656b003d 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -45,8 +45,9 @@ module ieu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B output logic [4:0] RdE, // Destination register output logic MDUActiveE, // Mul/Div instruction being executed - output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero - output logic [2:0] PrefetchE, // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w + output logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + output logic IFUPrefetchE, // instruction prefetch + output logic LSUPrefetchM, // datata prefetch // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU output logic [1:0] MemRWM, // Read/write control goes to LSU @@ -105,7 +106,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, - .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpE, .PrefetchE, + .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 9c0d00543..9fda87cd0 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -39,6 +39,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( input logic [6:0] Funct7M, // Atomic memory operation function input logic [1:0] AtomicM, // Atomic memory operation input logic FlushDCacheM, // Flush D cache to next level of memory + input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + input logic LSUPrefetchM, // Prefetch output logic CommittedM, // Delay interrupts while memory operation in flight output logic SquashSCW, // Store conditional failed disable write to GPR output logic DCacheMiss, // D cache miss for performance counters @@ -224,7 +226,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic [1:0] DTIMMemRWM; // The DTIM uses untranslated addresses, so it is not compatible with virtual memory. - mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr); + mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr); assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0; // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. // **** create config to support DTIM with floating point. @@ -258,8 +260,10 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM; assign CacheRWM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0; assign CacheAtomicM = CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSUAtomicM : '0; - assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW); + assign FlushDCache = FlushDCacheM & ~(IgnoreRequestTLB | SelHPTW); + // *** need RT to add support for CMOpM and LSUPrefetchM (DH 7/2/23) + // *** prefetch can just act as a read operation cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 438214d2a..793ea5777 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -78,9 +78,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic SquashSCW; logic MDUActiveE; // Mul/Div instruction being executed - logic [3:0] CMOpE; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero - logic [2:0] PrefetchE; // 1: prefetch.i, 2: prefetch.r, 4: prefetch.w - logic [3:0] ENVCFG_CBE; // Cache block operation enables + logic [3:0] ENVCFG_CBE; // Cache Block operation enables + logic [3:0] CMOpM; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero + logic IFUPrefetchE, LSUPrefetchM; // instruction / data prefetch hints // floating point unit signals logic [2:0] FRM_REGW; @@ -194,7 +194,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpE, .PrefetchE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU @@ -218,7 +218,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM, .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM, - .ReadDataW, .FlushDCacheM, + .ReadDataW, .FlushDCacheM, .CMOpM, .LSUPrefetchM, // connected to ahb (all stay the same) .LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY, From 4c921fc79728b68806acf46558378a1280893e55 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 13:29:27 -0700 Subject: [PATCH 34/54] Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder --- testbench/common/instrNameDecTB.sv | 16 ++++++++-- testbench/common/ramxdetector.sv | 45 +++++++++++++++++++++++++++++ testbench/common/riscvassertions.sv | 3 ++ testbench/testbench.sv | 22 ++++++++------ 4 files changed, 74 insertions(+), 12 deletions(-) create mode 100644 testbench/common/ramxdetector.sv diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index 1529de5e6..8f6fbe869 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -30,13 +30,14 @@ module instrNameDecTB( logic [2:0] funct3; logic [6:0] funct7; logic [11:0] imm; - logic [4:0] rs2; + logic [4:0] rs2, rd; assign op = instr[6:0]; assign funct3 = instr[14:12]; assign funct7 = instr[31:25]; assign imm = instr[31:20]; assign rs2 = instr[24:20]; + assign rd = instr[11:7]; // it would be nice to add the operands to the name // create another variable called decoded @@ -77,7 +78,10 @@ module instrNameDecTB( else if (funct7[6:1] == 6'b010010) name = "BEXTI"; else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B"; else name = "ILLEGAL"; - 10'b0010011_110: name = "ORI"; + 10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I"; + else if (rd == 0 & rs2 == 1) name = "PREFETCH.R"; + else if (rd == 0 & rs2 == 3) name = "PREFETCH.W"; + else name = "ORI"; 10'b0010011_111: name = "ANDI"; 10'b0010111_???: name = "AUIPC"; 10'b0100011_000: name = "SB"; @@ -215,7 +219,13 @@ module instrNameDecTB( else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D"; else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D"; else name = "ILLEGAL"; - 10'b0001111_???: name = "FENCE"; + 10'b0001111_000: name = "FENCE"; + 10'b0001111_001: name = "FENCE.I"; + 10'b0001111_010: if (instr[31:20] == 12'd0) name = "CBO.INVAL"; + else if (instr[31:20] == 12'd1) name = "CBO.CLEAN"; + else if (instr[31:20] == 12'd2) name = "CBO.FLUSH"; + else if (instr[31:20] == 12'd4) name = "CBO.ZERO"; + else name = "ILLEGAL"; 10'b1000011_???: name = "FMADD"; 10'b1000111_???: name = "FMSUB"; 10'b1001011_???: name = "FNMSUB"; diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv new file mode 100644 index 000000000..987bbefea --- /dev/null +++ b/testbench/common/ramxdetector.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// ramxdetector.sv +// +// Written: David_Harris@hmc.edu +// Modified: 2 July 2023 +// +// Purpose: Detects if the processor is attempting to read unitialized RAM +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ramxdetector #(parameter XLEN, LLEN) ( + input logic clk, + input logic MemReadM, + input logic LSULoadAccessFaultM, + input logic [LLEN-1:0] ReadDataM, + input logic [XLEN-1:0] PCM, + input logic [31:0] InstrM, + input logic [XLEN-1:0] IEUAdrM, + input string InstrMName +); + + always_ff @(posedge clk) + if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin + $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests."); + $display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM); + //$stop; + end + +endmodule diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 50577c37d..d1007ec41 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -58,6 +58,9 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled"); assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED"); assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED"); + assert ((P.ZICBOM_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOM required DCACHE_SUPPORTED"); + assert ((P.ZICBOZ_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOZ required DCACHE_SUPPORTED"); + assert ((P.ZICBOP_SUPPORTED == 0) || (P.DCACHE_SUPPORTED == 1)) else $error("ZICBOP required DCACHE_SUPPORTED"); end endmodule diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4cab1a105..a41d61217 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -409,7 +409,20 @@ module testbench; // Support logic //////////////////////////////////////////////////////////////////////////////// + // Track names of instructions + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); + instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, + dut.core.ifu.InstrRawF[31:0], + dut.core.ifu.InstrD, dut.core.ifu.InstrE, + dut.core.ifu.InstrM, InstrW, + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + // watch for problems such as lockup, reading unitialized memory, bad configs watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck + ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, + dut.core.ifu.PCM, dut.core.ifu.InstrM, dut.core.lsu.IEUAdrM, InstrMName); riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename); @@ -420,15 +433,6 @@ module testbench; .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end - // Track names of instructions - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - logic [31:0] InstrW; - flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.InstrRawF[31:0], - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - dut.core.ifu.InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // Termination condition // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed From 4f07d89d741d7bd25721511825a05c07bb78431b Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 4 Jul 2023 11:27:36 -0700 Subject: [PATCH 35/54] fixed spacing in fdivsqrt --- src/fpu/fdivsqrt/fdivsqrt.sv | 44 ++++++++++++++-------------- src/fpu/fdivsqrt/fdivsqrtcycles.sv | 4 +-- src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 4 +-- src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 5 ++-- src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 4 +-- src/fpu/fdivsqrt/fdivsqrtfsm.sv | 26 ++++++++-------- src/fpu/fdivsqrt/fdivsqrtiter.sv | 16 +++++----- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 18 ++++++------ src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 30 +++++++++---------- 9 files changed, 75 insertions(+), 76 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 1a1b893e0..9112da9d1 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -27,24 +27,24 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrt import cvw::*; #(parameter cvw_t P) ( - input logic clk, - input logic reset, + input logic clk, + input logic reset, input logic [P.FMTBITS-1:0] FmtE, - input logic XsE, + input logic XsE, input logic [P.NF:0] XmE, YmE, input logic [P.NE-1:0] XeE, YeE, - input logic XInfE, YInfE, - input logic XZeroE, YZeroE, - input logic XNaNE, YNaNE, - input logic FDivStartE, IDivStartE, - input logic StallM, - input logic FlushE, - input logic SqrtE, SqrtM, + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic FDivStartE, IDivStartE, + input logic StallM, + input logic FlushE, + input logic SqrtE, SqrtM, input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B - input logic [2:0] Funct3E, Funct3M, - input logic IntDivE, W64E, - output logic DivStickyM, - output logic FDivBusyE, IFDivStartE, FDivDoneE, + input logic [2:0] Funct3E, Funct3M, + input logic IntDivE, W64E, + output logic DivStickyM, + output logic FDivBusyE, IFDivStartE, FDivDoneE, output logic [P.NE+1:0] QeM, output logic [P.DIVb:0] QmM, output logic [P.XLEN-1:0] FIntDivResultM @@ -58,19 +58,19 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb+3:0] D; // Iterator Divisor logic [P.DIVb:0] FirstU, FirstUM; // Intermediate result values logic [P.DIVb+1:0] FirstC; // Step tracker - logic Firstun; // Quotient selection - logic WZeroE; // Early termination flag + logic Firstun; // Quotient selection + logic WZeroE; // Early termination flag logic [P.DURLEN-1:0] CyclesE; // FSM cycles - logic SpecialCaseM; // Divide by zero, square root of negative, etc. - logic DivStartE; // Enable signal for flops during stall + logic SpecialCaseM; // Divide by zero, square root of negative, etc. + logic DivStartE; // Enable signal for flops during stall // Integer div/rem signals - logic BZeroM; // Denominator is zero - logic IntDivM; // Integer operation + logic BZeroM; // Denominator is zero + logic IntDivM; // Integer operation logic [P.DIVBLEN:0] nM, mM; // Shift amounts - logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor + logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor - logic ISpecialCaseE; // Integer div/remainder special cases + logic ISpecialCaseE; // Integer div/remainder special cases fdivsqrtpreproc #(P) fdivsqrtpreproc( // Preprocessor .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index c7aea4588..09b17871a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -28,8 +28,8 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) ( input logic [P.FMTBITS-1:0] FmtE, - input logic SqrtE, - input logic IntDivE, + input logic SqrtE, + input logic IntDivE, input logic [P.DIVBLEN:0] nE, output logic [P.DURLEN-1:0] CyclesE ); diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index adc1d6bf5..5531276df 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -29,8 +29,8 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) ( input logic [P.FMTBITS-1:0] Fmt, input logic [P.NE-1:0] Xe, Ye, - input logic Sqrt, - input logic XZero, + input logic Sqrt, + input logic XZero, input logic [P.DIVBLEN:0] ell, m, output logic [P.NE+1:0] Qe ); diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index 73afeb527..990e3f19f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -27,18 +27,17 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrtfgen2 import cvw::*; #(parameter cvw_t P) ( - input logic up, uz, + input logic up, uz, input logic [P.DIVb+3:0] C, U, UM, output logic [P.DIVb+3:0] F ); - logic [P.DIVb+3:0] FP, FN, FZ; + logic [P.DIVb+3:0] FP, FN, FZ; // Generate for both positive and negative bits assign FP = ~(U << 1) & C; assign FN = (UM << 1) | (C & ~(C << 2)); assign FZ = '0; - always_comb // Choose which adder input will be used if (up) F = FP; else if (uz) F = FZ; diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index e0f19957e..fc648f5bd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -27,11 +27,11 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrtfgen4 import cvw::*; #(parameter cvw_t P) ( - input logic [3:0] udigit, + input logic [3:0] udigit, input logic [P.DIVb+3:0] C, U, UM, output logic [P.DIVb+3:0] F ); - logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2; + logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2; // Generate for both positive and negative bits assign F2 = (~U << 2) & (C << 2); diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index a10c9f6c9..a727e5536 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -27,20 +27,20 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) ( - input logic clk, reset, - input logic XInfE, YInfE, - input logic XZeroE, YZeroE, - input logic XNaNE, YNaNE, - input logic FDivStartE, IDivStartE, - input logic XsE, WZeroE, - input logic SqrtE, - input logic StallM, FlushE, - input logic IntDivE, - input logic ISpecialCaseE, + input logic clk, reset, + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic FDivStartE, IDivStartE, + input logic XsE, WZeroE, + input logic SqrtE, + input logic StallM, FlushE, + input logic IntDivE, + input logic ISpecialCaseE, input logic [P.DURLEN-1:0] CyclesE, - output logic IFDivStartE, - output logic FDivBusyE, FDivDoneE, - output logic SpecialCaseM + output logic IFDivStartE, + output logic FDivBusyE, FDivDoneE, + output logic SpecialCaseM ); typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 0d9600ad5..ede0a23cc 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -27,14 +27,14 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( - input logic clk, - input logic IFDivStartE, - input logic FDivBusyE, - input logic SqrtE, + input logic clk, + input logic IFDivStartE, + input logic FDivBusyE, + input logic SqrtE, input logic [P.DIVb+3:0] X, D, output logic [P.DIVb:0] FirstU, FirstUM, output logic [P.DIVb+1:0] FirstC, - output logic Firstun, + output logic Firstun, output logic [P.DIVb+3:0] FirstWS, FirstWC ); @@ -48,11 +48,11 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb:0] UNext[P.DIVCOPIES-1:0]; // U1.b logic [P.DIVb:0] UMNext[P.DIVCOPIES-1:0]; // U1.b logic [P.DIVb+1:0] C[P.DIVCOPIES:0]; // Q2.b - logic [P.DIVb+1:0] initC; // Q2.b + logic [P.DIVb+1:0] initC; // Q2.b logic [P.DIVCOPIES-1:0] un; - logic [P.DIVb+3:0] WSN, WCN; // Q4.b - logic [P.DIVb+3:0] DBar, D2, DBar2; // Q4.b + logic [P.DIVb+3:0] WSN, WCN; // Q4.b + logic [P.DIVb+3:0] DBar, D2, DBar2; // Q4.b logic [P.DIVb+1:0] NextC; logic [P.DIVb:0] UMux, UMMux; logic [P.DIVb:0] initU, initUM; diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index ad4742421..19856e932 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -27,27 +27,27 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( - input logic clk, reset, - input logic StallM, + input logic clk, reset, + input logic StallM, input logic [P.DIVb+3:0] WS, WC, input logic [P.DIVb+3:0] D, input logic [P.DIVb:0] FirstU, FirstUM, input logic [P.DIVb+1:0] FirstC, - input logic SqrtE, - input logic Firstun, SqrtM, SpecialCaseM, NegQuotM, + input logic SqrtE, + input logic Firstun, SqrtM, SpecialCaseM, NegQuotM, input logic [P.XLEN-1:0] AM, - input logic RemOpM, ALTBM, BZeroM, AsM, W64M, + input logic RemOpM, ALTBM, BZeroM, AsM, W64M, input logic [P.DIVBLEN:0] nM, mM, output logic [P.DIVb:0] QmM, - output logic WZeroE, - output logic DivStickyM, + output logic WZeroE, + output logic DivStickyM, output logic [P.XLEN-1:0] FIntDivResultM ); logic [P.DIVb+3:0] W, Sum; logic [P.DIVb:0] PreQmM; - logic NegStickyM; - logic weq0E, WZeroM; + logic NegStickyM; + logic weq0E, WZeroM; logic [P.XLEN-1:0] IntDivResultM; ////////////////////////// diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 2d50b9299..ef14bda78 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -27,24 +27,24 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( - input logic clk, - input logic IFDivStartE, + input logic clk, + input logic IFDivStartE, input logic [P.NF:0] Xm, Ym, input logic [P.NE-1:0] Xe, Ye, input logic [P.FMTBITS-1:0] FmtE, - input logic SqrtE, - input logic XZeroE, - input logic [2:0] Funct3E, + input logic SqrtE, + input logic XZeroE, + input logic [2:0] Funct3E, output logic [P.NE+1:0] QeM, output logic [P.DIVb+3:0] X, D, // Int-specific input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B - input logic IntDivE, W64E, - output logic ISpecialCaseE, + input logic IntDivE, W64E, + output logic ISpecialCaseE, output logic [P.DURLEN-1:0] CyclesE, output logic [P.DIVBLEN:0] nM, mM, - output logic NegQuotM, ALTBM, IntDivM, W64M, - output logic AsM, BZeroM, + output logic NegQuotM, ALTBM, IntDivM, W64M, + output logic AsM, BZeroM, output logic [P.XLEN-1:0] AM ); @@ -54,11 +54,11 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic [P.NE+1:0] QeE; // Quotient Exponent (FP only) logic [P.DIVb-1:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input logic [P.DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs - logic NumerZeroE; // Numerator is zero (X or A) - logic AZeroE, BZeroE; // A or B is Zero for integer division - logic SignedDivE; // signed division - logic NegQuotE; // Integer quotient is negative - logic AsE, BsE; // Signs of integer inputs + logic NumerZeroE; // Numerator is zero (X or A) + logic AZeroE, BZeroE; // A or B is Zero for integer division + logic SignedDivE; // signed division + logic NegQuotE; // Integer quotient is negative + logic AsE, BsE; // Signs of integer inputs logic [P.XLEN-1:0] AE; // input A after W64 adjustment logic ALTBE; @@ -166,7 +166,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( // Sqrt is initialized on step one as R(X-1), so depends on Radix mux2 #(P.DIVb+1) sqrtxmux({~XZeroE, Xfract}, {1'b0, ~XZeroE, Xfract[P.DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX); - if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX}; + if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX}; else assign SqrtX = {2'b11, PreSqrtX, 1'b0}; mux2 #(P.DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX); From 34ce25ca819b4d2bd3d605ba7dba48fc5233a0da Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 4 Jul 2023 11:34:07 -0700 Subject: [PATCH 36/54] Commented SVADU requirements for wally32priv mmu tests --- testbench/tests.vh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index f38f28056..116d39424 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -2031,8 +2031,8 @@ string arch64zbs[] = '{ "rv32i_m/privilege/src/WALLY-mie-01.S", "rv32i_m/privilege/src/WALLY-minfo-01.S", "rv32i_m/privilege/src/WALLY-misa-01.S", -// "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S", - "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S", + // "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S", // run this if SVADU_SUPPORTED = 0 + "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S", // run this if SVADU_SUPPORTED = 1 "rv32i_m/privilege/src/WALLY-mtvec-01.S", "rv32i_m/privilege/src/WALLY-pma-01.S", "rv32i_m/privilege/src/WALLY-pmp-01.S", From 19efc4eda8cd5797d81bd45b8b5a859609c6c31d Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 4 Jul 2023 11:34:58 -0700 Subject: [PATCH 37/54] Fixed comment typo --- src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index ede0a23cc..1d40e8d9a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -63,7 +63,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( // Otherwise, the divisor is retained and the residual and result // are fed back for the next iteration. - // Residual WS/SC registers/initializaiton mux + // Residual WS/SC registers/initialization mux mux2 #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN); mux2 #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN); flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]); From c0fdd3fbca32230c2f00a3f439aaf14badc674a7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Jul 2023 17:30:55 -0500 Subject: [PATCH 38/54] Partially solved fpga boot. --- src/uncore/plic_apb.sv | 82 ++++++++++++++++++++++-------------------- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 11c06153d..0014bdd72 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -31,7 +31,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define N P.PLIC_NUM_SRC // number of interrupt sources // does not include source 0, which does not connect to anything according to spec // up to 63 sources supported; in the future, allow up to 1023 sources @@ -59,19 +58,20 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( logic [31:0] Din, Dout; // context-independent signals - logic [`N:1] requests; - logic [`N:1][2:0] intPriority; - logic [`N:1] intInProgress, intPending, nextIntPending; + logic [P.PLIC_NUM_SRC:1] requests; + logic [P.PLIC_NUM_SRC:1][2:0] intPriority; + logic [P.PLIC_NUM_SRC:1] intInProgress, intPending, nextIntPending; // context-dependent signals logic [`C-1:0][2:0] intThreshold; - logic [`C-1:0][`N:1] intEn; + logic [`C-1:0][P.PLIC_NUM_SRC:1] intEn; logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources - logic [`C-1:0][7:1][`N:1] irqMatrix; + logic [`C-1:0][7:1][P.PLIC_NUM_SRC:1] irqMatrix; logic [`C-1:0][7:1] priorities_with_irqs; logic [`C-1:0][7:1] max_priority_with_irqs; - logic [`C-1:0][`N:1] irqs_at_max_priority; + logic [`C-1:0][P.PLIC_NUM_SRC:1] irqs_at_max_priority; logic [`C-1:0][7:1] threshMask; + logic [P.PLIC_NUM_SRC-1:0] One; // ======= // AHB I/O @@ -81,6 +81,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( assign memread = ~PWRITE & PSEL; // read at start of access phase. PENABLE hasn't set up before this assign PREADY = 1'b1; // PLIC never takes >1 cycle to respond assign entry = {PADDR[23:2],2'b0}; + assign One[P.PLIC_NUM_SRC-1:1] = '0; assign One[0] = 1'b1; // Vivado does not like this as a single assignment. // account for subword read/write circuitry // -- Note PLIC registers are 32 bits no matter what; access them with LW SW. @@ -92,7 +93,12 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( assign Din = PWDATA[31:0]; end - if (P.PLIC_NUM_SRC_LT_32) `define PLIC_NUM_SRC_LT_32 + // *** RT: 05 July 2023: BUG BUG BUG. PLIC_NUM_SRC_LT_32 is undefined after parameterization + // the FPGA does work the following code. For now I'm leaving the `define undefined but this + // means the code is only valid for 33 to 64 interrupt sources. In general this needs to be + // rethought for a more generalized implementation. + //if (P.PLIC_NUM_SRC_LT_32) `define PLIC_NUM_SRC_LT_32 + //`define PLIC_NUM_SRC_LT_32 // ================== // Register Interface @@ -101,29 +107,29 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( always @(posedge PCLK) begin // resetting if (~PRESETn) begin - intPriority <= #1 {`N{3'b0}}; - intEn <= #1 {2*`N{1'b0}}; - intThreshold <= #1 {2{3'b0}}; - intInProgress <= #1 {`N{1'b0}}; + intPriority <= #1 '0; + intEn <= #1 '0; + intThreshold <= #1 '0; + intInProgress <= #1 '0; // writing end else begin if (memwrite) casez(entry) 24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0]; `ifdef PLIC_NUM_SRC_LT_32 // eventually switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources - 24'h002000: intEn[0][`N:1] <= #1 Din[`N:1]; - 24'h002080: intEn[1][`N:1] <= #1 Din[`N:1]; + 24'h002000: intEn[0][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; + 24'h002080: intEn[1][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; `endif `ifndef PLIC_NUM_SRC_LT_32 24'h002000: intEn[0][31:1] <= #1 Din[31:1]; - 24'h002004: intEn[0][`N:32] <= #1 Din[31:0]; + 24'h002004: intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; 24'h002080: intEn[1][31:1] <= #1 Din[31:1]; - 24'h002084: intEn[1][`N:32] <= #1 Din[31:0]; + 24'h002084: intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; `endif 24'h200000: intThreshold[0] <= #1 Din[2:0]; - 24'h200004: intInProgress <= #1 intInProgress & ~({{`N-1{1'b0}}, 1'b1} << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h200004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 24'h201000: intThreshold[1] <= #1 Din[2:0]; - 24'h201004: intInProgress <= #1 intInProgress & ~({{`N-1{1'b0}}, 1'b1} << (Din[5:0]-1)); // lower "InProgress" to signify completion + 24'h201004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase // Read synchronously because a read can have side effect of changing intInProgress if (memread) begin @@ -131,27 +137,27 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( 24'h000000: Dout <= #1 32'b0; // there is no intPriority[0] 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; `ifdef PLIC_NUM_SRC_LT_32 - 24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0}; - 24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0}; - 24'h002080: Dout <= #1 {{(31-`N){1'b0}},intEn[1],1'b0}; + 24'h001000: Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intPending,1'b0}; + 24'h002000: Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[0],1'b0}; + 24'h002080: Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[1],1'b0}; `endif `ifndef PLIC_NUM_SRC_LT_32 24'h001000: Dout <= #1 {intPending[31:1],1'b0}; - 24'h001004: Dout <= #1 {{(63-`N){1'b0}},intPending[`N:32]}; + 24'h001004: Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; 24'h002000: Dout <= #1 {intEn[0][31:1],1'b0}; - 24'h002004: Dout <= #1 {{(63-`N){1'b0}},intEn[0][`N:32]}; + 24'h002004: Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; 24'h002080: Dout <= #1 {intEn[0][31:1],1'b0}; - 24'h002084: Dout <= #1 {{(63-`N){1'b0}},intEn[1][`N:32]}; + 24'h002084: Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]}; `endif 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; 24'h200004: begin Dout <= #1 {26'b0,intClaim[0]}; - intInProgress <= #1 intInProgress | ({{`N-1{1'b0}}, 1'b1} << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed + intInProgress <= #1 intInProgress | (One << (intClaim[0]-1)); // claimed requests are currently in progress of being serviced until they are completed end 24'h201000: Dout <= #1 {29'b0,intThreshold[1]}; 24'h201004: begin Dout <= #1 {26'b0,intClaim[1]}; - intInProgress <= #1 intInProgress | ({{`N-1{1'b0}}, 1'b1} << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed + intInProgress <= #1 intInProgress | (One << (intClaim[1]-1)); // claimed requests are currently in progress of being serviced until they are completed end default: Dout <= #1 32'h0; // invalid access endcase @@ -161,14 +167,14 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // connect sources to requests always_comb begin - requests = {`N{1'b0}}; + requests = {P.PLIC_NUM_SRC{1'b0}}; if(P.PLIC_GPIO_ID != 0) requests[P.PLIC_GPIO_ID] = GPIOIntr; if(P.PLIC_UART_ID != 0) requests[P.PLIC_UART_ID] = UARTIntr; end // pending interrupt request assign nextIntPending = (intPending | requests) & ~intInProgress; - flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending); + flopr #(P.PLIC_NUM_SRC) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending); // context-dependent signals genvar ctx; @@ -181,7 +187,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // ("active" meaning it is enabled in context and is pending) genvar src, pri; for (pri=1; pri<=7; pri++) begin - for (src=1; src<=`N; src++) begin + for (src=1; src<=P.PLIC_NUM_SRC; src++) begin assign irqMatrix[ctx][pri][src] = (intPriority[src]==pri) & intPending[src] & intEn[ctx][src]; end end @@ -210,14 +216,14 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // of the sources at the highest priority level that has active requests, // which sources have active requests? - assign irqs_at_max_priority[ctx][`N:1] = - ({`N{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) | - ({`N{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) | - ({`N{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) | - ({`N{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) | - ({`N{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) | - ({`N{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) | - ({`N{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]); + assign irqs_at_max_priority[ctx][P.PLIC_NUM_SRC:1] = + ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][7]}} & irqMatrix[ctx][7]) | + ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][6]}} & irqMatrix[ctx][6]) | + ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][5]}} & irqMatrix[ctx][5]) | + ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][4]}} & irqMatrix[ctx][4]) | + ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][3]}} & irqMatrix[ctx][3]) | + ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][2]}} & irqMatrix[ctx][2]) | + ({P.PLIC_NUM_SRC{max_priority_with_irqs[ctx][1]}} & irqMatrix[ctx][1]); // of the sources at the highest priority level that has active requests, // choose the source with the lowest source ID to be the most urgent @@ -225,7 +231,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( integer k; always_comb begin intClaim[ctx] = 6'b0; - for (k=`N; k>0; k--) begin + for (k=P.PLIC_NUM_SRC; k>0; k--) begin if (irqs_at_max_priority[ctx][k]) intClaim[ctx] = k[5:0]; end end From 930aed08989eb26cada2dee4816bfd89837350d9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Jul 2023 17:47:38 -0500 Subject: [PATCH 39/54] closer, but the wally32/64priv tests are failing. --- src/uncore/plic_apb.sv | 43 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 0014bdd72..7de757179 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -116,16 +116,14 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( if (memwrite) casez(entry) 24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0]; - `ifdef PLIC_NUM_SRC_LT_32 // eventually switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources - 24'h002000: intEn[0][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; - 24'h002080: intEn[1][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; - `endif - `ifndef PLIC_NUM_SRC_LT_32 - 24'h002000: intEn[0][31:1] <= #1 Din[31:1]; - 24'h002004: intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; - 24'h002080: intEn[1][31:1] <= #1 Din[31:1]; - 24'h002084: intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; - `endif + 24'h002000: begin if (P.PLIC_NUM_SRC < 32) intEn[0][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; + else intEn[0][31:1] <= #1 Din[31:1]; + end + 24'h002080: begin if (P.PLIC_NUM_SRC < 32) intEn[1][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; + else intEn[1][31:1] <= #1 Din[31:1]; + end + 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[31:0]; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[31:0]; 24'h200000: intThreshold[0] <= #1 Din[2:0]; 24'h200004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 24'h201000: intThreshold[1] <= #1 Din[2:0]; @@ -136,19 +134,18 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( casez(entry) 24'h000000: Dout <= #1 32'b0; // there is no intPriority[0] 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; - `ifdef PLIC_NUM_SRC_LT_32 - 24'h001000: Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intPending,1'b0}; - 24'h002000: Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[0],1'b0}; - 24'h002080: Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[1],1'b0}; - `endif - `ifndef PLIC_NUM_SRC_LT_32 - 24'h001000: Dout <= #1 {intPending[31:1],1'b0}; - 24'h001004: Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; - 24'h002000: Dout <= #1 {intEn[0][31:1],1'b0}; - 24'h002004: Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; - 24'h002080: Dout <= #1 {intEn[0][31:1],1'b0}; - 24'h002084: Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]}; - `endif + 24'h001000: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intPending,1'b0}; + else Dout <= #1 {intPending[31:1],1'b0}; + end + 24'h002000: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[0],1'b0}; + else Dout <= #1 {intEn[0][31:1],1'b0}; + end + 24'h002080: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[1],1'b0}; + else Dout <= #1 {intEn[0][31:1],1'b0}; + end + 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; + 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]}; 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; 24'h200004: begin Dout <= #1 {26'b0,intClaim[0]}; From ba9d5287d9634182ed643e70f78df0477856a5c2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 6 Jul 2023 11:53:34 -0500 Subject: [PATCH 40/54] This is at least functionally correct, but has verilator lint issues. --- src/uncore/plic_apb.sv | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 7de757179..cbfdc63ba 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -103,6 +103,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // ================== // Register Interface // ================== + localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 32; always @(posedge PCLK) begin // resetting @@ -122,6 +123,10 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( 24'h002080: begin if (P.PLIC_NUM_SRC < 32) intEn[1][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; else intEn[1][31:1] <= #1 Din[31:1]; end +/* -----\/----- EXCLUDED -----\/----- + 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32-1:1] <= #1 Din[PLIC_NUM_SRC_MIN_32-1:1]; + 24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32-1:1] <= #1 Din[PLIC_NUM_SRC_MIN_32-1:1]; + -----/\----- EXCLUDED -----/\----- */ 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[31:0]; 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[31:0]; 24'h200000: intThreshold[0] <= #1 Din[2:0]; @@ -135,16 +140,22 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( 24'h000000: Dout <= #1 32'b0; // there is no intPriority[0] 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; 24'h001000: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intPending,1'b0}; - else Dout <= #1 {intPending[31:1],1'b0}; - end + else Dout <= #1 {intPending[31:1],1'b0}; + end +// 24'h001000: Dout <= #1 {{(32-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32-1:1],1'b0}; + + 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; + 24'h002000: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[0],1'b0}; else Dout <= #1 {intEn[0][31:1],1'b0}; end +// 24'h002000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; + 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; + + 24'h002080: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[1],1'b0}; else Dout <= #1 {intEn[0][31:1],1'b0}; end - 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; - 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]}; 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; 24'h200004: begin From 18278b7f4dd10c53b6861b6d4602d2730e0ee2e6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 6 Jul 2023 14:07:37 -0500 Subject: [PATCH 41/54] It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga. --- src/uncore/plic_apb.sv | 47 +++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index cbfdc63ba..252114ce1 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -103,7 +103,8 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // ================== // Register Interface // ================== - localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 32; + localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31; + localparam PLIC_NUM_SRC_MIN_64 = P.PLIC_NUM_SRC < 64 ? P.PLIC_NUM_SRC : 63; always @(posedge PCLK) begin // resetting @@ -117,18 +118,14 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( if (memwrite) casez(entry) 24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0]; - 24'h002000: begin if (P.PLIC_NUM_SRC < 32) intEn[0][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; - else intEn[0][31:1] <= #1 Din[31:1]; - end - 24'h002080: begin if (P.PLIC_NUM_SRC < 32) intEn[1][P.PLIC_NUM_SRC:1] <= #1 Din[P.PLIC_NUM_SRC:1]; - else intEn[1][31:1] <= #1 Din[31:1]; - end -/* -----\/----- EXCLUDED -----\/----- - 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32-1:1] <= #1 Din[PLIC_NUM_SRC_MIN_32-1:1]; - 24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32-1:1] <= #1 Din[PLIC_NUM_SRC_MIN_32-1:1]; - -----/\----- EXCLUDED -----/\----- */ - 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[31:0]; - 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[31:0]; + 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1]; + 24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1]; + + // verilator lint_off SELRANGE + // *** RT: Long term we want to factor out these variable number of registers as a generate loop + 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; + // verilator lint_on SELRANGE 24'h200000: intThreshold[0] <= #1 Din[2:0]; 24'h200004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 24'h201000: intThreshold[1] <= #1 Din[2:0]; @@ -139,24 +136,22 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( casez(entry) 24'h000000: Dout <= #1 32'b0; // there is no intPriority[0] 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; - 24'h001000: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intPending,1'b0}; - else Dout <= #1 {intPending[31:1],1'b0}; - end -// 24'h001000: Dout <= #1 {{(32-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32-1:1],1'b0}; + 24'h001000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0}; + 24'h002000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; + // verilator lint_off SELRANGE + // verilator lint_off WIDTHTRUNC 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; - - 24'h002000: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[0],1'b0}; - else Dout <= #1 {intEn[0][31:1],1'b0}; - end -// 24'h002000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; + // verilator lint_on SELRANGE + // verilator lint_on WIDTHTRUNC - - 24'h002080: begin if (P.PLIC_NUM_SRC < 32) Dout <= #1 {{(31-P.PLIC_NUM_SRC){1'b0}},intEn[1],1'b0}; - else Dout <= #1 {intEn[0][31:1],1'b0}; - end + 24'h002080: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0}; + // verilator lint_off SELRANGE + // verilator lint_off WIDTHTRUNC 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]}; + // verilator lint_on SELRANGE + // verilator lint_on WIDTHTRUNC 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; 24'h200004: begin Dout <= #1 {26'b0,intClaim[0]}; From 29e62f05a445094e976304d8dc435dd6eb57dc1c Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 6 Jul 2023 12:40:53 -0700 Subject: [PATCH 42/54] Removed MTINST, which is not used in a system without a hypervisor --- src/privileged/csrm.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index fd2496c44..d77ed5175 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -82,7 +82,6 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam MCAUSE = 12'h342; localparam MTVAL = 12'h343; localparam MIP = 12'h344; - localparam MTINST = 12'h34A; localparam PMPCFG0 = 12'h3A0; // .. up to 15 more at consecutive addresses localparam PMPADDR0 = 12'h3B0; @@ -229,7 +228,6 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MEPC: CSRMReadValM = MEPC_REGW; MCAUSE: CSRMReadValM = MCAUSE_REGW; MTVAL: CSRMReadValM = MTVAL_REGW; - MTINST: CSRMReadValM = 0; // implemented as trivial zero MCOUNTEREN: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW}; MENVCFG: CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0]; MENVCFGH: CSRMReadValM = MENVCFGH_REGW; From 74a573cedd6483b48179d6850fdd1d5059276c3d Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 6 Jul 2023 12:41:46 -0700 Subject: [PATCH 43/54] Removed outdated commment about endianness --- src/privileged/csrsr.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 55db35f63..f474627f8 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -54,7 +54,6 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( // STATUS REGISTER FIELD // See Privileged Spec Section 3.1.6 // Lower privilege status registers are a subset of the full status register - // *** consider adding MBE, SBE, UBE fields, parameterized to be fixed or adjustable if (P.XLEN==64) begin: csrsr64 // RV64 assign MSTATUS_REGW = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, From dc50ddd75eda5a60eccce006209131a5359c8503 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 6 Jul 2023 14:57:07 -0500 Subject: [PATCH 44/54] Removed unused parameter. --- src/uncore/plic_apb.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index 252114ce1..af7845f0a 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -104,7 +104,6 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // Register Interface // ================== localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31; - localparam PLIC_NUM_SRC_MIN_64 = P.PLIC_NUM_SRC < 64 ? P.PLIC_NUM_SRC : 63; always @(posedge PCLK) begin // resetting From 40b2f7ff9c98082bc05ac22bd4eae63df0c7d0e3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 6 Jul 2023 15:24:26 -0500 Subject: [PATCH 45/54] Updated comments. --- src/uncore/plic_apb.sv | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index af7845f0a..36de7f396 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -93,13 +93,6 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( assign Din = PWDATA[31:0]; end - // *** RT: 05 July 2023: BUG BUG BUG. PLIC_NUM_SRC_LT_32 is undefined after parameterization - // the FPGA does work the following code. For now I'm leaving the `define undefined but this - // means the code is only valid for 33 to 64 interrupt sources. In general this needs to be - // rethought for a more generalized implementation. - //if (P.PLIC_NUM_SRC_LT_32) `define PLIC_NUM_SRC_LT_32 - //`define PLIC_NUM_SRC_LT_32 - // ================== // Register Interface // ================== @@ -122,6 +115,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( // verilator lint_off SELRANGE // *** RT: Long term we want to factor out these variable number of registers as a generate loop + // I think this won't work as a case statement. 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; // verilator lint_on SELRANGE From 850d8c2b24c0ccbca359051c9eda50bec02a2b70 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 7 Jul 2023 16:33:34 -0500 Subject: [PATCH 46/54] Fixed slight bug in config from parameterization. --- config/shared/test-shared.vh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/shared/test-shared.vh b/config/shared/test-shared.vh index 04961071f..96ef1e929 100644 --- a/config/shared/test-shared.vh +++ b/config/shared/test-shared.vh @@ -93,7 +93,7 @@ localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2); localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS); // division constants -localparam DIVN = (((NF(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+ /* verilator lint_off STMTDLY */ /* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ \ No newline at end of file +/* verilator lint_off PINCONNECTEMPTY */ From 74834bde2c1dc2cca21a0926caf2d768591eee44 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 7 Jul 2023 16:34:08 -0500 Subject: [PATCH 47/54] Removed duplicate signal name from testbench. --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0bcc34079..caa60e23c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -466,7 +466,7 @@ module testbench; integer i; logic [31:0] sig32[0:SIGNATURESIZE]; logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; - string signame, pathname; + string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; // for tests with no self checking mechanism, read .signature.output file and compare to check for errors From 4e54e5169b3c37b605717c842b4943b676b5c981 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 7 Jul 2023 18:22:28 -0500 Subject: [PATCH 48/54] Changes for xcelium. --- sim/wally.xrun | 2 ++ src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- src/mmu/pmpchecker.sv | 2 +- testbench/common/functionName.sv | 6 +++--- testbench/common/loggers.sv | 26 +++++++++++++++----------- testbench/common/shadowmem.sv | 8 ++++---- testbench/common/wallyTracer.sv | 2 +- testbench/testbench.sv | 2 +- 8 files changed, 28 insertions(+), 22 deletions(-) create mode 100644 sim/wally.xrun diff --git a/sim/wally.xrun b/sim/wally.xrun new file mode 100644 index 000000000..9e20e7fee --- /dev/null +++ b/sim/wally.xrun @@ -0,0 +1,2 @@ +xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv +xrun -elaborate -top testbench ../testbench/testbench.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index a727e5536..0e2cba90e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -55,7 +55,7 @@ module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) ( assign FDivBusyE = (state == BUSY) | IFDivStartE; // terminate immediately on special cases - assign FSpecialCaseE = XZeroE | | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE; + assign FSpecialCaseE = XZeroE | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE; if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE; else assign SpecialCaseE = FSpecialCaseE; flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index fd1243031..89c22c486 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -67,7 +67,7 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode + assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 90157f255..8498a425d 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -119,8 +119,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( // initial begin always @ (negedge reset) begin // clear out the old mapping between programs. - foreach(ProgramAddrMapMemory[i]) ProgramAddrMapMemory.delete(i); - foreach(ProgramLabelMapMemory[i]) ProgramLabelMapMemory.delete(i); + ProgramAddrMapMemory.delete(); + ProgramLabelMapMemory.delete(); $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory); // we need to count the number of lines in the file so we can set FunctionRadixLineCount. @@ -169,7 +169,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0; initial ProgramAddrIndex = '0; - assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex]; + always @(*) FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex]; endmodule // function_radix diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index cf42fe4ec..18aa2de34 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -151,8 +151,10 @@ module loggers import cvw::*; #(parameter cvw_t P, $fwrite(file, "BEGIN %s\n", memfilename); end string AccessTypeString, HitMissString; - assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : - dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; + always @(*) begin + HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : + dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; + end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename); @@ -174,15 +176,17 @@ module loggers import cvw::*; #(parameter cvw_t P, flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; - assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : - (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : - dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; - assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" : - dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" : - dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : - dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : - "NULL"; - + always @(*) begin + HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : + (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : + dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; + AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" : + dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" : + dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : + dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : + "NULL"; + end + assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & diff --git a/testbench/common/shadowmem.sv b/testbench/common/shadowmem.sv index 021d4b82f..19884390d 100644 --- a/testbench/common/shadowmem.sv +++ b/testbench/common/shadowmem.sv @@ -39,10 +39,10 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) logic startD; if(P.DCACHE_SUPPORTED) begin - localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; + localparam numlines = P.DCACHE_WAYSIZEINBYTES*8/P.DCACHE_LINELENINBITS; + localparam numways = P.DCACHE_NUMWAYS; + localparam linelen = P.DCACHE_LINELENINBITS; + localparam linebytelen = linelen/8; localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; localparam numwords = sramlen/P.XLEN; diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index a1dc318ec..66accfc9f 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -163,7 +163,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; - CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; + CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // user CSRs CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0bcc34079..caa60e23c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -466,7 +466,7 @@ module testbench; integer i; logic [31:0] sig32[0:SIGNATURESIZE]; logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; - string signame, pathname; + string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; // for tests with no self checking mechanism, read .signature.output file and compare to check for errors From c91bbc3ca8788a271f4cd36a0ac976b7f0c87bd2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 9 Jul 2023 18:25:07 -0700 Subject: [PATCH 49/54] MENVCFG only exists if U_SUPPORTED --- src/privileged/csrm.sv | 68 ++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 33 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index d77ed5175..a95ba8299 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -54,11 +54,9 @@ module csrm import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; logic [P.XLEN-1:0] MENVCFGH_REGW; - logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; - logic WriteMENVCFGM; // Machine CSRs localparam MVENDORID = 12'hF11; @@ -145,7 +143,6 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)); assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)); assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN); - assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG); assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT); assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID); @@ -167,28 +164,33 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); end else assign MCOUNTEREN_REGW = '0; - // MENVCFG is always 64 bits even for RV32 - assign MENVCFG_WriteValM = { - MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED, - MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED, - 54'b0, - MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED, - MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, - 3'b0, - MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED - }; - - if (P.XLEN == 64) begin - assign MENVCFG_PreWriteValM = CSRWriteValM; - flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW); - assign MENVCFGH_REGW = 0; - end else begin - logic WriteMENVCFGHM; - assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM}; - assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32); - flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]); - flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]); - assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; + // MENVCFG register + if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control + logic WriteMENVCFGM; + logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM; + assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG); + // MENVCFG is always 64 bits even for RV32 + assign MENVCFG_WriteValM = { + MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED, + MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED, + 54'b0, + MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED, + MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, + 3'b0, + MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED + }; + if (P.XLEN == 64) begin + assign MENVCFG_PreWriteValM = CSRWriteValM; + flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW); + assign MENVCFGH_REGW = 0; + end else begin // RV32 has high and low halves + logic WriteMENVCFGHM; + assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM}; + assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32); + flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]); + flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]); + assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; + end end // Read machine mode CSRs @@ -196,6 +198,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( logic [5:0] entry; always_comb begin entry = '0; + CSRMReadValM = 0; IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]}; @@ -218,7 +221,8 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0 MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0 MSTATUS: CSRMReadValM = MSTATUS_REGW; - MSTATUSH: CSRMReadValM = MSTATUSH_REGW; + MSTATUSH: if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW; + else IllegalCSRMAccessM = 1; MTVEC: CSRMReadValM = MTVEC_REGW; MEDELEG: CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW}; MIDELEG: CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW}; @@ -229,14 +233,12 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MCAUSE: CSRMReadValM = MCAUSE_REGW; MTVAL: CSRMReadValM = MTVAL_REGW; MCOUNTEREN: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW}; - MENVCFG: CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0]; - MENVCFGH: CSRMReadValM = MENVCFGH_REGW; + MENVCFG: if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0]; + else IllegalCSRMAccessM = 1; + MENVCFGH: if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW; + else IllegalCSRMAccessM = 1; MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW}; - - default: begin - CSRMReadValM = 0; - IllegalCSRMAccessM = 1; - end + default: IllegalCSRMAccessM = 1; endcase end // verilator lint_on WIDTH From e647937b27589cdaf94b483a0e83abac3960af87 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 10 Jul 2023 17:00:06 -0500 Subject: [PATCH 50/54] Fixed the privilege decoder bug which prevented the fpga linux boot. --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index c543348e5..ede8f258e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -200,7 +200,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( ((P.XLEN == 64) & (Funct3D == 3'b011)); assign BFunctD = Funct3D[2:1] != 2'b01; // legal branches assign JRFunctD = Funct3D == 3'b000; - assign PFunctD = Funct3D == 3'b000 & Rs1D == 5'b0 & RdD == 5'b0; + assign PFunctD = Funct3D == 3'b000 & RdD == 5'b0; assign CSRFunctD = Funct3D[1:0] != 2'b00; assign IWValidFunct3D = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101; end else begin:legalcheck2 From 05b1cce2d13c59557576c58d17057089214b35e4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 11 Jul 2023 10:51:02 -0500 Subject: [PATCH 51/54] RTL changes for Xcelium. --- src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- src/mmu/pmpchecker.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index a727e5536..0e2cba90e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -55,7 +55,7 @@ module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) ( assign FDivBusyE = (state == BUSY) | IFDivStartE; // terminate immediately on special cases - assign FSpecialCaseE = XZeroE | | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE; + assign FSpecialCaseE = XZeroE | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE; if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE; else assign SpecialCaseE = FSpecialCaseE; flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index fd1243031..89c22c486 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -67,7 +67,7 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode + assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; From b26dc6db7f3f8ca9a3cb5971e635d43af41c70d2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 11 Jul 2023 10:51:17 -0500 Subject: [PATCH 52/54] Simplificaiton of function tracker. --- testbench/common/functionName.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 90157f255..84ed99928 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -119,8 +119,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( // initial begin always @ (negedge reset) begin // clear out the old mapping between programs. - foreach(ProgramAddrMapMemory[i]) ProgramAddrMapMemory.delete(i); - foreach(ProgramLabelMapMemory[i]) ProgramLabelMapMemory.delete(i); + ProgramAddrMapMemory.delete(); + ProgramLabelMapMemory.delete(); $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory); // we need to count the number of lines in the file so we can set FunctionRadixLineCount. From c12bc4f4355e7a69781700762d284f03b78091d0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 11 Jul 2023 15:07:33 -0500 Subject: [PATCH 53/54] Created separate temporary testbench for xcelium. --- src/cache/cacheway.sv | 2 +- testbench/testbench-xcelium.sv | 606 +++++++++++++++++++++++++++++++++ 2 files changed, 607 insertions(+), 1 deletion(-) create mode 100644 testbench/testbench-xcelium.sv diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 0a5c7b6e5..4438ea2c7 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -124,7 +124,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, genvar words; - localparam SRAMLEN = 128; + localparam SRAMLEN = 128; // *** make this a global parameter localparam NUMSRAM = LINELEN/SRAMLEN; localparam SRAMLENINBYTES = SRAMLEN/8; localparam LOGNUMSRAM = $clog2(NUMSRAM); diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv new file mode 100644 index 000000000..368cc3f07 --- /dev/null +++ b/testbench/testbench-xcelium.sv @@ -0,0 +1,606 @@ +/////////////////////////////////////////// +// testbench.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Wally Testbench and helper modules +// Applies test programs from the riscv-arch-test and Imperas suites +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "config.vh" +`include "tests.vh" + +import cvw::*; + +module testbench; + /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ + parameter DEBUG=0; + parameter TEST="none"; + parameter PrintHPMCounters=1; + parameter BPRED_LOGGER=0; + parameter I_CACHE_ADDR_LOGGER=0; + parameter D_CACHE_ADDR_LOGGER=0; + +`include "parameter-defs.vh" + + logic clk; + logic reset_ext, reset; + logic ResetMem; + + // DUT signals + logic [P.AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic [P.PA_BITS-1:0] HADDR; + logic [P.AHBW-1:0] HWDATA; + logic [P.XLEN/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; + logic UARTSin, UARTSout; + + logic SDCCLK; + logic SDCCmdIn; + logic SDCCmdOut; + logic SDCCmdOE; + logic [3:0] SDCDatIn; + tri1 [3:0] SDCDat; + tri1 SDCCmd; + + logic HREADY; + logic HSELEXT; + + + string ProgramAddrMapFile, ProgramLabelMapFile; + integer ProgramAddrLabelArray [string]; + + int test, i, errors, totalerrors; + + string outputfile; + integer outputFilePointer; + + string tests[]; + logic DCacheFlushDone, DCacheFlushStart; + logic riscofTest; + logic Validate; + logic SelectTest; + + + + // pick tests based on modes supported + initial begin + $display("TEST is %s", TEST); + //tests = '{}; + if (P.XLEN == 64) begin // RV64 + case (TEST) + "arch64i": tests = arch64i; + "arch64priv": tests = arch64priv; + "arch64c": if (P.C_SUPPORTED) + if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; + else tests = {arch64c}; + "arch64m": if (P.M_SUPPORTED) tests = arch64m; + "arch64f": if (P.F_SUPPORTED) tests = arch64f; + "arch64d": if (P.D_SUPPORTED) tests = arch64d; + "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; + "arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma; + "arch64zi": if (P.ZIFENCEI_SUPPORTED) tests = arch64zi; + "imperas64i": tests = imperas64i; + "imperas64f": if (P.F_SUPPORTED) tests = imperas64f; + "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; + "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; + "wally64a": if (P.A_SUPPORTED) tests = wally64a; + "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; + else tests = imperas64iNOc; + "custom": tests = custom; + "wally64i": tests = wally64i; + "wally64priv": tests = wally64priv; + "wally64periph": tests = wally64periph; + "coremark": tests = coremark; + "fpga": tests = fpga; + "ahb" : tests = ahb; + "coverage64gc" : tests = coverage64gc; + "arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba; + "arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb; + "arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc; + "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; + endcase + end else begin // RV32 + case (TEST) + "arch32i": tests = arch32i; + "arch32priv": tests = arch32priv; + "arch32c": if (P.C_SUPPORTED) + if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; + else tests = {arch32c}; + "arch32m": if (P.M_SUPPORTED) tests = arch32m; + "arch32f": if (P.F_SUPPORTED) tests = arch32f; + "arch32d": if (P.D_SUPPORTED) tests = arch32d; + "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; + "arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma; + "arch32zi": if (P.ZIFENCEI_SUPPORTED) tests = arch32zi; + "imperas32i": tests = imperas32i; + "imperas32f": if (P.F_SUPPORTED) tests = imperas32f; + "imperas32m": if (P.M_SUPPORTED) tests = imperas32m; + "wally32a": if (P.A_SUPPORTED) tests = wally32a; + "imperas32c": if (P.C_SUPPORTED) tests = imperas32c; + else tests = imperas32iNOc; + "wally32i": tests = wally32i; + "wally32e": tests = wally32e; + "wally32priv": tests = wally32priv; + "wally32periph": tests = wally32periph; + "embench": tests = embench; + "coremark": tests = coremark; + "arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba; + "arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb; + "arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc; + "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; + endcase + end + if (tests.size() == 0) begin + $display("TEST %s not supported in this configuration", TEST); + $stop; + end + end // initial begin + + // Model the testbench as an fsm. + // Do this in parts so it easier to verify + // part 1: build a version which echos the same behavior as the below code, but does not drive anything + // part 2: drive some of the controls + // part 3: drive all logic and remove old inital and always @ negedge clk block + + typedef enum logic [3:0]{STATE_TESTBENCH_RESET, + STATE_INIT_TEST, + STATE_RESET_MEMORIES, + STATE_RESET_MEMORIES2, + STATE_LOAD_MEMORIES, + STATE_RESET_TEST, + STATE_RUN_TEST, + STATE_CHECK_TEST, + STATE_CHECK_TEST_WAIT, + STATE_VALIDATE, + STATE_INCR_TEST} statetype; + statetype CurrState, NextState; + logic TestBenchReset; + logic [2:0] ResetCount, ResetThreshold; + logic LoadMem; + logic ResetCntEn; + logic ResetCntRst; + + + string signame, memfilename, pathname; + integer begin_signature_addr; + + assign ResetThreshold = 3'd5; + + initial begin + TestBenchReset = 1; + # 100; + TestBenchReset = 0; + end + + always_ff @(posedge clk) + if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET; + else CurrState <= #1 NextState; + + // fsm next state logic + always_comb begin + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests + // and tests[0] == "2" refers to WallyRiscvArchTests + riscofTest = tests[0] == "1" | tests[0] == "2"; + pathname = tvpaths[tests[0].atoi()]; + + case(CurrState) + STATE_TESTBENCH_RESET: NextState = STATE_INIT_TEST; + STATE_INIT_TEST: NextState = STATE_RESET_MEMORIES; + STATE_RESET_MEMORIES: NextState = STATE_RESET_MEMORIES2; + STATE_RESET_MEMORIES2: NextState = STATE_LOAD_MEMORIES; // Give the reset enough time to ensure the bus is reset before loading the memories. + STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST; + STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST; + else NextState = STATE_RUN_TEST; + STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST; + else NextState = STATE_RUN_TEST; + STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE; + else NextState = STATE_CHECK_TEST_WAIT; + STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE; + else NextState = STATE_CHECK_TEST_WAIT; + STATE_VALIDATE: NextState = STATE_INIT_TEST; + STATE_INCR_TEST: NextState = STATE_INIT_TEST; + default: NextState = STATE_TESTBENCH_RESET; + endcase + end // always_comb + // fsm output control logic + assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST | + CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 | + CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST; + // this initialization is very expensive, only do it for coremark. + assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark"; + assign LoadMem = CurrState == STATE_LOAD_MEMORIES; + assign ResetCntRst = CurrState == STATE_INIT_TEST; + assign ResetCntEn = CurrState == STATE_RESET_TEST; + assign Validate = CurrState == STATE_VALIDATE; + assign SelectTest = CurrState == STATE_INIT_TEST; + + // fsm reset counter + counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount); + + //////////////////////////////////////////////////////////////////////////////// + // Find the test vector files and populate the PC to function label converter + //////////////////////////////////////////////////////////////////////////////// + logic [P.XLEN-1:0] testadr; + assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; + always @(posedge clk) begin + if(SelectTest) begin + if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; + else memfilename = {pathname, tests[test], ".elf.memfile"}; + if (riscofTest) begin + ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; + end else begin + ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + end + // declare memory labels that interest us, the updateProgramAddrLabelArray task will find + // the addr of each label and fill the array. To expand, add more elements to this array + // and initialize them to zero (also initilaize them to zero at the start of the next test) + if(!P.FPGA) begin + updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); + end + end + + //////////////////////////////////////////////////////////////////////////////// + // Verify the test ran correctly by checking the memory against a known signature. + //////////////////////////////////////////////////////////////////////////////// + if(TestBenchReset) test = 1; + if (TEST == "coremark") + if (dut.core.EcallFaultM) begin + $display("Benchmark: coremark is done."); + $stop; + end + if(Validate) begin + if (TEST == "embench") begin + // Writes contents of begin_signature to .sim.output file + // this contains instret and cycles for start and end of test run, used by embench + // python speed script to calculate embench speed score. + // also, begin_signature contains the results of the self checking mechanism, + // which will be read by the python script for error checking + $display("Embench Benchmark: %s is done.", tests[test]); + if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; + else outputfile = {pathname, tests[test], ".sim.output"}; + outputFilePointer = $fopen(outputfile, "w"); + i = 0; + testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); + while ($unsigned(i) < $unsigned(5'd5)) begin + $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]); + i = i + 1; + end + $fclose(outputFilePointer); + $display("Embench Benchmark: created output file: %s", outputfile); + end else if (TEST == "coverage64gc") begin + $display("Coverage tests don't get checked"); + end else begin + // for tests with no self checking mechanism, read .signature.output file and compare to check for errors + // clear signature to prevent contamination from previous tests + end + + if (!begin_signature_addr) + $display("begin_signature addr not found in %s", ProgramLabelMapFile); + else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution + CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors); + end + if(errors > 0) totalerrors = totalerrors + 1; + test = test + 1; // *** this probably needs to be moved. + if (test == tests.size()) begin + if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); + else $display("FAIL: %d test programs had errors", totalerrors); + $stop; + end + end + end + + + //////////////////////////////////////////////////////////////////////////////// + // Some memories are not reset, but should be zeros or set to some initial value for simulation + //////////////////////////////////////////////////////////////////////////////// + integer adrindex; + + if (P.UNCORE_RAM_SUPPORTED) `define TB_UNCORE_RAM_SUPPORTED; + if (P.BPRED_SUPPORTED) `define TB_BPRED_SUPPORTED; + if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) `define TB_BHT; + + always @(posedge clk) begin + if (ResetMem) // program memory is sometimes reset + if (P.UNCORE_RAM_SUPPORTED) begin + `ifdef TB_UNCORE_RAM_SUPPORTED + for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + `endif + end + if(reset) begin // branch predictor must always be reset + if (P.BPRED_SUPPORTED) begin + `ifdef TB_BPRED_SUPPORTED + // local history only + if (P.BPRED_TYPE == BP_LOCAL_AHEAD | P.BPRED_TYPE == BP_LOCAL_REPAIR) begin + `ifdef TB_BHT + for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; + `endif + end + // these are both always included if there is a bpred + for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + `endif + end + end + end + + //////////////////////////////////////////////////////////////////////////////// + // load memories with program image + //////////////////////////////////////////////////////////////////////////////// + if (P.FPGA) `define TB_FPGA // this is a gross hack for xcelium and verilator + if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED + if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED + if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED + always @(posedge clk) begin + if (LoadMem) begin + if (P.FPGA) begin + `ifdef TB_FPGA + string romfilename, sdcfilename; + romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; + sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; + $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); + $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); + // shorten sdc timers for simulation + dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + `endif + end + else if (P.IROM_SUPPORTED) begin + `ifdef TB_IROM_SUPPORTED + $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + `endif + end + else if (P.BUS_SUPPORTED) begin + `ifdef TB_BUS_SUPPORTED + $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + `endif + end + if (P.DTIM_SUPPORTED) begin + `ifdef TB_DTIM_SUPPORTED + $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + `endif + end + $display("Read memfile %s", memfilename); + end + end + + //////////////////////////////////////////////////////////////////////////////// + // Actual hardware + //////////////////////////////////////////////////////////////////////////////// + + // instantiate device to be tested + assign GPIOIN = 0; + assign UARTSin = 1; + + if(P.EXT_MEM_SUPPORTED) begin + ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE)) + ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), + .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB); + end else begin + assign HREADYEXT = 1; + assign {HRESPEXT, HRDATAEXT} = '0; + end + + if(P.FPGA) begin : sdcard + sdModel sdcard + (.sdClk(SDCCLK), + .cmd(SDCCmd), + .dat(SDCDat)); + + assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz; + assign SDCCmdIn = SDCCmd; + assign SDCDatIn = SDCDat; + end else begin + assign SDCCmd = '0; + assign SDCDat = '0; + end + + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, + .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); + + // generate clock to sequence tests + always begin + clk = 1; # 5; clk = 0; # 5; + end + + //////////////////////////////////////////////////////////////////////////////// + // Support logic + //////////////////////////////////////////////////////////////////////////////// + + // Track names of instructions + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); + instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, + dut.core.ifu.InstrRawF[31:0], + dut.core.ifu.InstrD, dut.core.ifu.InstrE, + dut.core.ifu.InstrM, InstrW, + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + // watch for problems such as lockup, reading unitialized memory, bad configs + watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck + ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM, + dut.core.ifu.PCM, dut.core.ifu.InstrM, dut.core.lsu.IEUAdrM, InstrMName); + riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration + loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER) + loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename); + + // track the current function or global label + if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName + FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), + .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); + end + + + // Termination condition + // terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed + // or sw gp,-56(t0) for new Imperas tests + // or sd gp, -56(t0) + // or on a jump to self infinite loop (6f) for RISC-V Arch tests + logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls + if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM; + else assign ecf = 0; + assign DCacheFlushStart = ecf & + (dut.core.ieu.dp.regf.rf[3] == 1 | + (dut.core.ieu.dp.regf.we3 & + dut.core.ieu.dp.regf.a3 == 3 & + dut.core.ieu.dp.regf.wd3 == 1)) | + ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); + + DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone)); + + task automatic CheckSignature; + // This task must be declared inside this module as it needs access to parameter P. There is + // no way to pass P to the task unless we convert it to a module. + + input string pathname; + input string TestName; + input logic riscofTest; + input integer begin_signature_addr; + output integer errors; + + localparam SIGNATURESIZE = 5000000; + integer i; + logic [31:0] sig32[0:SIGNATURESIZE]; + logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; + string signame; + logic [P.XLEN-1:0] testadr, testadrNoBase; + + if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED2 + + // for tests with no self checking mechanism, read .signature.output file and compare to check for errors + // clear signature to prevent contamination from previous tests + for(i=0; i Date: Thu, 13 Jul 2023 02:41:17 -0700 Subject: [PATCH 54/54] Clean up privilege rs1 decoding and implement svinval as sfence.vma --- config/buildroot/config.vh | 2 +- config/fpga/config.vh | 1 + config/rv32e/config.vh | 1 + config/rv32gc/config.vh | 1 + config/rv32i/config.vh | 1 + config/rv32imc/config.vh | 1 + config/rv64fpquad/config.vh | 1 + config/rv64gc/config.vh | 1 + config/rv64i/config.vh | 1 + config/shared/parameter-defs.vh | 1 + src/cvw.sv | 1 + src/privileged/privdec.sv | 29 +++++++++++++++++++++-------- src/privileged/privileged.sv | 2 +- 13 files changed, 33 insertions(+), 10 deletions(-) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index 14f329907..371c825e2 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -49,7 +49,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; - +localparam SVINVAL_SUPPORTED = 1; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/fpga/config.vh b/config/fpga/config.vh index 25fbaae13..dbd7d9687 100644 --- a/config/fpga/config.vh +++ b/config/fpga/config.vh @@ -50,6 +50,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index e19e5e892..30b7c3050 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 031cd523f..a966b0401 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -50,6 +50,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 892ee356b..eda81e298 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 1359cae49..0b2aee01e 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -48,6 +48,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 48a341b93..a784d369f 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 243b6ed47..8d266ab3e 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -52,6 +52,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 426a012ca..ff6a1c61e 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -49,6 +49,7 @@ localparam ZICBOM_SUPPORTED = 0; localparam ZICBOZ_SUPPORTED = 0; localparam ZICBOP_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 0; diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 713a947e8..f1000d6d9 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -24,6 +24,7 @@ parameter cvw_t P = '{ ZICBOZ_SUPPORTED : ZICBOZ_SUPPORTED, ZICBOP_SUPPORTED : ZICBOP_SUPPORTED, SVPBMT_SUPPORTED : SVPBMT_SUPPORTED, + SVINVAL_SUPPORTED : SVINVAL_SUPPORTED, BUS_SUPPORTED : BUS_SUPPORTED, DCACHE_SUPPORTED : DCACHE_SUPPORTED, ICACHE_SUPPORTED : ICACHE_SUPPORTED, diff --git a/src/cvw.sv b/src/cvw.sv index 896c3245b..e2c81b4e2 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -61,6 +61,7 @@ typedef struct packed { logic ZICBOZ_SUPPORTED; logic ZICBOP_SUPPORTED; logic SVPBMT_SUPPORTED; + logic SVINVAL_SUPPORTED; // Microarchitectural Features logic BUS_SUPPORTED; diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 59db8c9d4..a0195f366 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -30,7 +30,7 @@ module privdec import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, input logic StallM, - input logic [31:20] InstrM, // privileged instruction function field + input logic [31:15] InstrM, // privileged instruction function field input logic PrivilegedM, // is this a privileged instruction (from IEU controller) input logic IllegalIEUFPUInstrM, // Not a legal IEU instruction input logic IllegalCSRAccessM, // Not a legal CSR access @@ -39,24 +39,37 @@ module privdec import cvw::*; #(parameter cvw_t P) ( output logic IllegalInstrFaultM, // Illegal instruction output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs output logic sretM, mretM, // return instructions - output logic wfiM, sfencevmaM // wfi / sfence.fma instructions + output logic wfiM, sfencevmaM // wfi / sfence.vma / sinval.vma instructions ); + logic rs1zeroM; // rs1 field = 0 logic IllegalPrivilegedInstrM; // privileged instruction isn't a legal one or in legal mode logic WFITimeoutM; // WFI reaches timeout threshold logic ebreakM, ecallM; // ebreak / ecall instructions + logic sinvalvmaM; // sinval.vma + logic sfencewinvalM, sfenceinvalirM; // sfence.w.inval, sfence.inval.ir + logic invalM; // any of the svinval instructions /////////////////////////////////////////// // Decode privileged instructions /////////////////////////////////////////// - assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & P.S_SUPPORTED & + assign rs1zeroM = InstrM[19:15] == 5'b0; + + // svinval instructions + // any svinval instruction is treated as sfence.vma on Wally + assign sinvalvmaM = (InstrM[31:25] == 7'b0001001); + assign sfencewinvalM = (InstrM[31:20] == 12'b000110000000) & rs1zeroM; + assign sfenceinvalirM = (InstrM[31:20] == 12'b000110000001) & rs1zeroM; + assign invalM = P.SVINVAL_SUPPORTED & (sinvalvmaM | sfencewinvalM | sfenceinvalirM); + + assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED & (PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR); - assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == P.M_MODE); - assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000); - assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); - assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); - assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001) & + assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & rs1zeroM & (PrivilegeModeW == P.M_MODE); + assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM; + assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM; + assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM; + assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001 | invalM) & (PrivilegeModeW == P.M_MODE | (PrivilegeModeW == P.S_MODE & ~STATUS_TVM)); /////////////////////////////////////////// diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 1023618b5..46c69f17d 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -118,7 +118,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); // decode privileged instructions - privdec #(P) pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), + privdec #(P) pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:15]), .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);