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https://github.com/openhwgroup/cvw
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Lint cleanup
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@ -380,7 +380,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
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if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
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else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats.
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else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats.
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assign LSUHBURST = 3'b0;
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assign LSUHBURST = 3'b0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0;
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end
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end
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end else begin: nobus // block: bus, only DTIM
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end else begin: nobus // block: bus, only DTIM
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assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0;
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assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0;
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@ -115,8 +115,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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logic SelHPTW;
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logic SelHPTW;
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// PMA checker signals
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// PMA checker signals
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/* verilator lint_off UNDRIVEN */ // these signals are undriven in configurations without a privileged unit
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var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
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var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
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var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
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var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
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/* verilator lint_on UNDRIVEN */
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// IMem stalls
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// IMem stalls
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logic IFUStallF;
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logic IFUStallF;
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