From cac67aae4f08ab30f47aa856f3f5a958923f5dde Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Tue, 18 Jun 2024 05:58:54 -0700
Subject: [PATCH] Lint cleanup

---
 src/lsu/lsu.sv                  | 2 +-
 src/wally/wallypipelinedcore.sv | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index f0d046679..e5ecec458 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -380,7 +380,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
       if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
       else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats.
       assign LSUHBURST = 3'b0;
-      assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
+      assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess, DCacheReadDataWordM} = '0;
     end
   end else begin: nobus // block: bus, only DTIM
     assign {LSUHWDATA, LSUHADDR, LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHWSTRB} = '0; 
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index b20472732..16a4d9e61 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -115,8 +115,10 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          SelHPTW;
 
   // PMA checker signals
+  /* verilator lint_off UNDRIVEN */ // these signals are undriven in configurations without a privileged unit
   var logic [P.PA_BITS-3:0]      PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
   var logic [7:0]                PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
+  /* verilator lint_on UNDRIVEN */
 
   // IMem stalls
   logic                          IFUStallF;