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Merge pull request #1194 from kevindkim723/divremsqrtport

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fixed typos in intdiv regression script; added delay state in fp-testbench fsm to fix a bug
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David Harris 2024-12-19 14:16:06 -08:00 committed by GitHub
commit caa700ef18
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2 changed files with 7 additions and 3 deletions
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2
bin/regression-wally-intdiv
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@ -447,7 +447,7 @@ if (intdiv):
] ]
for config in intdivconfigs: for config in intdivconfigs:
# fdivremsqrt test case # fdivremsqrt test case
name = "div_drsu" name = "fdivremsqrt"
logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+name+".log" logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+name+".log"
fdivremsqrttestcase = TestCase( fdivremsqrttestcase = TestCase(
name=name, name=name,

8
testbench/testbench_fp.sv
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@ -131,7 +131,7 @@ module testbench_fp;
logic IntDivE; // Is Integer operation on FPU? logic IntDivE; // Is Integer operation on FPU?
// FSM for testing each item per clock // FSM for testing each item per clock
typedef enum logic [2:0] {S0, Start, S2, Done} statetype; typedef enum logic [2:0] {S0, S1, Start, S2, Done} statetype;
statetype state, nextstate; statetype state, nextstate;
/////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////
@ -1051,6 +1051,10 @@ module testbench_fp;
// properly and within time. // properly and within time.
case (state) case (state)
S0: begin S0: begin
DivStart = 1'b0;
nextstate = S1;
end
S1: begin
DivStart = 1'b0; DivStart = 1'b0;
nextstate = Start; nextstate = Start;
end end
@ -1199,7 +1203,7 @@ module testbench_fp;
errors += 1; errors += 1;
$display("\nError in %s", Tests[TestNum]); $display("\nError in %s", Tests[TestNum]);
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]); $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); $display("inputs: %h %h %h\nSrcA: %h\nSrcB: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, SrcB, Res, ResFlg, Ans, AnsFlg);
$stop; $stop;
end end