diff --git a/bin/regression-wally-intdiv b/bin/regression-wally-intdiv
index 5408e8661..2ea280a70 100755
--- a/bin/regression-wally-intdiv
+++ b/bin/regression-wally-intdiv
@@ -447,7 +447,7 @@ if (intdiv):
     ]
     for config in intdivconfigs:
         # fdivremsqrt test case
-        name = "div_drsu"
+        name = "fdivremsqrt"
         logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+name+".log" 
         fdivremsqrttestcase = TestCase(
             name=name,
diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv
index 1617d392c..24c0d8abf 100644
--- a/testbench/testbench_fp.sv
+++ b/testbench/testbench_fp.sv
@@ -131,7 +131,7 @@ module testbench_fp;
    logic      IntDivE;                    // Is Integer operation on FPU?
 
    // FSM for testing each item per clock
-   typedef enum logic [2:0] {S0, Start, S2, Done} statetype;
+   typedef enum logic [2:0] {S0, S1, Start, S2, Done} statetype;
    statetype state, nextstate;   
    
    ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -1051,6 +1051,10 @@ module testbench_fp;
       // properly and within time.
       case (state)
         S0: begin
+           DivStart = 1'b0;
+           nextstate = S1;
+        end
+        S1: begin
            DivStart = 1'b0;
            nextstate = Start;
         end
@@ -1199,7 +1203,7 @@ module testbench_fp;
          errors += 1;
          $display("\nError in %s", Tests[TestNum]);
          $display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);	 
-         $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
+         $display("inputs: %h %h %h\nSrcA: %h\nSrcB: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, SrcB, Res, ResFlg, Ans, AnsFlg);
          $stop;
       end