Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-22 20:44:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1194 from kevindkim723/divremsqrtport

Browse Source 
fixed typos in intdiv regression script; added delay state in fp-testbench fsm to fix a bug
This commit is contained in:
David Harris 2024-12-19 14:16:06 -08:00 committed by GitHub
commit caa700ef18
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
bin/regression-wally-intdiv
View File

@ -447,7 +447,7 @@ if (intdiv):
]
for config in intdivconfigs:
# fdivremsqrt test case
name = "div_drsu"
name = "fdivremsqrt"
logname = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+name+".log"
fdivremsqrttestcase = TestCase(
name=name,

8
testbench/testbench_fp.sv
View File

@ -131,7 +131,7 @@ module testbench_fp;
logic IntDivE; // Is Integer operation on FPU?
// FSM for testing each item per clock
typedef enum logic [2:0] {S0, Start, S2, Done} statetype;
typedef enum logic [2:0] {S0, S1, Start, S2, Done} statetype;
statetype state, nextstate;
///////////////////////////////////////////////////////////////////////////////////////////////
@ -1051,6 +1051,10 @@ module testbench_fp;
// properly and within time.
case (state)
S0: begin
DivStart = 1'b0;
nextstate = S1;
end
S1: begin
DivStart = 1'b0;
nextstate = Start;
end
@ -1199,7 +1203,7 @@ module testbench_fp;
errors += 1;
$display("\nError in %s", Tests[TestNum]);
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
$display("inputs: %h %h %h\nSrcA: %h\nSrcB: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, SrcB, Res, ResFlg, Ans, AnsFlg);
$stop;
end