Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230

pipelined/regression/Makefile

@@ -1,3 +1,7 @@
+make allclean:
+	make clean
+	make all
+
 make clean:
 	make clean -C ../../addins/riscv-arch-test
 	make clean -C ../../tests/wally-riscv-arch-test
@@ -15,7 +19,9 @@ make all:
 	cd ../../tests/wally-riscv-arch-test; elf2hex.sh
 	# ***extractFunctionRadix
 
-	# Only compile Imperas tests if they are installed
+	# Only compile Imperas tests if they are installed locally.  
+	# They are usually a symlink to $RISCV/imperas-riscv-tests and only 
+	# get compiled there manually during installation
 	# make -C ../../addins/imperas-riscv-tests
 	# make -C ../../addins/imperas-riscv-tests XLEN=64
 	# cd ../../addins/imperas-riscv-tests; elf2hex.sh

pipelined/regression/sim-wally

@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv64gc arch64d"
+vsim -do "do wally-pipelined.do rv32gc arch32f"
 

pipelined/regression/sim-wally-batch

@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv64gc arch64d 
+do wally-pipelined-batch.do rv32gc arch32f
 !

pipelined/src/fpu/fma.sv

@@ -557,7 +557,6 @@ module normalize(
     output logic [`NE+1:0]      SumExp,         // exponent of the normalized sum
     output logic                ResultDenorm    // is the result denormalized
 );
-    logic [`NE+1:0]     FracLen;            // length of the fraction
     logic [`NE+1:0]     SumExpTmp;          // exponent of the normalized sum not taking into account denormal or zero results
     logic [8:0]         DenormShift;        // right shift if the result is denormalized //***change this later
     logic [3*`NF+5:0]   CorrSumShifted;     // the shifted sum after LZA correction
@@ -574,9 +573,6 @@ module normalize(
     // Determine if the sum is zero
     assign SumZero = ~(|SumM);
 
-    // determine the length of the fraction based on precision
-    assign FracLen = FmtM ? `NF+1 : 13'd24;
-
     // calculate the sum's exponent
     assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
     assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}};
@@ -752,6 +748,7 @@ module fmaflags(
     output logic [4:0]          FMAFlgM // FMA flags
 );
     logic               SigNaN;     // is an input a signaling NaN
+    logic               GtMaxExp;   // is exponent greater than the maximum
     logic               UnderflowFlag, Inexact; // flags
 
     ///////////////////////////////////////////////////////////////////////////////
@@ -770,9 +767,8 @@ module fmaflags(
    
     // Set Overflow flag if the number is too big to be represented
     //      - Don't set the overflow flag if an overflowed result isn't outputed
-    logic LtMaxExp;
+    assign GtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[7:0] | FullResultExp[8];
-    assign LtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[7:0] | FullResultExp[8];
+    assign Overflow = GtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
-    assign Overflow = LtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
 
     // Set Underflow flag if the number is too small to be represented in normal numbers
     //      - Don't set the underflow flag if the result is exact

pipelined/src/fpu/fpu.sv

@@ -125,6 +125,7 @@ module fpu (
    logic [63:0] 	  DivInput1E, DivInput2E;             // inputs to divide/squareroot unit
    logic 		  load_preload;                       // enable for FF on fpdivsqrt     
    logic [63:0] 	  AlignedSrcAE;                       // align SrcA to the floating point format
+   logic [63:0]     BoxedZeroE;                         // Zero value for Z for multiplication, with NaN boxing if needed
    
    // DECODE STAGE
 
@@ -164,7 +165,8 @@ module fpu (
             {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)}, 
             FSrcYE); // Force Z to be 0 for multiply instructions
    // Force Z to be 0 for multiply instructions 
-   mux3  #(64)  fzmulmux (FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
+   mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero
+   mux3  #(64)  fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
       
    // unpacking unit
    //    - splits FP inputs into their various parts

pipelined/src/fpu/unpacking.sv

@@ -22,11 +22,10 @@ module unpacking (
     logic           XFracZero, YFracZero, ZFracZero; // input fraction zero
     logic           XExpZero, YExpZero, ZExpZero; // input exponent zero
     logic           YExpMaxE, ZExpMaxE;  // input exponent all 1s
-    logic           XDoubleNaN, YDoubleNaN, ZDoubleNaN;
     logic  [31:0]   XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed
 
     // Determine if number is NaN as double precision to check single precision NaN boxing
-    if (`XLEN==32) begin  // eventually this should change to FLEN when RV32f has FLEN=32
+    if (`F_SUPPORTED & ~`D_SUPPORTED) begin  // eventually this should change to FLEN when FLEN isn't hardwared to 64
         assign XFloat = X[31:0]; 
         assign YFloat = Y[31:0];  
         assign ZFloat = Z[31:0]; 

pipelined/src/wally/wallypipelinedhart.sv

@@ -68,8 +68,8 @@ module wallypipelinedhart (
   (* mark_debug = "true" *) logic [31:0] 		    InstrM;
   logic [`XLEN-1:0] 	    PCF, PCD, PCE, PCLinkE;
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    PCM;
-  logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
+ logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
-  logic [`XLEN-1:0] 	    PrivilegedNextPCM;
+   logic [`XLEN-1:0] 	    PrivilegedNextPCM;
   (* mark_debug = "true" *) logic [1:0] 		    MemRWM;
   (* mark_debug = "true" *) logic 		    InstrValidM;
   logic 		    InstrMisalignedFaultM;

pipelined/testbench/tests.vh

@@ -240,7 +240,6 @@ string imperas32f[] = '{
 
   string imperas64f[] = '{
     `IMPERASTEST,
-		"rv64i_m/F/FMUL-S-DYN-RDN-01", "002010",  // ***extra
 		"rv64i_m/F/FADD-S-DYN-RDN-01", "002010",
 		"rv64i_m/F/FADD-S-DYN-RMM-01", "002010",
 		"rv64i_m/F/FADD-S-DYN-RNE-01", "002010",
@@ -1283,7 +1282,7 @@ string imperas32f[] = '{
     "rv32i_m/F/feq_b1-01", "6220",
     "rv32i_m/F/feq_b19-01", "a190",
     "rv32i_m/F/fle_b1-01", "6220",
-    "rv32i_m/F/fle_b19-01", "a190", // looks fine to me is the actual input value supposed to be infinity?
+    "rv32i_m/F/fle_b19-01", "a190",
     "rv32i_m/F/flt_b1-01", "6220",
     "rv32i_m/F/flt_b19-01", "8ee0", 
     "rv32i_m/F/flw-align-01", "2010",
@@ -1298,7 +1297,7 @@ string imperas32f[] = '{
     "rv32i_m/F/fmadd_b4-01", "3700",
     "rv32i_m/F/fmadd_b5-01", "3ac0",
     "rv32i_m/F/fmadd_b6-01", "3700",
-    //"rv32i_m/F/fmadd_b7-01", "d7f0", // input values aren't even in the memfile are being used in the test; didn't run even with fixed memfile
+    "rv32i_m/F/fmadd_b7-01", "37f0",
     "rv32i_m/F/fmadd_b8-01", "13f30", 
     "rv32i_m/F/fmax_b1-01", "7220",
     "rv32i_m/F/fmax_b19-01", "9e00",
@@ -1355,7 +1354,7 @@ string imperas32f[] = '{
     "rv32i_m/F/fnmsub_b17-01", "39d0",
     "rv32i_m/F/fnmsub_b18-01", "4d10", 
     "rv32i_m/F/fnmsub_b2-01", "4d60",
-    //"rv32i_m/F/fnmsub_b3-01", "4df0", // inputs that don't exist in memfile
+    "rv32i_m/F/fnmsub_b3-01", "d4f0",
     "rv32i_m/F/fnmsub_b4-01", "3700",
     "rv32i_m/F/fnmsub_b5-01", "3ac0",
     "rv32i_m/F/fnmsub_b6-01", "3700",