From b3ebce0365b0847e0385856c935a650b0031e478 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 6 Jan 2022 23:03:20 +0000 Subject: [PATCH 1/4] some FPU test fixes --- addins/riscv-arch-test | 2 +- pipelined/regression/Makefile | 2 +- pipelined/regression/sim-wally | 2 +- pipelined/regression/sim-wally-batch | 2 +- pipelined/src/fpu/fma.sv | 10 +++------- pipelined/testbench/tests.vh | 6 +++--- 6 files changed, 10 insertions(+), 14 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile index 4dce61abb..ecebb246b 100644 --- a/pipelined/regression/Makefile +++ b/pipelined/regression/Makefile @@ -23,4 +23,4 @@ make all: # Link Linux test vectors (fix this later***) #cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh - \ No newline at end of file + diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index 51c8b3edc..a7dffc9ed 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv64gc arch64d" +vsim -do "do wally-pipelined.do rv32gc arch32f" diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch index 52b95c0ca..7db25e6cf 100755 --- a/pipelined/regression/sim-wally-batch +++ b/pipelined/regression/sim-wally-batch @@ -1,3 +1,3 @@ vsim -c < Date: Thu, 6 Jan 2022 23:03:29 +0000 Subject: [PATCH 2/4] Fixed multiplier nan boxing bug --- pipelined/src/fpu/fpu.sv | 8 +++++--- pipelined/src/fpu/unpacking.sv | 3 +-- pipelined/src/wally/wallypipelinedhart.sv | 4 ++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index c09d81a17..f0730d98d 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -125,7 +125,8 @@ module fpu ( logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit logic load_preload; // enable for FF on fpdivsqrt logic [63:0] AlignedSrcAE; // align SrcA to the floating point format - + logic [63:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed + // DECODE STAGE // calculate FP control signals @@ -163,8 +164,9 @@ module fpu ( {2'b0, {10{1'b1}}, 52'b0}, {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)}, FSrcYE); // Force Z to be 0 for multiply instructions - // Force Z to be 0 for multiply instructions - mux3 #(64) fzmulmux (FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); + // Force Z to be 0 for multiply instructions + mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero + mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); // unpacking unit // - splits FP inputs into their various parts diff --git a/pipelined/src/fpu/unpacking.sv b/pipelined/src/fpu/unpacking.sv index b61dd8315..78a4d7446 100644 --- a/pipelined/src/fpu/unpacking.sv +++ b/pipelined/src/fpu/unpacking.sv @@ -22,11 +22,10 @@ module unpacking ( logic XFracZero, YFracZero, ZFracZero; // input fraction zero logic XExpZero, YExpZero, ZExpZero; // input exponent zero logic YExpMaxE, ZExpMaxE; // input exponent all 1s - logic XDoubleNaN, YDoubleNaN, ZDoubleNaN; logic [31:0] XFloat, YFloat, ZFloat; // Bottom half or NaN, if RV64 and not properly NaN boxed // Determine if number is NaN as double precision to check single precision NaN boxing - if (`XLEN==32) begin // eventually this should change to FLEN when RV32f has FLEN=32 + if (`F_SUPPORTED & ~`D_SUPPORTED) begin // eventually this should change to FLEN when FLEN isn't hardwared to 64 assign XFloat = X[31:0]; assign YFloat = Y[31:0]; assign ZFloat = Z[31:0]; diff --git a/pipelined/src/wally/wallypipelinedhart.sv b/pipelined/src/wally/wallypipelinedhart.sv index 59ba0aee8..5c931d027 100644 --- a/pipelined/src/wally/wallypipelinedhart.sv +++ b/pipelined/src/wally/wallypipelinedhart.sv @@ -68,8 +68,8 @@ module wallypipelinedhart ( (* mark_debug = "true" *) logic [31:0] InstrM; logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] CSRReadValW, MulDivResultW; - logic [`XLEN-1:0] PrivilegedNextPCM; + logic [`XLEN-1:0] CSRReadValW, MulDivResultW; + logic [`XLEN-1:0] PrivilegedNextPCM; (* mark_debug = "true" *) logic [1:0] MemRWM; (* mark_debug = "true" *) logic InstrValidM; logic InstrMisalignedFaultM; From fc4db84bbca7297a10658a0dc4e39ed54e489aab Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 6 Jan 2022 23:04:30 +0000 Subject: [PATCH 3/4] Makefile make allclean --- pipelined/regression/Makefile | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile index 4dce61abb..8b94aaec1 100644 --- a/pipelined/regression/Makefile +++ b/pipelined/regression/Makefile @@ -1,3 +1,7 @@ +make allclean: + make clean + make all + make clean: make clean -C ../../addins/riscv-arch-test make clean -C ../../tests/wally-riscv-arch-test @@ -15,7 +19,9 @@ make all: cd ../../tests/wally-riscv-arch-test; elf2hex.sh # ***extractFunctionRadix - # Only compile Imperas tests if they are installed + # Only compile Imperas tests if they are installed locally. + # They are usually a symlink to $RISCV/imperas-riscv-tests and only + # get compiled there manually during installation # make -C ../../addins/imperas-riscv-tests # make -C ../../addins/imperas-riscv-tests XLEN=64 # cd ../../addins/imperas-riscv-tests; elf2hex.sh From 08231d4e66544918866efab66d1f4ee586caa4ca Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 6 Jan 2022 23:07:22 +0000 Subject: [PATCH 4/4] Tests cleanup: --- pipelined/testbench/tests.vh | 1 - 1 file changed, 1 deletion(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 6134f16d6..a7289d6e4 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -240,7 +240,6 @@ string imperas32f[] = '{ string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", // ***extra "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", "rv64i_m/F/FADD-S-DYN-RNE-01", "002010",