From 8edc4057ed9cd5b6e740dd944650f59040c8d1c6 Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Sat, 25 May 2024 23:10:09 -0700 Subject: [PATCH 1/4] compilable tests generating for loaditypes[lb, lh, lw, ld, lbu, lhu, lwu] --- Makefile | 1 + tests/testgen/covergen.py | 38 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 24d531917..b78bb689d 100644 --- a/Makefile +++ b/Makefile @@ -89,6 +89,7 @@ riscvdv_functcov: combine_functcov: mkdir -p ${SIM}/questa/functcov + mkdir -p ${SIM}/questa/functcov_logs cd ${SIM}/questa/functcov && rm -rf * run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 44a0eea4c..03edc2f90 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -31,6 +31,23 @@ def signedImm12(imm): imm = imm - 0x1000 return str(imm) +def signedImm20(imm): + imm = imm % pow(2, 20) + if (imm & 0x80000): + imm = imm - 0x100000 + return str(imm) + +''' +rtype = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and", + "addw", "subw", "sllw", "srlw", "sraw" + "mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu", + "mulw", "divw", "divuw", "remw", "remuw"] +loaditype = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] +shiftitype = ["slli", "srli", "srai"] +itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"] +stypes = ["sb", "sh", "sw", "sd"] +btypes = ["beq", "bne", "blt", "bge", "bltu", "bgeu"] +''' def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen): lines = "\n# Testcase " + str(desc) + "\n" if (rs1val < 0): @@ -48,6 +65,20 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor elif (test in itype): lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n" + elif (test in loaditype): + ''' + auipc s9,0x2 + addi s9,s9,-448 # 80002800 + lw a4,-2048(s9) + ''' + lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n" + lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1 \n" + lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" + #print("Error: %s type not implemented yet" % test) + elif (test in stypes): + print("Error: %s type not implemented yet" % test) + elif (test in btypes): + print("Error: %s type not implemented yet" % test) else: pass #print("Error: %s type not implemented yet" % test) @@ -130,12 +161,12 @@ def make_rd_maxvals(test, storecmd, xlen): def make_rd_rs1_eqval(test, storecmd, xlen): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rdm_rs1_eqval (Test rs1 = rd = " + hex(rs1val) + ")" - writeCovVector(desc, rs1, 0, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, 0, rd, rdval, rs2val, immval, rdval, test, storecmd, xlen) def make_rd_rs2_eqval(test, storecmd, xlen): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rd_rs2_eqval (Test rs2 = rd = " + hex(rs2val) + ")" - writeCovVector(desc, 0, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, 0, rs2, rd, rs1val, rdval, immval, rdval, test, storecmd, xlen) def make_rs1_rs2_eqval(test, storecmd, xlen): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() @@ -238,6 +269,7 @@ def getcovergroups(coverdefdir, coverfiles): if (m): coverpoints[curinstr].append(m.group(1)) f.close() + print(coverpoints) return coverpoints ################################## @@ -258,6 +290,8 @@ shiftitype = ["slli", "srli", "srai"] itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"] stypes = ["sb", "sh", "sw", "sd"] btypes = ["beq", "bne", "blt", "bge", "bltu", "bgeu"] +# TODO: auipc missing, check whatelse is missing in ^these^ types + coverpoints = getcovergroups(coverdefdir, coverfiles) author = "David_Harris@hmc.edu" From 29d7cd56634caab652490b2d85c8a95cccf23280 Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Sat, 25 May 2024 23:16:07 -0700 Subject: [PATCH 2/4] unwanted comments --- tests/testgen/covergen.py | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 03edc2f90..53313d9ab 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -37,17 +37,6 @@ def signedImm20(imm): imm = imm - 0x100000 return str(imm) -''' -rtype = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and", - "addw", "subw", "sllw", "srlw", "sraw" - "mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu", - "mulw", "divw", "divuw", "remw", "remuw"] -loaditype = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] -shiftitype = ["slli", "srli", "srai"] -itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"] -stypes = ["sb", "sh", "sw", "sd"] -btypes = ["beq", "bne", "blt", "bge", "bltu", "bgeu"] -''' def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen): lines = "\n# Testcase " + str(desc) + "\n" if (rs1val < 0): @@ -66,15 +55,9 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n" elif (test in loaditype): - ''' - auipc s9,0x2 - addi s9,s9,-448 # 80002800 - lw a4,-2048(s9) - ''' lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n" lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1 \n" lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" - #print("Error: %s type not implemented yet" % test) elif (test in stypes): print("Error: %s type not implemented yet" % test) elif (test in btypes): From 1bf9b1395325e33cdaee850fd5ee2fb0d187eef3 Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Sun, 26 May 2024 03:47:08 -0700 Subject: [PATCH 3/4] added some sb types --- tests/testgen/covergen.py | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 53313d9ab..233fa3495 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -54,14 +54,25 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor elif (test in itype): lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n" - elif (test in loaditype): + elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n" lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1 \n" lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" - elif (test in stypes): - print("Error: %s type not implemented yet" % test) - elif (test in btypes): - print("Error: %s type not implemented yet" % test) + elif (test in stypes):#["sb", "sh", "sw", "sd"] + #lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" + lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n" + #print("Error: %s type not implemented yet" % test) + elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"] + if (randint(1,100) > 50): + rs1val = rs2val + lines = lines + "# same values in both registers\n" + lines = lines + "nop \n" + lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value that should get changed\n" + lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value that should get changed\n" + lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n" + lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n" + lines = lines + "nop \nnop \nnop \nnop \nnop \n" + #print("Error: %s type not implemented yet" % test) else: pass #print("Error: %s type not implemented yet" % test) From 997b5901cc47f2a6237c7be6bef8d7c16ddc8e2a Mon Sep 17 00:00:00 2001 From: Quswar Abid Date: Mon, 27 May 2024 04:27:50 -0700 Subject: [PATCH 4/4] sb types are all passing, loaditypes are not! --- tests/testgen/covergen.py | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 233fa3495..5a01b7c62 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -66,13 +66,14 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor if (randint(1,100) > 50): rs1val = rs2val lines = lines + "# same values in both registers\n" - lines = lines + "nop \n" + lines = lines + "nop\n" lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value that should get changed\n" lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value that should get changed\n" lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n" + lines = lines + "addi x0, x1, 1\n" lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n" - lines = lines + "nop \nnop \nnop \nnop \nnop \n" - #print("Error: %s type not implemented yet" % test) + lines = lines + "addi x0, x2, 2\n" + lines = lines + "nop\nnop\nnop\nnop\nnop\n" else: pass #print("Error: %s type not implemented yet" % test) @@ -232,17 +233,37 @@ def write_tests(coverpoints, test, storecmd, xlen): elif (coverpoint == "cp_rs2_sign"): make_rs2_sign(test, storecmd, xlen) elif (coverpoint == "cp_rd_sign"): - pass # hope already covered by rd_maxvals + pass #TODO hope already covered by rd_maxvals elif (coverpoint == "cr_rs1_rs2"): make_cr_rs1_rs2_sign(test, storecmd, xlen) elif (coverpoint == "cp_rs1_toggle"): - pass # toggle not needed and seems to be covered by other things + pass #TODO toggle not needed and seems to be covered by other things elif (coverpoint == "cp_rs2_toggle"): - pass # toggle not needed and seems to be covered by other things + pass #TODO toggle not needed and seems to be covered by other things elif (coverpoint == "cp_rd_toggle"): - pass # toggle not needed and seems to be covered by other things + pass #TODO toggle not needed and seems to be covered by other things elif (coverpoint == "cp_gpr_hazard"): - pass # not yet implemented + pass #TODO not yet implemented + elif (coverpoint == "cp_imm_sign"): + pass #TODO + elif (coverpoint == "cr_rs1_imm"): + pass #TODO (not if crosses are not needed) + elif (coverpoint == "cp_imm_ones_zeros"): + pass #TODO + elif (coverpoint == "cp_mem_hazard"): + pass #TODO + elif (coverpoint == "cp_imm_zero"): + pass #TODO + elif (coverpoint == "cp_mem_unaligned"): + pass #TODO + elif (coverpoint == "cp_offset"): + pass #TODO + elif (coverpoint == "cr_nord_rs1_rs2"): + pass #TODO (not if crosses are not needed) + elif (coverpoint == "cp_imm_shift"): + pass #TODO + elif (coverpoint == "cp_rd_boolean"): + pass #TODO else: print("Warning: " + coverpoint + " not implemented yet for " + test)