Fixed bug.

It was possible for DTLBMissM to prevent a dcache flush.

bugs.txt

@@ -0,0 +1,2 @@
+1. [X] Cache is suppressing d cache flush if there is a dtlb miss.
+   1. Fixed by disabling mmu's address translation on flush.

pipelined/src/cache/cachefsm.sv

@@ -113,7 +113,7 @@ module cachefsm
   // using both IgnoreRequestTLB and IgnoreRequestTrapM.  Otherwise we can just use IgnoreRequestTLB.
 
   // need to re organize all of these.  Low priority though.
-  assign DoFlush = FlushCache & ~IgnoreRequest;
+  assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation.
   assign AMO = Atomic[1] & (&RW);
   assign DoAMO = AMO & ~IgnoreRequest; 
   assign DoAMOHit = DoAMO & CacheHit;
@@ -224,8 +224,8 @@ module cachefsm
                          (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag);
   assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) |
                          (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
-  assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush);
-  assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR);
+  assign FlushAdrCntRst = (CurrState == STATE_READY);
+  assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR);
   // Bus interface controls
   assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss));
   assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |

pipelined/src/lsu/lsu.sv

@@ -139,7 +139,7 @@ module lsu (
 
     mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
     dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
-      .PrivilegeModeW, .DisableTranslation(SelHPTW),
+      .PrivilegeModeW, .DisableTranslation(SelHPTW | FlushDCacheM),
       .PAdr(PreLSUPAdrM),
       .VAdr(IEUAdrM),
       .Size(LSUFunct3M[1:0]),