From c8e68849263f65be6456be809a711448979718ea Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Feb 2022 14:00:01 -0600 Subject: [PATCH] Fixed bug. It was possible for DTLBMissM to prevent a dcache flush. --- bugs.txt | 2 ++ pipelined/src/cache/cachefsm.sv | 10 +++++----- pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-) create mode 100644 bugs.txt diff --git a/bugs.txt b/bugs.txt new file mode 100644 index 000000000..f2a22fd81 --- /dev/null +++ b/bugs.txt @@ -0,0 +1,2 @@ +1. [X] Cache is suppressing d cache flush if there is a dtlb miss. + 1. Fixed by disabling mmu's address translation on flush. diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 4a22b9cb0..0fd7f5d51 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -113,8 +113,8 @@ module cachefsm // using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB. // need to re organize all of these. Low priority though. - assign DoFlush = FlushCache & ~IgnoreRequest; - assign AMO = Atomic[1] & (&RW); + assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. + assign AMO = Atomic[1] & (&RW); assign DoAMO = AMO & ~IgnoreRequest; assign DoAMOHit = DoAMO & CacheHit; assign DoAMOMiss = DoAMO & ~CacheHit; @@ -188,7 +188,7 @@ module cachefsm // com back to CPU assign CacheCommitted = CurrState != STATE_READY; - assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) | + assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) | @@ -224,8 +224,8 @@ module cachefsm (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag); assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); - assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush); - assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR); + assign FlushAdrCntRst = (CurrState == STATE_READY); + assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss)); assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1151cd903..f6c8ec47d 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -139,7 +139,7 @@ module lsu ( mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .PrivilegeModeW, .DisableTranslation(SelHPTW), + .PrivilegeModeW, .DisableTranslation(SelHPTW | FlushDCacheM), .PAdr(PreLSUPAdrM), .VAdr(IEUAdrM), .Size(LSUFunct3M[1:0]),