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Noted possible bug with endianness during hptw.

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Minor complexity reduction in interlockfsm.  I think there is a lot of room to simplify.
This commit is contained in:
Ross Thompson 2022-10-19 12:20:19 -05:00
parent a53ca5c99f
commit c6a9b17918
2 changed files with 3 additions and 2 deletions
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4
pipelined/src/lsu/interlockfsm.sv
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@ -81,7 +81,7 @@ module interlockfsm(
else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS; else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS;
else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS; else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS;
else InterlockNextState = STATE_T0_READY; else InterlockNextState = STATE_T0_READY;
STATE_T1_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T1_REPLAY; STATE_T1_REPLAY: if(0) InterlockNextState = STATE_T1_REPLAY;
else InterlockNextState = STATE_T0_READY; else InterlockNextState = STATE_T0_READY;
STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T1_REPLAY; STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T1_REPLAY;
else InterlockNextState = STATE_T3_DTLB_MISS; else InterlockNextState = STATE_T3_DTLB_MISS;
@ -98,7 +98,7 @@ module interlockfsm(
assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF) & ~TrapM) | assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF) & ~TrapM) |
(InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
assign SelReplayMemE = (InterlockCurrState == STATE_T1_REPLAY & DCacheStallM) | assign SelReplayMemE = (InterlockCurrState == STATE_T1_REPLAY) |
(InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) | (InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) |
(InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF); (InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF);
assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |

1
pipelined/src/privileged/csrsr.sv
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@ -126,6 +126,7 @@ module csrsr (
else if (PrivilegeModeW == `M_MODE & STATUS_MPRV) EndiannessPrivMode = STATUS_MPP; else if (PrivilegeModeW == `M_MODE & STATUS_MPRV) EndiannessPrivMode = STATUS_MPP;
else EndiannessPrivMode = PrivilegeModeW; else EndiannessPrivMode = PrivilegeModeW;
// *** Ross possible BUG: HPTW needs to match the endianness of SBE not xBE.
case (EndiannessPrivMode) case (EndiannessPrivMode)
`M_MODE: BigEndianM = STATUS_MBE; `M_MODE: BigEndianM = STATUS_MBE;
`S_MODE: BigEndianM = STATUS_SBE; `S_MODE: BigEndianM = STATUS_SBE;