From c6a9b1791833e7733d539474c6f8c22c76238bcb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Oct 2022 12:20:19 -0500 Subject: [PATCH] Noted possible bug with endianness during hptw. Minor complexity reduction in interlockfsm. I think there is a lot of room to simplify. --- pipelined/src/lsu/interlockfsm.sv | 4 ++-- pipelined/src/privileged/csrsr.sv | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/pipelined/src/lsu/interlockfsm.sv b/pipelined/src/lsu/interlockfsm.sv index 7f0dd395d..cb60596dc 100644 --- a/pipelined/src/lsu/interlockfsm.sv +++ b/pipelined/src/lsu/interlockfsm.sv @@ -81,7 +81,7 @@ module interlockfsm( else if(ToITLBMiss) InterlockNextState = STATE_T5_ITLB_MISS; else if(ToBoth) InterlockNextState = STATE_T7_DITLB_MISS; else InterlockNextState = STATE_T0_READY; - STATE_T1_REPLAY: if(DCacheStallM) InterlockNextState = STATE_T1_REPLAY; + STATE_T1_REPLAY: if(0) InterlockNextState = STATE_T1_REPLAY; else InterlockNextState = STATE_T0_READY; STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T1_REPLAY; else InterlockNextState = STATE_T3_DTLB_MISS; @@ -98,7 +98,7 @@ module interlockfsm( assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF) & ~TrapM) | (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | (InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS); - assign SelReplayMemE = (InterlockCurrState == STATE_T1_REPLAY & DCacheStallM) | + assign SelReplayMemE = (InterlockCurrState == STATE_T1_REPLAY) | (InterlockCurrState == STATE_T3_DTLB_MISS & DTLBWriteM) | (InterlockCurrState == STATE_T5_ITLB_MISS & ITLBWriteF); assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) | diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index c4f841959..3209dd414 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -126,6 +126,7 @@ module csrsr ( else if (PrivilegeModeW == `M_MODE & STATUS_MPRV) EndiannessPrivMode = STATUS_MPP; else EndiannessPrivMode = PrivilegeModeW; + // *** Ross possible BUG: HPTW needs to match the endianness of SBE not xBE. case (EndiannessPrivMode) `M_MODE: BigEndianM = STATUS_MBE; `S_MODE: BigEndianM = STATUS_SBE;