From c644e940c2d1102f91090dd7b68a1923e6344580 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Sep 2021 11:22:54 -0500 Subject: [PATCH] Updated Imperas test bench to work with the SDC reader. --- wally-pipelined/regression/wave.do | 25 ++++--------------- wally-pipelined/src/sdc/SDC.sv | 2 +- wally-pipelined/src/sdc/tb/run_tb.do | 2 +- wally-pipelined/src/uncore/uncore.sv | 6 +++-- .../sdc/tb => testbench/common}/sdModel.sv | 0 .../sdc/tb => testbench/common}/sd_crc_16.sv | 0 .../sdc/tb => testbench/common}/sd_crc_7.sv | 0 .../sdc/tb => testbench/common}/sd_defines.h | 0 .../testbench/testbench-imperas.sv | 12 +++++++++ 9 files changed, 23 insertions(+), 24 deletions(-) rename wally-pipelined/{src/sdc/tb => testbench/common}/sdModel.sv (100%) rename wally-pipelined/{src/sdc/tb => testbench/common}/sd_crc_16.sv (100%) rename wally-pipelined/{src/sdc/tb => testbench/common}/sd_crc_7.sv (100%) rename wally-pipelined/{src/sdc/tb => testbench/common}/sd_defines.h (100%) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index d176c63f1..da01ea21a 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -516,25 +516,10 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -color Gold /testbench/dut/hart/lsu/dcache/subwordread/offset0 -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1 -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2 -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3 -add wave -noupdate /testbench/dut/hart/ExceptionM -add wave -noupdate /testbench/dut/hart/PendingInterruptM -add wave -noupdate /testbench/dut/hart/TrapM -add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF -add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF -add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu -add wave -noupdate /testbench/dut/hart/ifu/PCPF -add wave -noupdate /testbench/dut/hart/ifu/PCF -add wave -noupdate /testbench/dut/hart/ifu/immu/Translate -add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF -add wave -noupdate /testbench/dut/hart/ifu/icache/StallF -add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheMemReadData -add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF -add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF -add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn +add wave -noupdate -expand -group SDC -color Gold /testbench/dut/uncore/sdc/SDC/CurrState +add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/HCLK +add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/CLKGate +add wave -noupdate -expand -group SDC /testbench/dut/uncore/sdc/SDC/SDCCLK TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 6} {122378 ns} 0} quietly wave cursor active 1 @@ -552,4 +537,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {122227 ns} {122479 ns} +WaveRestoreZoom {122134 ns} {122622 ns} diff --git a/wally-pipelined/src/sdc/SDC.sv b/wally-pipelined/src/sdc/SDC.sv index 7167286e8..08fb72902 100644 --- a/wally-pipelined/src/sdc/SDC.sv +++ b/wally-pipelined/src/sdc/SDC.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" -`define SDCCLKDIV 2 +`define SDCCLKDIV 8'd2 module SDC (input logic HCLK, diff --git a/wally-pipelined/src/sdc/tb/run_tb.do b/wally-pipelined/src/sdc/tb/run_tb.do index a2d3ba382..e16a5b8cc 100644 --- a/wally-pipelined/src/sdc/tb/run_tb.do +++ b/wally-pipelined/src/sdc/tb/run_tb.do @@ -6,7 +6,7 @@ if [file exists work] { } vlib work -vlog +incdir+../../../config/rv64ic +incdir+../../../config/shared ../../../testbench/common/*.sv ../../*/*.sv sd_top_tb.sv sdModel.sv sd_crc_7.sv sd_crc_16.sv -suppress 2583 +vlog +incdir+../../../config/rv64ic +incdir+../../../config/shared ../../../testbench/common/*.sv ../../*/*.sv sd_top_tb.sv -suppress 2583 vopt -fsmdebug +acc -gDEBUG=1 work.sd_top_tb -o workopt vsim workopt -fsmdebug diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index bf9e46081..4524e656b 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -129,8 +129,10 @@ module uncore ( // interrupt to PLIC .SDCIntM ); - end else begin : uart - assign UARTSout = 0; assign UARTIntr = 0; + end else begin : sdc + assign SDCCLK = 0; + assign SDCCmdOut = 0; + assign SDCCmdOE = 0; end endgenerate diff --git a/wally-pipelined/src/sdc/tb/sdModel.sv b/wally-pipelined/testbench/common/sdModel.sv similarity index 100% rename from wally-pipelined/src/sdc/tb/sdModel.sv rename to wally-pipelined/testbench/common/sdModel.sv diff --git a/wally-pipelined/src/sdc/tb/sd_crc_16.sv b/wally-pipelined/testbench/common/sd_crc_16.sv similarity index 100% rename from wally-pipelined/src/sdc/tb/sd_crc_16.sv rename to wally-pipelined/testbench/common/sd_crc_16.sv diff --git a/wally-pipelined/src/sdc/tb/sd_crc_7.sv b/wally-pipelined/testbench/common/sd_crc_7.sv similarity index 100% rename from wally-pipelined/src/sdc/tb/sd_crc_7.sv rename to wally-pipelined/testbench/common/sd_crc_7.sv diff --git a/wally-pipelined/src/sdc/tb/sd_defines.h b/wally-pipelined/testbench/common/sd_defines.h similarity index 100% rename from wally-pipelined/src/sdc/tb/sd_defines.h rename to wally-pipelined/testbench/common/sd_defines.h diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 318140769..82aea2683 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -566,6 +566,10 @@ string tests32f[] = '{ logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; + logic SDCCLK; + tri1 SDCCmd; + tri1 [3:0] SDCDat; + // instantiate device to be tested assign GPIOPinsIn = 0; assign UARTSin = 1; @@ -582,6 +586,14 @@ string tests32f[] = '{ dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + // SD card model + + sdModel sdcard + (.sdClk(SDCCLK), + .cmd(SDCCmd), + .dat(SDCDat)); + + // initialize tests localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32); localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);